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Core/Src/stm32l4xx_it.c
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320
Core/Src/stm32l4xx_it.c
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/* USER CODE BEGIN Header */
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/**
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******************************************************************************
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* @file stm32l4xx_it.c
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* @brief Interrupt Service Routines.
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) 2021 STMicroelectronics.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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*/
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/* USER CODE END Header */
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/* Includes ------------------------------------------------------------------*/
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#include "main.h"
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#include "stm32l4xx_it.h"
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#include "FreeRTOS.h"
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#include "task.h"
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/* Private includes ----------------------------------------------------------*/
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/* USER CODE BEGIN Includes */
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/* USER CODE END Includes */
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/* Private typedef -----------------------------------------------------------*/
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/* USER CODE BEGIN TD */
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/* USER CODE END TD */
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/* Private define ------------------------------------------------------------*/
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/* USER CODE BEGIN PD */
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/* USER CODE END PD */
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/* Private macro -------------------------------------------------------------*/
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/* USER CODE BEGIN PM */
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/* USER CODE END PM */
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/* Private variables ---------------------------------------------------------*/
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/* USER CODE BEGIN PV */
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/* USER CODE END PV */
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/* Private function prototypes -----------------------------------------------*/
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/* USER CODE BEGIN PFP */
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/* USER CODE END PFP */
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/* Private user code ---------------------------------------------------------*/
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/* USER CODE BEGIN 0 */
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/* USER CODE END 0 */
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/* External variables --------------------------------------------------------*/
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extern DMA_HandleTypeDef hdma_adc1;
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extern ADC_HandleTypeDef hadc1;
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extern CAN_HandleTypeDef hcan1;
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extern DMA_HandleTypeDef hdma_spi1_rx;
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extern DMA_HandleTypeDef hdma_spi1_tx;
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extern SPI_HandleTypeDef hspi1;
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/* USER CODE BEGIN EV */
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/* USER CODE END EV */
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/******************************************************************************/
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/* Cortex-M4 Processor Interruption and Exception Handlers */
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/******************************************************************************/
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/**
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* @brief This function handles Non maskable interrupt.
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*/
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void NMI_Handler(void)
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{
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/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
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/* USER CODE END NonMaskableInt_IRQn 0 */
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/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
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while (1)
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{
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}
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/* USER CODE END NonMaskableInt_IRQn 1 */
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}
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/**
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* @brief This function handles Hard fault interrupt.
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*/
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void HardFault_Handler(void)
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{
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/* USER CODE BEGIN HardFault_IRQn 0 */
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/* USER CODE END HardFault_IRQn 0 */
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while (1)
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{
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/* USER CODE BEGIN W1_HardFault_IRQn 0 */
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/* USER CODE END W1_HardFault_IRQn 0 */
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}
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}
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/**
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* @brief This function handles Memory management fault.
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*/
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void MemManage_Handler(void)
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{
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/* USER CODE BEGIN MemoryManagement_IRQn 0 */
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/* USER CODE END MemoryManagement_IRQn 0 */
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while (1)
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{
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/* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
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/* USER CODE END W1_MemoryManagement_IRQn 0 */
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}
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}
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/**
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* @brief This function handles Prefetch fault, memory access fault.
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*/
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void BusFault_Handler(void)
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{
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/* USER CODE BEGIN BusFault_IRQn 0 */
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/* USER CODE END BusFault_IRQn 0 */
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while (1)
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{
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/* USER CODE BEGIN W1_BusFault_IRQn 0 */
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/* USER CODE END W1_BusFault_IRQn 0 */
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}
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}
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/**
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* @brief This function handles Undefined instruction or illegal state.
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*/
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void UsageFault_Handler(void)
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{
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/* USER CODE BEGIN UsageFault_IRQn 0 */
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/* USER CODE END UsageFault_IRQn 0 */
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while (1)
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{
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/* USER CODE BEGIN W1_UsageFault_IRQn 0 */
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/* USER CODE END W1_UsageFault_IRQn 0 */
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}
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}
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/**
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* @brief This function handles Debug monitor.
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*/
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void DebugMon_Handler(void)
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{
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/* USER CODE BEGIN DebugMonitor_IRQn 0 */
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/* USER CODE END DebugMonitor_IRQn 0 */
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/* USER CODE BEGIN DebugMonitor_IRQn 1 */
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/* USER CODE END DebugMonitor_IRQn 1 */
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}
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/**
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* @brief This function handles System tick timer.
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*/
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void SysTick_Handler(void)
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{
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/* USER CODE BEGIN SysTick_IRQn 0 */
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/* USER CODE END SysTick_IRQn 0 */
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HAL_IncTick();
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#if (INCLUDE_xTaskGetSchedulerState == 1 )
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if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED)
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{
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#endif /* INCLUDE_xTaskGetSchedulerState */
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xPortSysTickHandler();
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#if (INCLUDE_xTaskGetSchedulerState == 1 )
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}
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#endif /* INCLUDE_xTaskGetSchedulerState */
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/* USER CODE BEGIN SysTick_IRQn 1 */
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/* USER CODE END SysTick_IRQn 1 */
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}
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/******************************************************************************/
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/* STM32L4xx Peripheral Interrupt Handlers */
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/* Add here the Interrupt Handlers for the used peripherals. */
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/* For the available peripheral interrupt handler names, */
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/* please refer to the startup file (startup_stm32l4xx.s). */
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/******************************************************************************/
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/**
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* @brief This function handles DMA1 channel2 global interrupt.
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*/
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void DMA1_Channel2_IRQHandler(void)
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{
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/* USER CODE BEGIN DMA1_Channel2_IRQn 0 */
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/* USER CODE END DMA1_Channel2_IRQn 0 */
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HAL_DMA_IRQHandler(&hdma_spi1_rx);
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/* USER CODE BEGIN DMA1_Channel2_IRQn 1 */
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/* USER CODE END DMA1_Channel2_IRQn 1 */
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}
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/**
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* @brief This function handles DMA1 channel3 global interrupt.
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*/
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void DMA1_Channel3_IRQHandler(void)
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{
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/* USER CODE BEGIN DMA1_Channel3_IRQn 0 */
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/* USER CODE END DMA1_Channel3_IRQn 0 */
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HAL_DMA_IRQHandler(&hdma_spi1_tx);
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/* USER CODE BEGIN DMA1_Channel3_IRQn 1 */
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/* USER CODE END DMA1_Channel3_IRQn 1 */
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}
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/**
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* @brief This function handles ADC1 global interrupt.
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*/
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void ADC1_IRQHandler(void)
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{
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/* USER CODE BEGIN ADC1_IRQn 0 */
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/* USER CODE END ADC1_IRQn 0 */
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HAL_ADC_IRQHandler(&hadc1);
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/* USER CODE BEGIN ADC1_IRQn 1 */
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/* USER CODE END ADC1_IRQn 1 */
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}
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/**
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* @brief This function handles CAN1 TX interrupt.
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*/
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void CAN1_TX_IRQHandler(void)
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{
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/* USER CODE BEGIN CAN1_TX_IRQn 0 */
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/* USER CODE END CAN1_TX_IRQn 0 */
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HAL_CAN_IRQHandler(&hcan1);
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/* USER CODE BEGIN CAN1_TX_IRQn 1 */
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/* USER CODE END CAN1_TX_IRQn 1 */
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}
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/**
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* @brief This function handles CAN1 RX0 interrupt.
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*/
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void CAN1_RX0_IRQHandler(void)
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{
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/* USER CODE BEGIN CAN1_RX0_IRQn 0 */
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/* USER CODE END CAN1_RX0_IRQn 0 */
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HAL_CAN_IRQHandler(&hcan1);
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/* USER CODE BEGIN CAN1_RX0_IRQn 1 */
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/* USER CODE END CAN1_RX0_IRQn 1 */
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}
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/**
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* @brief This function handles CAN1 RX1 interrupt.
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*/
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void CAN1_RX1_IRQHandler(void)
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{
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/* USER CODE BEGIN CAN1_RX1_IRQn 0 */
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/* USER CODE END CAN1_RX1_IRQn 0 */
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HAL_CAN_IRQHandler(&hcan1);
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/* USER CODE BEGIN CAN1_RX1_IRQn 1 */
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/* USER CODE END CAN1_RX1_IRQn 1 */
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}
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/**
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* @brief This function handles CAN1 SCE interrupt.
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*/
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void CAN1_SCE_IRQHandler(void)
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{
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/* USER CODE BEGIN CAN1_SCE_IRQn 0 */
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/* USER CODE END CAN1_SCE_IRQn 0 */
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HAL_CAN_IRQHandler(&hcan1);
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/* USER CODE BEGIN CAN1_SCE_IRQn 1 */
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/* USER CODE END CAN1_SCE_IRQn 1 */
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}
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/**
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* @brief This function handles SPI1 global interrupt.
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*/
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void SPI1_IRQHandler(void)
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{
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/* USER CODE BEGIN SPI1_IRQn 0 */
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/* USER CODE END SPI1_IRQn 0 */
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HAL_SPI_IRQHandler(&hspi1);
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/* USER CODE BEGIN SPI1_IRQn 1 */
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/* USER CODE END SPI1_IRQn 1 */
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}
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/**
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* @brief This function handles DMA2 channel3 global interrupt.
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*/
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void DMA2_Channel3_IRQHandler(void)
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{
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/* USER CODE BEGIN DMA2_Channel3_IRQn 0 */
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/* USER CODE END DMA2_Channel3_IRQn 0 */
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HAL_DMA_IRQHandler(&hdma_adc1);
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/* USER CODE BEGIN DMA2_Channel3_IRQn 1 */
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/* USER CODE END DMA2_Channel3_IRQn 1 */
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}
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/* USER CODE BEGIN 1 */
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/* USER CODE END 1 */
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