From 7cadcdbc28d0fea79cab4e0273a4e7a3078ea167 Mon Sep 17 00:00:00 2001 From: pique_n Date: Tue, 13 Dec 2022 14:30:40 +0100 Subject: [PATCH] add first rev of eeprom and ref voltage in varhandler --- .mxproject | 4 +- .vscode/c_cpp_properties.json | 2 + .vscode/settings.json | 3 +- Core/Application/MAIN_MainApplication.c | 20 +- Core/Application/VARH_VariableHandler.c | 58 + Core/Application/VARH_VariableHandler.h | 4 + Core/Drivers/ANPI_AnalogPortsIn.c | 17 +- Core/Drivers/ANPI_AnalogPortsIn.h | 1 - Core/Drivers/ANPO_AnalogPortsOut.c | 21 +- Core/Drivers/ANPO_AnalogPortsOut.h | 1 - Core/Drivers/USFL_UserFlash.c | 243 +- Core/Drivers/USFL_UserFlash.h | 5 + Core/Inc/stm32l4xx_hal_conf.h | 2 +- Core/Src/main.c | 47 +- Core/Src/stm32l4xx_hal_msp.c | 47 +- Core/Src/stm32l4xx_it.c | 1 - .../Inc/stm32l4xx_hal_crc.h | 342 + .../Inc/stm32l4xx_hal_crc_ex.h | 150 + .../Inc/stm32l4xx_ll_bus.h | 1954 ++++++ .../Inc/stm32l4xx_ll_cortex.h | 637 ++ .../Inc/stm32l4xx_ll_crc.h | 467 ++ .../Inc/stm32l4xx_ll_crs.h | 785 +++ .../Inc/stm32l4xx_ll_dac.h | 1979 ++++++ .../Inc/stm32l4xx_ll_dma.h | 2430 +++++++ .../Inc/stm32l4xx_ll_dmamux.h | 1981 ++++++ .../Inc/stm32l4xx_ll_exti.h | 1359 ++++ .../Inc/stm32l4xx_ll_gpio.h | 1056 +++ .../Inc/stm32l4xx_ll_i2c.h | 2272 ++++++ .../Inc/stm32l4xx_ll_pwr.h | 1675 +++++ .../Inc/stm32l4xx_ll_rcc.h | 6233 +++++++++++++++++ .../Inc/stm32l4xx_ll_system.h | 1627 +++++ .../Inc/stm32l4xx_ll_utils.h | 329 + .../Src/stm32l4xx_hal_crc.c | 516 ++ .../Src/stm32l4xx_hal_crc_ex.c | 223 + Makefile | 6 +- Middlewares/ST/EEPROM_Emul/Core/eeprom_emul.c | 2071 ++++++ Middlewares/ST/EEPROM_Emul/Core/eeprom_emul.h | 142 + .../ST/EEPROM_Emul/Core/eeprom_emul_conf.h | 90 + .../ST/EEPROM_Emul/Core/eeprom_emul_types.h | 118 + .../Porting/STM32L4/flash_interface.c | 279 + .../Porting/STM32L4/flash_interface.h | 125 + PeltierControllerV1.srec | 1145 --- PeltierControllerV2.srec | 1337 ++++ PeltierControllerV3.ioc | 38 +- STM32-for-VSCode.config.yaml | 7 +- STM32Make.make | 10 +- convertHEXtoSREC.bat | 4 +- 47 files changed, 30486 insertions(+), 1377 deletions(-) create mode 100644 Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_crc.h create mode 100644 Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_crc_ex.h create mode 100644 Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_bus.h create mode 100644 Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_cortex.h create mode 100644 Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_crc.h create mode 100644 Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_crs.h create mode 100644 Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_dac.h create mode 100644 Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_dma.h create mode 100644 Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_dmamux.h create mode 100644 Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_exti.h create mode 100644 Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_gpio.h create mode 100644 Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_i2c.h create mode 100644 Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_pwr.h create mode 100644 Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_rcc.h create mode 100644 Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_system.h create mode 100644 Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_utils.h create mode 100644 Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_crc.c create mode 100644 Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_crc_ex.c create mode 100644 Middlewares/ST/EEPROM_Emul/Core/eeprom_emul.c create mode 100644 Middlewares/ST/EEPROM_Emul/Core/eeprom_emul.h create mode 100644 Middlewares/ST/EEPROM_Emul/Core/eeprom_emul_conf.h create mode 100644 Middlewares/ST/EEPROM_Emul/Core/eeprom_emul_types.h create mode 100644 Middlewares/ST/EEPROM_Emul/Porting/STM32L4/flash_interface.c create mode 100644 Middlewares/ST/EEPROM_Emul/Porting/STM32L4/flash_interface.h delete mode 100644 PeltierControllerV1.srec create mode 100644 PeltierControllerV2.srec diff --git a/.mxproject b/.mxproject index 9ddb7aa..feca652 100644 --- a/.mxproject +++ b/.mxproject @@ -1,5 +1,5 @@ [PreviousLibFiles] -LibFiles=Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_adc.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_ll_adc.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_adc_ex.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_def.h;Drivers\STM32L4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_i2c.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_i2c_ex.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_rcc.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_rcc_ex.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_flash.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_flash_ex.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_flash_ramfunc.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_gpio.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_gpio_ex.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_dma.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_dma_ex.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_pwr.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_pwr_ex.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_cortex.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_exti.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_can.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_dac.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_dac_ex.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_iwdg.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_spi.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_spi_ex.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_tim.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_tim_ex.h;Middlewares\Third_Party\FreeRTOS\Source\include\croutine.h;Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h;Middlewares\Third_Party\FreeRTOS\Source\include\event_groups.h;Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h;Middlewares\Third_Party\FreeRTOS\Source\include\list.h;Middlewares\Third_Party\FreeRTOS\Source\include\message_buffer.h;Middlewares\Third_Party\FreeRTOS\Source\include\mpu_prototypes.h;Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h;Middlewares\Third_Party\FreeRTOS\Source\include\portable.h;Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h;Middlewares\Third_Party\FreeRTOS\Source\include\queue.h;Middlewares\Third_Party\FreeRTOS\Source\include\semphr.h;Middlewares\Third_Party\FreeRTOS\Source\include\stack_macros.h;Middlewares\Third_Party\FreeRTOS\Source\include\StackMacros.h;Middlewares\Third_Party\FreeRTOS\Source\include\stream_buffer.h;Middlewares\Third_Party\FreeRTOS\Source\include\task.h;Middlewares\Third_Party\FreeRTOS\Source\include\timers.h;Middlewares\Third_Party\FreeRTOS\Source\include\atomic.h;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.h;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os.h;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\freertos_mpool.h;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\freertos_os2.h;Middlewares\Third_Party\FreeRTOS\Source\portable\GCC\ARM_CM4F\portmacro.h;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_adc.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_adc_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_i2c.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_i2c_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash_ramfunc.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_gpio.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_cortex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_exti.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_can.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dac.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dac_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_iwdg.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_spi.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_spi_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_tim.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_tim_ex.c;Middlewares\Third_Party\FreeRTOS\Source\croutine.c;Middlewares\Third_Party\FreeRTOS\Source\event_groups.c;Middlewares\Third_Party\FreeRTOS\Source\list.c;Middlewares\Third_Party\FreeRTOS\Source\queue.c;Middlewares\Third_Party\FreeRTOS\Source\stream_buffer.c;Middlewares\Third_Party\FreeRTOS\Source\tasks.c;Middlewares\Third_Party\FreeRTOS\Source\timers.c;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.c;Middlewares\Third_Party\FreeRTOS\Source\portable\MemMang\heap_4.c;Middlewares\Third_Party\FreeRTOS\Source\portable\GCC\ARM_CM4F\port.c;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_adc.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_ll_adc.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_adc_ex.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_def.h;Drivers\STM32L4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_i2c.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_i2c_ex.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_rcc.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_rcc_ex.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_flash.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_flash_ex.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_flash_ramfunc.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_gpio.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_gpio_ex.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_dma.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_dma_ex.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_pwr.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_pwr_ex.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_cortex.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_exti.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_can.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_dac.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_dac_ex.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_iwdg.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_spi.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_spi_ex.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_tim.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_tim_ex.h;Middlewares\Third_Party\FreeRTOS\Source\include\croutine.h;Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h;Middlewares\Third_Party\FreeRTOS\Source\include\event_groups.h;Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h;Middlewares\Third_Party\FreeRTOS\Source\include\list.h;Middlewares\Third_Party\FreeRTOS\Source\include\message_buffer.h;Middlewares\Third_Party\FreeRTOS\Source\include\mpu_prototypes.h;Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h;Middlewares\Third_Party\FreeRTOS\Source\include\portable.h;Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h;Middlewares\Third_Party\FreeRTOS\Source\include\queue.h;Middlewares\Third_Party\FreeRTOS\Source\include\semphr.h;Middlewares\Third_Party\FreeRTOS\Source\include\stack_macros.h;Middlewares\Third_Party\FreeRTOS\Source\include\StackMacros.h;Middlewares\Third_Party\FreeRTOS\Source\include\stream_buffer.h;Middlewares\Third_Party\FreeRTOS\Source\include\task.h;Middlewares\Third_Party\FreeRTOS\Source\include\timers.h;Middlewares\Third_Party\FreeRTOS\Source\include\atomic.h;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.h;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os.h;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\freertos_mpool.h;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\freertos_os2.h;Middlewares\Third_Party\FreeRTOS\Source\portable\GCC\ARM_CM4F\portmacro.h;Drivers\CMSIS\Device\ST\STM32L4xx\Include\stm32l432xx.h;Drivers\CMSIS\Device\ST\STM32L4xx\Include\stm32l4xx.h;Drivers\CMSIS\Device\ST\STM32L4xx\Include\system_stm32l4xx.h;Drivers\CMSIS\Device\ST\STM32L4xx\Source\Templates\system_stm32l4xx.c;Drivers\CMSIS\Include\cmsis_armcc.h;Drivers\CMSIS\Include\cmsis_armclang.h;Drivers\CMSIS\Include\cmsis_armclang_ltm.h;Drivers\CMSIS\Include\cmsis_compiler.h;Drivers\CMSIS\Include\cmsis_gcc.h;Drivers\CMSIS\Include\cmsis_iccarm.h;Drivers\CMSIS\Include\cmsis_version.h;Drivers\CMSIS\Include\core_armv81mml.h;Drivers\CMSIS\Include\core_armv8mbl.h;Drivers\CMSIS\Include\core_armv8mml.h;Drivers\CMSIS\Include\core_cm0.h;Drivers\CMSIS\Include\core_cm0plus.h;Drivers\CMSIS\Include\core_cm1.h;Drivers\CMSIS\Include\core_cm23.h;Drivers\CMSIS\Include\core_cm3.h;Drivers\CMSIS\Include\core_cm33.h;Drivers\CMSIS\Include\core_cm35p.h;Drivers\CMSIS\Include\core_cm4.h;Drivers\CMSIS\Include\core_cm7.h;Drivers\CMSIS\Include\core_sc000.h;Drivers\CMSIS\Include\core_sc300.h;Drivers\CMSIS\Include\mpu_armv7.h;Drivers\CMSIS\Include\mpu_armv8.h;Drivers\CMSIS\Include\tz_context.h; +LibFiles=Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_adc.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_ll_adc.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_adc_ex.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_def.h;Drivers\STM32L4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_i2c.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_i2c_ex.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_rcc.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_rcc_ex.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_ll_bus.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_ll_rcc.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_ll_crs.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_ll_system.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_ll_utils.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_flash.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_flash_ex.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_flash_ramfunc.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_gpio.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_gpio_ex.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_ll_gpio.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_dma.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_dma_ex.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_ll_dma.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_ll_dmamux.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_pwr.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_pwr_ex.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_ll_pwr.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_cortex.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_ll_cortex.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_exti.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_ll_exti.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_can.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_crc.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_crc_ex.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_ll_crc.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_dac.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_ll_dac.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_dac_ex.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_ll_i2c.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_iwdg.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_spi.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_spi_ex.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_tim.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_tim_ex.h;Middlewares\Third_Party\FreeRTOS\Source\include\croutine.h;Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h;Middlewares\Third_Party\FreeRTOS\Source\include\event_groups.h;Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h;Middlewares\Third_Party\FreeRTOS\Source\include\list.h;Middlewares\Third_Party\FreeRTOS\Source\include\message_buffer.h;Middlewares\Third_Party\FreeRTOS\Source\include\mpu_prototypes.h;Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h;Middlewares\Third_Party\FreeRTOS\Source\include\portable.h;Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h;Middlewares\Third_Party\FreeRTOS\Source\include\queue.h;Middlewares\Third_Party\FreeRTOS\Source\include\semphr.h;Middlewares\Third_Party\FreeRTOS\Source\include\stack_macros.h;Middlewares\Third_Party\FreeRTOS\Source\include\StackMacros.h;Middlewares\Third_Party\FreeRTOS\Source\include\stream_buffer.h;Middlewares\Third_Party\FreeRTOS\Source\include\task.h;Middlewares\Third_Party\FreeRTOS\Source\include\timers.h;Middlewares\Third_Party\FreeRTOS\Source\include\atomic.h;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.h;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os.h;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\freertos_mpool.h;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\freertos_os2.h;Middlewares\Third_Party\FreeRTOS\Source\portable\GCC\ARM_CM4F\portmacro.h;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_adc.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_adc_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_i2c.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_i2c_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash_ramfunc.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_gpio.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_cortex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_exti.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_can.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_crc.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_crc_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dac.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dac_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_iwdg.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_spi.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_spi_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_tim.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_tim_ex.c;Middlewares\Third_Party\FreeRTOS\Source\croutine.c;Middlewares\Third_Party\FreeRTOS\Source\event_groups.c;Middlewares\Third_Party\FreeRTOS\Source\list.c;Middlewares\Third_Party\FreeRTOS\Source\queue.c;Middlewares\Third_Party\FreeRTOS\Source\stream_buffer.c;Middlewares\Third_Party\FreeRTOS\Source\tasks.c;Middlewares\Third_Party\FreeRTOS\Source\timers.c;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.c;Middlewares\Third_Party\FreeRTOS\Source\portable\MemMang\heap_4.c;Middlewares\Third_Party\FreeRTOS\Source\portable\GCC\ARM_CM4F\port.c;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_adc.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_ll_adc.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_adc_ex.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_def.h;Drivers\STM32L4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_i2c.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_i2c_ex.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_rcc.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_rcc_ex.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_ll_bus.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_ll_rcc.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_ll_crs.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_ll_system.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_ll_utils.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_flash.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_flash_ex.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_flash_ramfunc.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_gpio.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_gpio_ex.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_ll_gpio.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_dma.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_dma_ex.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_ll_dma.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_ll_dmamux.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_pwr.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_pwr_ex.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_ll_pwr.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_cortex.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_ll_cortex.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_exti.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_ll_exti.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_can.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_crc.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_crc_ex.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_ll_crc.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_dac.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_ll_dac.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_dac_ex.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_ll_i2c.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_iwdg.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_spi.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_spi_ex.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_tim.h;Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_tim_ex.h;Middlewares\Third_Party\FreeRTOS\Source\include\croutine.h;Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h;Middlewares\Third_Party\FreeRTOS\Source\include\event_groups.h;Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h;Middlewares\Third_Party\FreeRTOS\Source\include\list.h;Middlewares\Third_Party\FreeRTOS\Source\include\message_buffer.h;Middlewares\Third_Party\FreeRTOS\Source\include\mpu_prototypes.h;Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h;Middlewares\Third_Party\FreeRTOS\Source\include\portable.h;Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h;Middlewares\Third_Party\FreeRTOS\Source\include\queue.h;Middlewares\Third_Party\FreeRTOS\Source\include\semphr.h;Middlewares\Third_Party\FreeRTOS\Source\include\stack_macros.h;Middlewares\Third_Party\FreeRTOS\Source\include\StackMacros.h;Middlewares\Third_Party\FreeRTOS\Source\include\stream_buffer.h;Middlewares\Third_Party\FreeRTOS\Source\include\task.h;Middlewares\Third_Party\FreeRTOS\Source\include\timers.h;Middlewares\Third_Party\FreeRTOS\Source\include\atomic.h;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.h;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os.h;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\freertos_mpool.h;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\freertos_os2.h;Middlewares\Third_Party\FreeRTOS\Source\portable\GCC\ARM_CM4F\portmacro.h;Drivers\CMSIS\Device\ST\STM32L4xx\Include\stm32l432xx.h;Drivers\CMSIS\Device\ST\STM32L4xx\Include\stm32l4xx.h;Drivers\CMSIS\Device\ST\STM32L4xx\Include\system_stm32l4xx.h;Drivers\CMSIS\Device\ST\STM32L4xx\Source\Templates\system_stm32l4xx.c;Drivers\CMSIS\Include\cmsis_armcc.h;Drivers\CMSIS\Include\cmsis_armclang.h;Drivers\CMSIS\Include\cmsis_armclang_ltm.h;Drivers\CMSIS\Include\cmsis_compiler.h;Drivers\CMSIS\Include\cmsis_gcc.h;Drivers\CMSIS\Include\cmsis_iccarm.h;Drivers\CMSIS\Include\cmsis_version.h;Drivers\CMSIS\Include\core_armv81mml.h;Drivers\CMSIS\Include\core_armv8mbl.h;Drivers\CMSIS\Include\core_armv8mml.h;Drivers\CMSIS\Include\core_cm0.h;Drivers\CMSIS\Include\core_cm0plus.h;Drivers\CMSIS\Include\core_cm1.h;Drivers\CMSIS\Include\core_cm23.h;Drivers\CMSIS\Include\core_cm3.h;Drivers\CMSIS\Include\core_cm33.h;Drivers\CMSIS\Include\core_cm35p.h;Drivers\CMSIS\Include\core_cm4.h;Drivers\CMSIS\Include\core_cm7.h;Drivers\CMSIS\Include\core_sc000.h;Drivers\CMSIS\Include\core_sc300.h;Drivers\CMSIS\Include\mpu_armv7.h;Drivers\CMSIS\Include\mpu_armv8.h;Drivers\CMSIS\Include\tz_context.h; [PreviousUsedCubeIDEFiles] SourceFiles=Core\Src\main.c;Core\Src\freertos.c;Core\Src\stm32l4xx_it.c;Core\Src\stm32l4xx_hal_msp.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_can.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dac.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dac_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c;Middlewares/Third_Party/FreeRTOS/Source/croutine.c;Middlewares/Third_Party/FreeRTOS/Source/event_groups.c;Middlewares/Third_Party/FreeRTOS/Source/list.c;Middlewares/Third_Party/FreeRTOS/Source/queue.c;Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c;Middlewares/Third_Party/FreeRTOS/Source/tasks.c;Middlewares/Third_Party/FreeRTOS/Source/timers.c;Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c;Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c;Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c;Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/system_stm32l4xx.c;Core\Src/system_stm32l4xx.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_can.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dac.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dac_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c;Middlewares/Third_Party/FreeRTOS/Source/croutine.c;Middlewares/Third_Party/FreeRTOS/Source/event_groups.c;Middlewares/Third_Party/FreeRTOS/Source/list.c;Middlewares/Third_Party/FreeRTOS/Source/queue.c;Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c;Middlewares/Third_Party/FreeRTOS/Source/tasks.c;Middlewares/Third_Party/FreeRTOS/Source/timers.c;Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c;Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c;Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c;Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/system_stm32l4xx.c;Core\Src/system_stm32l4xx.c;;;Middlewares/Third_Party/FreeRTOS/Source/croutine.c;Middlewares/Third_Party/FreeRTOS/Source/event_groups.c;Middlewares/Third_Party/FreeRTOS/Source/list.c;Middlewares/Third_Party/FreeRTOS/Source/queue.c;Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c;Middlewares/Third_Party/FreeRTOS/Source/tasks.c;Middlewares/Third_Party/FreeRTOS/Source/timers.c;Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c;Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c;Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c; @@ -7,7 +7,7 @@ HeaderPath=Drivers\STM32L4xx_HAL_Driver\Inc;Drivers\STM32L4xx_HAL_Driver\Inc\Leg CDefines=USE_HAL_DRIVER;STM32L432xx;USE_HAL_DRIVER;USE_HAL_DRIVER; [PreviousUsedMakefileFiles] -SourceFiles=Core\Src\main.c;Core\Src\freertos.c;Core\Src\stm32l4xx_it.c;Core\Src\stm32l4xx_hal_msp.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_adc.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_adc_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_i2c.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_i2c_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash_ramfunc.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_gpio.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_cortex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_exti.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_can.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dac.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dac_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_iwdg.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_spi.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_spi_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_tim.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_tim_ex.c;Middlewares\Third_Party\FreeRTOS\Source\croutine.c;Middlewares\Third_Party\FreeRTOS\Source\event_groups.c;Middlewares\Third_Party\FreeRTOS\Source\list.c;Middlewares\Third_Party\FreeRTOS\Source\queue.c;Middlewares\Third_Party\FreeRTOS\Source\stream_buffer.c;Middlewares\Third_Party\FreeRTOS\Source\tasks.c;Middlewares\Third_Party\FreeRTOS\Source\timers.c;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.c;Middlewares\Third_Party\FreeRTOS\Source\portable\MemMang\heap_4.c;Middlewares\Third_Party\FreeRTOS\Source\portable\GCC\ARM_CM4F\port.c;Drivers\CMSIS\Device\ST\STM32L4xx\Source\Templates\system_stm32l4xx.c;Core\Src\system_stm32l4xx.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_adc.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_adc_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_i2c.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_i2c_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash_ramfunc.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_gpio.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_cortex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_exti.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_can.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dac.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dac_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_iwdg.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_spi.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_spi_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_tim.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_tim_ex.c;Middlewares\Third_Party\FreeRTOS\Source\croutine.c;Middlewares\Third_Party\FreeRTOS\Source\event_groups.c;Middlewares\Third_Party\FreeRTOS\Source\list.c;Middlewares\Third_Party\FreeRTOS\Source\queue.c;Middlewares\Third_Party\FreeRTOS\Source\stream_buffer.c;Middlewares\Third_Party\FreeRTOS\Source\tasks.c;Middlewares\Third_Party\FreeRTOS\Source\timers.c;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.c;Middlewares\Third_Party\FreeRTOS\Source\portable\MemMang\heap_4.c;Middlewares\Third_Party\FreeRTOS\Source\portable\GCC\ARM_CM4F\port.c;Drivers\CMSIS\Device\ST\STM32L4xx\Source\Templates\system_stm32l4xx.c;Core\Src\system_stm32l4xx.c;;;Middlewares\Third_Party\FreeRTOS\Source\croutine.c;Middlewares\Third_Party\FreeRTOS\Source\event_groups.c;Middlewares\Third_Party\FreeRTOS\Source\list.c;Middlewares\Third_Party\FreeRTOS\Source\queue.c;Middlewares\Third_Party\FreeRTOS\Source\stream_buffer.c;Middlewares\Third_Party\FreeRTOS\Source\tasks.c;Middlewares\Third_Party\FreeRTOS\Source\timers.c;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.c;Middlewares\Third_Party\FreeRTOS\Source\portable\MemMang\heap_4.c;Middlewares\Third_Party\FreeRTOS\Source\portable\GCC\ARM_CM4F\port.c; +SourceFiles=Core\Src\main.c;Core\Src\freertos.c;Core\Src\stm32l4xx_it.c;Core\Src\stm32l4xx_hal_msp.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_adc.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_adc_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_i2c.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_i2c_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash_ramfunc.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_gpio.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_cortex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_exti.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_can.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_crc.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_crc_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dac.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dac_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_iwdg.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_spi.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_spi_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_tim.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_tim_ex.c;Middlewares\Third_Party\FreeRTOS\Source\croutine.c;Middlewares\Third_Party\FreeRTOS\Source\event_groups.c;Middlewares\Third_Party\FreeRTOS\Source\list.c;Middlewares\Third_Party\FreeRTOS\Source\queue.c;Middlewares\Third_Party\FreeRTOS\Source\stream_buffer.c;Middlewares\Third_Party\FreeRTOS\Source\tasks.c;Middlewares\Third_Party\FreeRTOS\Source\timers.c;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.c;Middlewares\Third_Party\FreeRTOS\Source\portable\MemMang\heap_4.c;Middlewares\Third_Party\FreeRTOS\Source\portable\GCC\ARM_CM4F\port.c;Drivers\CMSIS\Device\ST\STM32L4xx\Source\Templates\system_stm32l4xx.c;Core\Src\system_stm32l4xx.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_adc.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_adc_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_i2c.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_i2c_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash_ramfunc.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_gpio.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_cortex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_exti.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_can.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_crc.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_crc_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dac.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dac_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_iwdg.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_spi.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_spi_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_tim.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_tim_ex.c;Middlewares\Third_Party\FreeRTOS\Source\croutine.c;Middlewares\Third_Party\FreeRTOS\Source\event_groups.c;Middlewares\Third_Party\FreeRTOS\Source\list.c;Middlewares\Third_Party\FreeRTOS\Source\queue.c;Middlewares\Third_Party\FreeRTOS\Source\stream_buffer.c;Middlewares\Third_Party\FreeRTOS\Source\tasks.c;Middlewares\Third_Party\FreeRTOS\Source\timers.c;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.c;Middlewares\Third_Party\FreeRTOS\Source\portable\MemMang\heap_4.c;Middlewares\Third_Party\FreeRTOS\Source\portable\GCC\ARM_CM4F\port.c;Drivers\CMSIS\Device\ST\STM32L4xx\Source\Templates\system_stm32l4xx.c;Core\Src\system_stm32l4xx.c;;;Middlewares\Third_Party\FreeRTOS\Source\croutine.c;Middlewares\Third_Party\FreeRTOS\Source\event_groups.c;Middlewares\Third_Party\FreeRTOS\Source\list.c;Middlewares\Third_Party\FreeRTOS\Source\queue.c;Middlewares\Third_Party\FreeRTOS\Source\stream_buffer.c;Middlewares\Third_Party\FreeRTOS\Source\tasks.c;Middlewares\Third_Party\FreeRTOS\Source\timers.c;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.c;Middlewares\Third_Party\FreeRTOS\Source\portable\MemMang\heap_4.c;Middlewares\Third_Party\FreeRTOS\Source\portable\GCC\ARM_CM4F\port.c; HeaderPath=Drivers\STM32L4xx_HAL_Driver\Inc;Drivers\STM32L4xx_HAL_Driver\Inc\Legacy;Middlewares\Third_Party\FreeRTOS\Source\include;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2;Middlewares\Third_Party\FreeRTOS\Source\portable\GCC\ARM_CM4F;Drivers\CMSIS\Device\ST\STM32L4xx\Include;Drivers\CMSIS\Include;Core\Inc; CDefines=USE_HAL_DRIVER;STM32L432xx;USE_HAL_DRIVER;USE_HAL_DRIVER; diff --git a/.vscode/c_cpp_properties.json b/.vscode/c_cpp_properties.json index 64c89c0..9c4f9db 100644 --- a/.vscode/c_cpp_properties.json +++ b/.vscode/c_cpp_properties.json @@ -12,6 +12,8 @@ "Drivers/CMSIS/Include", "Drivers/STM32L4xx_HAL_Driver/Inc", "Drivers/STM32L4xx_HAL_Driver/Inc/Legacy", + "Middlewares/ST/EEPROM_Emul/Core", + "Middlewares/ST/EEPROM_Emul/Porting/STM32L4", "Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2", "Middlewares/Third_Party/FreeRTOS/Source/include", "Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F" diff --git a/.vscode/settings.json b/.vscode/settings.json index 2f91c54..b04cd1a 100644 --- a/.vscode/settings.json +++ b/.vscode/settings.json @@ -3,7 +3,8 @@ "files.associations": { "peco_peltiercontroller.h": "c", "cmsis_os2.h": "c", - "varh_variablehandler.h": "c" + "varh_variablehandler.h": "c", + "eeprom_emul.h": "c" }, "cortex-debug.armToolchainPath": "c:\\Users\\pique_n\\AppData\\Roaming\\Code\\User\\globalStorage\\bmd.stm32-for-vscode\\@xpack-dev-tools\\arm-none-eabi-gcc\\11.3.1-1.1.2\\.content\\bin", "cortex-debug.openocdPath": "C:\\USERS\\PIQUE_N\\APPDATA\\ROAMING\\CODE\\USER\\GLOBALSTORAGE\\BMD.STM32-FOR-VSCODE\\@XPACK-DEV-TOOLS\\OPENOCD\\0.11.0-5.1\\.CONTENT\\BIN\\OPENOCD.EXE", diff --git a/Core/Application/MAIN_MainApplication.c b/Core/Application/MAIN_MainApplication.c index 7b2f64e..43b4af5 100644 --- a/Core/Application/MAIN_MainApplication.c +++ b/Core/Application/MAIN_MainApplication.c @@ -57,7 +57,7 @@ //================================================================================================= /* Software Version */ -#define SW_VERSION 1 +#define SW_VERSION 2 #define MSG_QUEUE_SIZE 8 @@ -74,7 +74,8 @@ #define COMMAND_ALARM 4 #define COMMAND_CLEAR_ERROR 5 #define COMMAND_GET_SW_VERSION 6 -#define COMMAND_SET_REF_VOLTAGE 7 +#define COMMAND_SAVE_VARIABLES 7 +#define COMMAND_LOAD_VARIABLES 8 #define COMMAND_REBOOT 255 @@ -199,7 +200,7 @@ LOCAL CONST osTimerAttr_t stWatchdogTimerAttribute = // Returns: Boolean TRUE if successful //------------------------------------------------------------------------------------------------- -BOOL MAIN_boInitializeModule( VOID ) +BOOL MAIN_boInitializeModule( VOID ) { BOOL boOK = TRUE; @@ -274,7 +275,6 @@ PRIVATE VOID vTask( PVOID arg ) case COMMAND_ON: PECO_Enable( TRUE ); break; - case COMMAND_OFF: PECO_Enable( FALSE ); break; @@ -293,11 +293,13 @@ PRIVATE VOID vTask( PVOID arg ) au8Buffer[1] = SW_VERSION; CAND_boSendMessage( au8Buffer, 2, stMessage.boIsPrivate, stMessage.u8Type ); break; - case COMMAND_SET_REF_VOLTAGE: - VARH_UVariable uData; - UTIL_vMemCopy(&stMessage.au8Data[1], &uData, 4); - ANPI_vSetRefVoltage(uData.flVal); - ANPO_boSetVoltage(uData.flVal); + case COMMAND_SAVE_VARIABLES: + au8Buffer[0] = COMMAND_SAVE_VARIABLES; + au8Buffer[1] = VARH_vSaveVariablestoFlash() ? 0xFF : 0x00; + CAND_boSendMessage( au8Buffer, 2, stMessage.boIsPrivate, stMessage.u8Type ); + break; + case COMMAND_LOAD_VARIABLES: + VARH_vLoadVariablesfromFlash(); break; default: break; diff --git a/Core/Application/VARH_VariableHandler.c b/Core/Application/VARH_VariableHandler.c index 10b6506..cfef782 100644 --- a/Core/Application/VARH_VariableHandler.c +++ b/Core/Application/VARH_VariableHandler.c @@ -30,6 +30,8 @@ #include "VARH_VariableHandler.h" +#include "USFL_UserFlash.h" + // Toolbox #include "../Toolbox/UTIL_Utility.h" @@ -69,6 +71,11 @@ LOCAL osMutexId_t m_pstMutexID = NULL; // Description: Definition of local constants (visible by this module only). //================================================================================================= +/* + If you set the VARH_FLAGINFO_FLASH, don't forget to update the Number of variables saved into Flash!!! + Middlewares\ST\EEPROM_Emul\Core\eeprom_emul_conf.h +*/ + LOCAL CONST VARH_StVarInfo m_astVarInfo[VARH_eNumberOfVariables] = { { VARH_FLAGINFO_NONE, (VARH_UVariable)(U32)1, (VARH_UVariable)(U32)0, (VARH_UVariable)(U32)1}, // VARH_eMode @@ -97,6 +104,7 @@ LOCAL CONST VARH_StVarInfo m_astVarInfo[VARH_eNumberOfVariables] = { VARH_FLAGINFO_READONLY, (VARH_UVariable)(U32)0, (VARH_UVariable)(U32)0, (VARH_UVariable)(U32)1 }, // VARH_ePowerState { VARH_FLAGINFO_READONLY, (VARH_UVariable)(U32)0, (VARH_UVariable)(U32)0, (VARH_UVariable)(U32)0xFFFFFFFF }, // VARH_eError + { VARH_FLAGINFO_FLASH | VARH_FLAGINFO_FLOAT, (VARH_UVariable)3.3f, (VARH_UVariable)(U32)2.0f, (VARH_UVariable)4.0f }, // VARH_eRef_U }; LOCAL CONST osMutexAttr_t m_stMutexAttr = @@ -353,6 +361,56 @@ VOID VARH_vSetAllVariablesToInitData( VOID ) } } +//------------------------------------------------------------------------------------------------- +// Function: VARH_vSaveVariablestoFlash +// Description: Saves all Variables with Flag VARH_FLAGINFO_FLASH to Flash +// Parameters: None +// Returns: TRUE if successful +//------------------------------------------------------------------------------------------------- +BOOL VARH_vSaveVariablestoFlash( VOID ) +{ + BOOL boOK = TRUE; + USFL_vUnlock(); + for( U8 u8Var = 0; u8Var < VARH_eNumberOfVariables; u8Var++ ) + { + if( (m_astVarInfo[u8Var].u8Flags & VARH_FLAGINFO_FLASH) == VARH_FLAGINFO_FLASH ){ + boOK &= USFL_boSetVariable(u8Var, VARH_u32GetVariableData(u8Var)); + } + } + USFL_vLock(); + + return boOK; +} + + +//------------------------------------------------------------------------------------------------- +// Function: VARH_vSaveVariablestoFlash +// Description: Saves all Variables with Flag VARH_FLAGINFO_FLASH to Flash +// Parameters: None +// Returns: None +//------------------------------------------------------------------------------------------------- +VOID VARH_vLoadVariablesfromFlash( VOID ) +{ + BOOL boOK = TRUE; + for( U8 u8Var = 0; u8Var < VARH_eNumberOfVariables; u8Var++ ) + { + if( (m_astVarInfo[u8Var].u8Flags & VARH_FLAGINFO_FLASH) == VARH_FLAGINFO_FLASH ){ + U32 u32Data; + boOK &= USFL_boGetVariable(u8Var, &u32Data); + if( boOK ) VARH_vSetVariableDataFromSystemU32(u8Var, u32Data); + } + } + if( !boOK ){ + for( U8 u8Var = 0; u8Var < VARH_eNumberOfVariables; u8Var++ ) + { + if( (m_astVarInfo[u8Var].u8Flags & VARH_FLAGINFO_FLASH) == VARH_FLAGINFO_FLASH ){ + VARH_vSetVariableToInitData( u8Var ); + } + } + } +} + + //================================================================================================= // Section: LOCAL FUNCTIONS // Descriptionn: Definition (implementation) of local functions. diff --git a/Core/Application/VARH_VariableHandler.h b/Core/Application/VARH_VariableHandler.h index c0c7767..a90a8b2 100644 --- a/Core/Application/VARH_VariableHandler.h +++ b/Core/Application/VARH_VariableHandler.h @@ -91,6 +91,7 @@ typedef enum VARH_ePowerState, VARH_eError, + VARH_eRef_U, VARH_eNumberOfVariables, // Must be last entry } VARH_EnVariables; @@ -167,6 +168,9 @@ U8 VARH_uGetVariableFlags( U8 u8Variable ); VOID VARH_vSetVariableToInitData( U8 u8Variable ); VOID VARH_vSetAllVariablesToInitData( VOID ); +BOOL VARH_vSaveVariablestoFlash( VOID ); +VOID VARH_vLoadVariablesfromFlash( VOID ); + #ifdef __cplusplus } #endif diff --git a/Core/Drivers/ANPI_AnalogPortsIn.c b/Core/Drivers/ANPI_AnalogPortsIn.c index 92daa34..269050f 100644 --- a/Core/Drivers/ANPI_AnalogPortsIn.c +++ b/Core/Drivers/ANPI_AnalogPortsIn.c @@ -52,8 +52,6 @@ #define ADC_RES (4096) // ADC resolution: 12 bits #define NR_OF_ADCS ANPI_eInNumberOfInputs // number of internal adc channels -#define INT_ADC_REF (3.3f)// int. reference voltage for conversion - #define BUFFER_SIZE NR_OF_ADCS * 2 #define BUFFER_HALF_SIZE NR_OF_ADCS @@ -95,8 +93,6 @@ LOCAL osThreadId_t m_pstThreadID = NULL; LOCAL osEventFlagsId_t m_pstEventID = NULL; LOCAL osMutexId_t m_pstMutexID = NULL; -LOCAL FLOAT flRefVoltage = INT_ADC_REF; - //================================================================================================= // Section: LOCAL CONSTANTS // Description: Definition of local constants (visible by this module only). @@ -200,17 +196,6 @@ BOOL ANPI_boInitializeModule( VOID ) return( boOK ); } -//------------------------------------------------------------------------------------------------- -// Function: ANPI_vSetRefVoltage -// Description: Sets the Reference Voltage for calculating the Voltage -// Parameters: FLOAT flVoltage -> The Ref Voltage measured with an DMM for example -// Returns: None -//------------------------------------------------------------------------------------------------- -VOID ANPI_vSetRefVoltage( FLOAT flVoltage ) -{ - flRefVoltage = flVoltage; -} - //------------------------------------------------------------------------------------------------- // Function: ANPI_vTask // Description: ANPI_vTask @@ -244,6 +229,8 @@ VOID vTask( PVOID arg ) for( U16 u16Cnt = 0; u16Cnt < BUFFER_HALF_SIZE; u16Cnt++ ) au32ADCRawData[ u16Cnt ] = m_au16ADCDataBuffer[u16Cnt + u16Offset]; + FLOAT flRefVoltage = VARH_flGetVariableData(VARH_eRef_U); + // multiply conversion factor and add the offset for( U16 u16Cnt = 0; u16Cnt < ANPI_eInNumberOfInputs; u16Cnt++ ) { diff --git a/Core/Drivers/ANPI_AnalogPortsIn.h b/Core/Drivers/ANPI_AnalogPortsIn.h index 1a8673e..3f6ff74 100644 --- a/Core/Drivers/ANPI_AnalogPortsIn.h +++ b/Core/Drivers/ANPI_AnalogPortsIn.h @@ -94,7 +94,6 @@ typedef enum //================================================================================================= BOOL ANPI_boInitializeModule( VOID ); -VOID ANPI_vSetRefVoltage( FLOAT flVoltage ); #ifdef __cplusplus } diff --git a/Core/Drivers/ANPO_AnalogPortsOut.c b/Core/Drivers/ANPO_AnalogPortsOut.c index 44333c1..a75e5b6 100644 --- a/Core/Drivers/ANPO_AnalogPortsOut.c +++ b/Core/Drivers/ANPO_AnalogPortsOut.c @@ -32,6 +32,8 @@ #include "ANPO_AnalogPortsOut.h" +#include "VARH_VariableHandler.h" + // Toolbox #include "../Toolbox/UTIL_Utility.h" @@ -45,7 +47,7 @@ // Description: Definition of local constants (visible by this module only). //================================================================================================= -#define INT_DAC_REF (3.3f)// int. reference voltage for conversion + //================================================================================================= // Section: MACROS @@ -61,7 +63,6 @@ - //================================================================================================= // Section: STRUCTURES // Description: Definition of local Structures (visible by this module only). @@ -69,13 +70,12 @@ - //================================================================================================= // Section: LOCAL VARIABLES // Description: Definition of local variables (visible by this module only). //================================================================================================= -LOCAL FLOAT flRefVoltage = INT_DAC_REF; + //================================================================================================= // Section: LOCAL CONSTANTS @@ -125,17 +125,6 @@ BOOL ANPO_boInitializeModule( VOID ) return( boOK ); } -//------------------------------------------------------------------------------------------------- -// Function: ANPO_vSetRefVoltage -// Description: Sets the Reference Voltage for calculating the Voltage -// Parameters: FLOAT flVoltage -> The Ref Voltage measured with an DMM for example -// Returns: None -//------------------------------------------------------------------------------------------------- -VOID ANPO_vSetRefVoltage( FLOAT flVoltage ) -{ - flRefVoltage = flVoltage; -} - //================================================================================================= // Section: LOCAL FUNCTIONS // Descriptionn: Definition (implementation) of local functions. @@ -166,7 +155,7 @@ BOOL ANPO_boSetVoltage( FLOAT flVoltage ){ U32 u32ConvertVoltagetoRaw( FLOAT flVoltage ){ U32 RawData; - RawData = flVoltage * 4095 / flRefVoltage; + RawData = flVoltage * 4095 / VARH_flGetVariableData(VARH_eRef_U); return RawData; } diff --git a/Core/Drivers/ANPO_AnalogPortsOut.h b/Core/Drivers/ANPO_AnalogPortsOut.h index 8ff9235..f239afc 100644 --- a/Core/Drivers/ANPO_AnalogPortsOut.h +++ b/Core/Drivers/ANPO_AnalogPortsOut.h @@ -88,7 +88,6 @@ typedef enum BOOL ANPO_boInitializeModule( VOID ); BOOL ANPO_boSetVoltage( FLOAT flVoltage ); -VOID ANPO_vSetRefVoltage( FLOAT flVoltage ); #ifdef __cplusplus } diff --git a/Core/Drivers/USFL_UserFlash.c b/Core/Drivers/USFL_UserFlash.c index 4f7e17d..fb42596 100644 --- a/Core/Drivers/USFL_UserFlash.c +++ b/Core/Drivers/USFL_UserFlash.c @@ -19,23 +19,11 @@ // //------------------------------------------------------------------------------------------------- // -// Description: This source file contains all functions dealing with internal flash for User Settings +// Description: This source file contains all functions dealing with the virtual eeprom // -// STM32L432KBUX_FLASH.ld +// More info in the AN4894 or this link: +// https://www.st.com/en/embedded-software/x-cube-eeprom.html // -// DATA (rwx) : ORIGIN = 0x801F800, LENGTH = 2K -// -// /* Sections */ -// SECTIONS -// { -// /* NOLOAD is required for not ereasing this block */ -// .user_data (NOLOAD) : -// { -// . = ALIGN(4); -// *(.user_data) -// . = ALIGN(4); -// } > DATA*/ -// ... //================================================================================================= @@ -47,26 +35,18 @@ #include "USFL_UserFlash.h" -// Toolbox -#include "../Application/VARH_VariableHandler.h" - // include STM32 drivers #include "stm32l4xx_hal.h" #include "cmsis_os2.h" +#include "eeprom_emul.h" + //================================================================================================= // Section: DEFINITIONS // Description: Definition of local constants (visible by this module only). //================================================================================================= -#define USERFLASHSIZE (2000/4) // Bytes -> 64 Bits -#define USERFLASHPAGE (63) - -#define VARDEF 0xABCDEF - -#define STARTDEF (((U64)0xAA01F055 << 32) + (VARDEF << 2)) - //================================================================================================= @@ -88,12 +68,6 @@ // Description: Definition of local Structures (visible by this module only). //================================================================================================= -FLASH_EraseInitTypeDef stEreaseInit = { - FLASH_TYPEERASE_PAGES, - FLASH_BANK_1, - USERFLASHPAGE, - 1 -}; //================================================================================================= @@ -101,24 +75,29 @@ FLASH_EraseInitTypeDef stEreaseInit = { // Description: Definition of local variables (visible by this module only). //================================================================================================= -U32 u32VarPointer = 0; +__IO uint32_t ErasingOnGoing = 0; + +LOCAL osMutexId_t m_pstMutexID = NULL; //================================================================================================= // Section: LOCAL CONSTANTS // Description: Definition of local constants (visible by this module only). //================================================================================================= -__attribute__((__section__(".user_data"))) const U64 UserFlash[USERFLASHSIZE]; +LOCAL CONST osMutexAttr_t m_stMutexAttr = +{ + "USFL_Mutex", // human readable mutex name + osMutexRecursive | osMutexPrioInherit, // attr_bits + NULL, // memory for control block + 0U // size for control block +}; //================================================================================================= // Section: LOCAL FUNCTIONS (PROTOTYPES) // Description: Definition of local functions (visible by this module only). //================================================================================================= -BOOL vEreaseUserFlash( void ); -U32 vFindNextFreePointer( void ); -U32 u32FindLastPointer( void ); -U8 u8ConvertWordsToDoubleWords( U8 u8Words ); + //================================================================================================= // Section: GLOBAL FUNCTIONS @@ -131,28 +110,87 @@ U8 u8ConvertWordsToDoubleWords( U8 u8Words ); // Parameters: None // Returns: Boolean TRUE if successful //------------------------------------------------------------------------------------------------- - BOOL USFL_boInitializeModule( VOID ) { BOOL boOK = TRUE; - if( UserFlash[0] != STARTDEF ){ - boOK &= vEreaseUserFlash(); - } - + boOK &= ( ( m_pstMutexID = osMutexNew( &m_stMutexAttr )) == NULL) ? FALSE : TRUE; + boOK &= EE_Init(EE_FORCED_ERASE) == EE_OK ? TRUE : FALSE; return( boOK ); } -VARH_UVariable USFL_uGetVariable ( void ){ +//------------------------------------------------------------------------------------------------- +// Function: USFL_boGetVariable +// Description: Gets a variable out of the virtual eeprom +// Parameters: U8 u8Variable -> virtual adress of variable +// U32 * u32Variable -> pointer to data +// Returns: Boolean TRUE if successful +//------------------------------------------------------------------------------------------------- +BOOL USFL_boGetVariable ( U8 u8Variable, U32 * u32Variable ){ + BOOL boOK = TRUE; - if( u32VarPointer == 0 ) u32VarPointer = u32FindLastPointer(); - - + osMutexAcquire( m_pstMutexID, osWaitForever ); // aquire mutex + boOK &= EE_ReadVariable32bits( (U16) u8Variable, u32Variable ) == EE_OK ? TRUE : FALSE; + osMutexRelease( m_pstMutexID ); // release mutex + return boOK; } +//------------------------------------------------------------------------------------------------- +// Function: USFL_boSetVariable +// Description: Writes a variable into the virtual eeprom +// Parameters: U8 u8Variable -> virtual adress of variable +// U32 u32Variable -> data to write +// Returns: Boolean TRUE if successful +//------------------------------------------------------------------------------------------------- +BOOL USFL_boSetVariable ( U8 u8Variable, U32 u32Variable ){ + BOOL boOK = TRUE; + EE_Status ee_status = EE_OK; + + osMutexAcquire( m_pstMutexID, osWaitForever ); // aquire mutex + boOK &= (ee_status = EE_WriteVariable32bits( (U16) u8Variable, u32Variable )) == EE_OK ? TRUE : FALSE; + + /* Start cleanup IT mode, if cleanup is needed */ + if ((ee_status & EE_STATUSMASK_CLEANUP) == EE_STATUSMASK_CLEANUP) { + ErasingOnGoing = 1; + boOK &= (ee_status |= EE_CleanUp()) == EE_OK ? TRUE : FALSE; + } + if ((ee_status & EE_STATUSMASK_ERROR) == EE_STATUSMASK_ERROR) {boOK &= FALSE;} + + osMutexRelease( m_pstMutexID ); // release mutex + + return boOK; +} + +//------------------------------------------------------------------------------------------------- +// Function: USFL_vLock +// Description: Locks the Flash, no more clearing and programming possible +// Parameters: None +// Returns: Boolean TRUE if successful +//------------------------------------------------------------------------------------------------- +BOOL USFL_vLock( VOID ){ + BOOL boOK = TRUE; + + boOK &= HAL_FLASH_Lock() == HAL_OK ? TRUE : FALSE; + + return boOK; +} + +//------------------------------------------------------------------------------------------------- +// Function: USFL_vUnlock +// Description: Unlocks the Flash, clearing and programming possible +// Parameters: None +// Returns: Boolean TRUE if successful +//------------------------------------------------------------------------------------------------- +BOOL USFL_vUnlock( VOID ){ + BOOL boOK = TRUE; + + boOK &= HAL_FLASH_Unlock() == HAL_OK ? TRUE : FALSE; + + return boOK; +} //================================================================================================= @@ -160,116 +198,3 @@ VARH_UVariable USFL_uGetVariable ( void ){ // Descriptionn: Definition (implementation) of local functions. //================================================================================================= -//------------------------------------------------------------------------------------------------- -// Function: u32FindNextFreePointer -// Description: Finds the next free sector in the flash for saving variables -// Parameters: None -// Returns: U32 next free pointer -//------------------------------------------------------------------------------------------------- -U32 u32FindNextFreePointer( void ){ - - BOOL boFound = FALSE; - U32 u32Pointer = u32VarPointer; - - while(!boFound){ - - if( ( ( UserFlash[u32Pointer] >> 8 ) & 0xFFFFFF ) == VARDEF ){ - U8 u8Size = UserFlash[u32Pointer] & 0xFF; - if( u8Size == 0 ){ - boFound = TRUE; - } else { - u32Pointer += u8ConvertWordsToDoubleWords(u8Size); - } - } else { - u32Pointer += 1; - } - - if( u32Pointer >= USERFLASHSIZE ){ - u32Pointer = 1; - break; - } - } - return u32Pointer; -} - - -//------------------------------------------------------------------------------------------------- -// Function: u32FindLastPointer -// Description: Finds the next free sector in the flash for saving variables -// Parameters: None -// Returns: U32 next free pointer -//------------------------------------------------------------------------------------------------- -U32 u32FindLastPointer( void ){ - - BOOL boFound = FALSE; - U32 u32Pointer = 0; - U8 u8LastSize = 0; - - while(!boFound){ - - if( ( UserFlash[u32Pointer] >> 40) == VARDEF ){ - U8 u8Size = UserFlash[u32Pointer] & 0xFF; - if( u8Size == 0 ){ - boFound = TRUE; - u32Pointer -= u8ConvertWordsToDoubleWords(u8LastSize); - } else { - u32Pointer += u8ConvertWordsToDoubleWords(u8Size); - u8LastSize = u8Size; - } - } else { - u32Pointer += 1; - } - - if( u32Pointer >= USERFLASHSIZE ){ - u32Pointer = 1; - break; - } - } - return u32Pointer; -} - - -//------------------------------------------------------------------------------------------------- -// Function: u8ConvertWordsToDoubleWords -// Description: Converts 32Bit Word size to 64 Bit Double Word size for saving Vars -// Parameters: U8 u8Words -// Returns: U8 Double Words -//------------------------------------------------------------------------------------------------- -U8 u8ConvertWordsToDoubleWords( U8 u8Words ) { - U8 u8DWords; - - u8Words += 1; // + VARDEF - u8DWords = u8Words / 2; - u8DWords += u8Words % 2; - - return u8DWords; -} - -//------------------------------------------------------------------------------------------------- -// Function: vEreaseUserFlash -// Description: Ereases the User Flash Sector -// Parameters: None -// Returns: Boolean TRUE if successful -//------------------------------------------------------------------------------------------------- -BOOL vEreaseUserFlash( void ){ - uint32_t u32PageError = 0; - - BOOL boOK = TRUE; - - HAL_FLASH_Unlock(); - boOK &= HAL_FLASHEx_Erase(&stEreaseInit, &u32PageError) == HAL_OK ? TRUE : FALSE; - - if( !boOK ){ - return FALSE; - } - - HAL_FLASH_Program(FLASH_TYPEPROGRAM_DOUBLEWORD, (U32) &UserFlash[0], STARTDEF); - - HAL_FLASH_Lock(); - - return TRUE; -} - - - - diff --git a/Core/Drivers/USFL_UserFlash.h b/Core/Drivers/USFL_UserFlash.h index f89cba0..3cd78a1 100644 --- a/Core/Drivers/USFL_UserFlash.h +++ b/Core/Drivers/USFL_UserFlash.h @@ -87,6 +87,11 @@ extern "C" { //================================================================================================= BOOL USFL_boInitializeModule( VOID ); +BOOL USFL_boGetVariable ( U8 u8Variable, U32 * u32Variable ); +BOOL USFL_boSetVariable ( U8 u8Variable, U32 u32Variable ); + +BOOL USFL_vLock( VOID ); +BOOL USFL_vUnlock( VOID ); #ifdef __cplusplus } diff --git a/Core/Inc/stm32l4xx_hal_conf.h b/Core/Inc/stm32l4xx_hal_conf.h index 3540da6..5409f12 100644 --- a/Core/Inc/stm32l4xx_hal_conf.h +++ b/Core/Inc/stm32l4xx_hal_conf.h @@ -40,7 +40,7 @@ /*#define HAL_CRYP_MODULE_ENABLED */ #define HAL_CAN_MODULE_ENABLED /*#define HAL_COMP_MODULE_ENABLED */ -/*#define HAL_CRC_MODULE_ENABLED */ +#define HAL_CRC_MODULE_ENABLED /*#define HAL_CRYP_MODULE_ENABLED */ #define HAL_DAC_MODULE_ENABLED /*#define HAL_DCMI_MODULE_ENABLED */ diff --git a/Core/Src/main.c b/Core/Src/main.c index c6a3d0e..33f6505 100644 --- a/Core/Src/main.c +++ b/Core/Src/main.c @@ -52,6 +52,8 @@ DMA_HandleTypeDef hdma_adc1; CAN_HandleTypeDef hcan1; +CRC_HandleTypeDef hcrc; + DAC_HandleTypeDef hdac1; I2C_HandleTypeDef hi2c1; @@ -83,6 +85,7 @@ static void MX_DAC1_Init(void); static void MX_SPI1_Init(void); static void MX_I2C1_Init(void); static void MX_IWDG_Init(void); +static void MX_CRC_Init(void); void vDefaultTask(void *argument); /* USER CODE BEGIN PFP */ @@ -146,6 +149,7 @@ int main(void) MX_SPI1_Init(); MX_I2C1_Init(); MX_IWDG_Init(); + MX_CRC_Init(); /* USER CODE BEGIN 2 */ /* USER CODE END 2 */ @@ -211,6 +215,7 @@ void SystemClock_Config(void) { Error_Handler(); } + /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ @@ -228,6 +233,7 @@ void SystemClock_Config(void) { Error_Handler(); } + /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK @@ -260,6 +266,7 @@ static void MX_ADC1_Init(void) /* USER CODE BEGIN ADC1_Init 1 */ /* USER CODE END ADC1_Init 1 */ + /** Common config */ hadc1.Instance = ADC1; @@ -285,6 +292,7 @@ static void MX_ADC1_Init(void) { Error_Handler(); } + /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_6; @@ -297,6 +305,7 @@ static void MX_ADC1_Init(void) { Error_Handler(); } + /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_16; @@ -305,6 +314,7 @@ static void MX_ADC1_Init(void) { Error_Handler(); } + /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_7; @@ -313,6 +323,7 @@ static void MX_ADC1_Init(void) { Error_Handler(); } + /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_15; @@ -366,6 +377,37 @@ static void MX_CAN1_Init(void) } +/** + * @brief CRC Initialization Function + * @param None + * @retval None + */ +static void MX_CRC_Init(void) +{ + + /* USER CODE BEGIN CRC_Init 0 */ + + /* USER CODE END CRC_Init 0 */ + + /* USER CODE BEGIN CRC_Init 1 */ + + /* USER CODE END CRC_Init 1 */ + hcrc.Instance = CRC; + hcrc.Init.DefaultPolynomialUse = DEFAULT_POLYNOMIAL_ENABLE; + hcrc.Init.DefaultInitValueUse = DEFAULT_INIT_VALUE_ENABLE; + hcrc.Init.InputDataInversionMode = CRC_INPUTDATA_INVERSION_NONE; + hcrc.Init.OutputDataInversionMode = CRC_OUTPUTDATA_INVERSION_DISABLE; + hcrc.InputDataFormat = CRC_INPUTDATA_FORMAT_BYTES; + if (HAL_CRC_Init(&hcrc) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN CRC_Init 2 */ + + /* USER CODE END CRC_Init 2 */ + +} + /** * @brief DAC1 Initialization Function * @param None @@ -383,6 +425,7 @@ static void MX_DAC1_Init(void) /* USER CODE BEGIN DAC1_Init 1 */ /* USER CODE END DAC1_Init 1 */ + /** DAC Initialization */ hdac1.Instance = DAC1; @@ -390,6 +433,7 @@ static void MX_DAC1_Init(void) { Error_Handler(); } + /** DAC channel OUT1 config */ sConfig.DAC_SampleAndHold = DAC_SAMPLEANDHOLD_DISABLE; @@ -440,12 +484,14 @@ static void MX_I2C1_Init(void) { Error_Handler(); } + /** Configure Analogue filter */ if (HAL_I2CEx_ConfigAnalogFilter(&hi2c1, I2C_ANALOGFILTER_ENABLE) != HAL_OK) { Error_Handler(); } + /** Configure Digital filter */ if (HAL_I2CEx_ConfigDigitalFilter(&hi2c1, 0) != HAL_OK) @@ -665,4 +711,3 @@ void assert_failed(uint8_t *file, uint32_t line) /* USER CODE END 6 */ } #endif /* USE_FULL_ASSERT */ - diff --git a/Core/Src/stm32l4xx_hal_msp.c b/Core/Src/stm32l4xx_hal_msp.c index 739ee08..d9f9784 100644 --- a/Core/Src/stm32l4xx_hal_msp.c +++ b/Core/Src/stm32l4xx_hal_msp.c @@ -99,6 +99,7 @@ void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) /* USER CODE BEGIN ADC1_MspInit 0 */ /* USER CODE END ADC1_MspInit 0 */ + /** Initializes the peripherals clock */ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC; @@ -274,6 +275,50 @@ void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan) } +/** +* @brief CRC MSP Initialization +* This function configures the hardware resources used in this example +* @param hcrc: CRC handle pointer +* @retval None +*/ +void HAL_CRC_MspInit(CRC_HandleTypeDef* hcrc) +{ + if(hcrc->Instance==CRC) + { + /* USER CODE BEGIN CRC_MspInit 0 */ + + /* USER CODE END CRC_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_CRC_CLK_ENABLE(); + /* USER CODE BEGIN CRC_MspInit 1 */ + + /* USER CODE END CRC_MspInit 1 */ + } + +} + +/** +* @brief CRC MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hcrc: CRC handle pointer +* @retval None +*/ +void HAL_CRC_MspDeInit(CRC_HandleTypeDef* hcrc) +{ + if(hcrc->Instance==CRC) + { + /* USER CODE BEGIN CRC_MspDeInit 0 */ + + /* USER CODE END CRC_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_CRC_CLK_DISABLE(); + /* USER CODE BEGIN CRC_MspDeInit 1 */ + + /* USER CODE END CRC_MspDeInit 1 */ + } + +} + /** * @brief DAC MSP Initialization * This function configures the hardware resources used in this example @@ -350,6 +395,7 @@ void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c) /* USER CODE BEGIN I2C1_MspInit 0 */ /* USER CODE END I2C1_MspInit 0 */ + /** Initializes the peripherals clock */ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_I2C1; @@ -525,4 +571,3 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ - diff --git a/Core/Src/stm32l4xx_it.c b/Core/Src/stm32l4xx_it.c index b58941a..66c265e 100644 --- a/Core/Src/stm32l4xx_it.c +++ b/Core/Src/stm32l4xx_it.c @@ -317,4 +317,3 @@ void DMA2_Channel3_IRQHandler(void) /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ - diff --git a/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_crc.h b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_crc.h new file mode 100644 index 0000000..f4d9db4 --- /dev/null +++ b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_crc.h @@ -0,0 +1,342 @@ +/** + ****************************************************************************** + * @file stm32l4xx_hal_crc.h + * @author MCD Application Team + * @brief Header file of CRC HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32L4xx_HAL_CRC_H +#define STM32L4xx_HAL_CRC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx_hal_def.h" + +/** @addtogroup STM32L4xx_HAL_Driver + * @{ + */ + +/** @addtogroup CRC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup CRC_Exported_Types CRC Exported Types + * @{ + */ + +/** + * @brief CRC HAL State Structure definition + */ +typedef enum +{ + HAL_CRC_STATE_RESET = 0x00U, /*!< CRC not yet initialized or disabled */ + HAL_CRC_STATE_READY = 0x01U, /*!< CRC initialized and ready for use */ + HAL_CRC_STATE_BUSY = 0x02U, /*!< CRC internal process is ongoing */ + HAL_CRC_STATE_TIMEOUT = 0x03U, /*!< CRC timeout state */ + HAL_CRC_STATE_ERROR = 0x04U /*!< CRC error state */ +} HAL_CRC_StateTypeDef; + +/** + * @brief CRC Init Structure definition + */ +typedef struct +{ + uint8_t DefaultPolynomialUse; /*!< This parameter is a value of @ref CRC_Default_Polynomial and indicates if default polynomial is used. + If set to DEFAULT_POLYNOMIAL_ENABLE, resort to default + X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + + X^4 + X^2+ X +1. + In that case, there is no need to set GeneratingPolynomial field. + If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and + CRCLength fields must be set. */ + + uint8_t DefaultInitValueUse; /*!< This parameter is a value of @ref CRC_Default_InitValue_Use and indicates if default init value is used. + If set to DEFAULT_INIT_VALUE_ENABLE, resort to default + 0xFFFFFFFF value. In that case, there is no need to set InitValue field. If + otherwise set to DEFAULT_INIT_VALUE_DISABLE, InitValue field must be set. */ + + uint32_t GeneratingPolynomial; /*!< Set CRC generating polynomial as a 7, 8, 16 or 32-bit long value for a polynomial degree + respectively equal to 7, 8, 16 or 32. This field is written in normal, + representation e.g., for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 + is written 0x65. No need to specify it if DefaultPolynomialUse is set to + DEFAULT_POLYNOMIAL_ENABLE. */ + + uint32_t CRCLength; /*!< This parameter is a value of @ref CRC_Polynomial_Sizes and indicates CRC length. + Value can be either one of + @arg @ref CRC_POLYLENGTH_32B (32-bit CRC), + @arg @ref CRC_POLYLENGTH_16B (16-bit CRC), + @arg @ref CRC_POLYLENGTH_8B (8-bit CRC), + @arg @ref CRC_POLYLENGTH_7B (7-bit CRC). */ + + uint32_t InitValue; /*!< Init value to initiate CRC computation. No need to specify it if DefaultInitValueUse + is set to DEFAULT_INIT_VALUE_ENABLE. */ + + uint32_t InputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Input_Data_Inversion and specifies input data inversion mode. + Can be either one of the following values + @arg @ref CRC_INPUTDATA_INVERSION_NONE no input data inversion + @arg @ref CRC_INPUTDATA_INVERSION_BYTE byte-wise inversion, 0x1A2B3C4D + becomes 0x58D43CB2 + @arg @ref CRC_INPUTDATA_INVERSION_HALFWORD halfword-wise inversion, + 0x1A2B3C4D becomes 0xD458B23C + @arg @ref CRC_INPUTDATA_INVERSION_WORD word-wise inversion, 0x1A2B3C4D + becomes 0xB23CD458 */ + + uint32_t OutputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Output_Data_Inversion and specifies output data (i.e. CRC) inversion mode. + Can be either + @arg @ref CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion, + @arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE CRC 0x11223344 is converted + into 0x22CC4488 */ +} CRC_InitTypeDef; + +/** + * @brief CRC Handle Structure definition + */ +typedef struct +{ + CRC_TypeDef *Instance; /*!< Register base address */ + + CRC_InitTypeDef Init; /*!< CRC configuration parameters */ + + HAL_LockTypeDef Lock; /*!< CRC Locking object */ + + __IO HAL_CRC_StateTypeDef State; /*!< CRC communication state */ + + uint32_t InputDataFormat; /*!< This parameter is a value of @ref CRC_Input_Buffer_Format and specifies input data format. + Can be either + @arg @ref CRC_INPUTDATA_FORMAT_BYTES input data is a stream of bytes + (8-bit data) + @arg @ref CRC_INPUTDATA_FORMAT_HALFWORDS input data is a stream of + half-words (16-bit data) + @arg @ref CRC_INPUTDATA_FORMAT_WORDS input data is a stream of words + (32-bit data) + + Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization + error must occur if InputBufferFormat is not one of the three values listed + above */ +} CRC_HandleTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup CRC_Exported_Constants CRC Exported Constants + * @{ + */ + +/** @defgroup CRC_Default_Polynomial_Value Default CRC generating polynomial + * @{ + */ +#define DEFAULT_CRC32_POLY 0x04C11DB7U /*!< X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1 */ +/** + * @} + */ + +/** @defgroup CRC_Default_InitValue Default CRC computation initialization value + * @{ + */ +#define DEFAULT_CRC_INITVALUE 0xFFFFFFFFU /*!< Initial CRC default value */ +/** + * @} + */ + +/** @defgroup CRC_Default_Polynomial Indicates whether or not default polynomial is used + * @{ + */ +#define DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00U) /*!< Enable default generating polynomial 0x04C11DB7 */ +#define DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01U) /*!< Disable default generating polynomial 0x04C11DB7 */ +/** + * @} + */ + +/** @defgroup CRC_Default_InitValue_Use Indicates whether or not default init value is used + * @{ + */ +#define DEFAULT_INIT_VALUE_ENABLE ((uint8_t)0x00U) /*!< Enable initial CRC default value */ +#define DEFAULT_INIT_VALUE_DISABLE ((uint8_t)0x01U) /*!< Disable initial CRC default value */ +/** + * @} + */ + +/** @defgroup CRC_Polynomial_Sizes Polynomial sizes to configure the peripheral + * @{ + */ +#define CRC_POLYLENGTH_32B 0x00000000U /*!< Resort to a 32-bit long generating polynomial */ +#define CRC_POLYLENGTH_16B CRC_CR_POLYSIZE_0 /*!< Resort to a 16-bit long generating polynomial */ +#define CRC_POLYLENGTH_8B CRC_CR_POLYSIZE_1 /*!< Resort to a 8-bit long generating polynomial */ +#define CRC_POLYLENGTH_7B CRC_CR_POLYSIZE /*!< Resort to a 7-bit long generating polynomial */ +/** + * @} + */ + +/** @defgroup CRC_Polynomial_Size_Definitions CRC polynomial possible sizes actual definitions + * @{ + */ +#define HAL_CRC_LENGTH_32B 32U /*!< 32-bit long CRC */ +#define HAL_CRC_LENGTH_16B 16U /*!< 16-bit long CRC */ +#define HAL_CRC_LENGTH_8B 8U /*!< 8-bit long CRC */ +#define HAL_CRC_LENGTH_7B 7U /*!< 7-bit long CRC */ +/** + * @} + */ + +/** @defgroup CRC_Input_Buffer_Format Input Buffer Format + * @{ + */ +/* WARNING: CRC_INPUT_FORMAT_UNDEFINED is created for reference purposes but + * an error is triggered in HAL_CRC_Init() if InputDataFormat field is set + * to CRC_INPUT_FORMAT_UNDEFINED: the format MUST be defined by the user for + * the CRC APIs to provide a correct result */ +#define CRC_INPUTDATA_FORMAT_UNDEFINED 0x00000000U /*!< Undefined input data format */ +#define CRC_INPUTDATA_FORMAT_BYTES 0x00000001U /*!< Input data in byte format */ +#define CRC_INPUTDATA_FORMAT_HALFWORDS 0x00000002U /*!< Input data in half-word format */ +#define CRC_INPUTDATA_FORMAT_WORDS 0x00000003U /*!< Input data in word format */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup CRC_Exported_Macros CRC Exported Macros + * @{ + */ + +/** @brief Reset CRC handle state. + * @param __HANDLE__ CRC handle. + * @retval None + */ +#define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET) + +/** + * @brief Reset CRC Data Register. + * @param __HANDLE__ CRC handle + * @retval None + */ +#define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET) + +/** + * @brief Set CRC INIT non-default value + * @param __HANDLE__ CRC handle + * @param __INIT__ 32-bit initial value + * @retval None + */ +#define __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__)) + +/** + * @brief Store data in the Independent Data (ID) register. + * @param __HANDLE__ CRC handle + * @param __VALUE__ Value to be stored in the ID register + * @note Refer to the Reference Manual to get the authorized __VALUE__ length in bits + * @retval None + */ +#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__))) + +/** + * @brief Return the data stored in the Independent Data (ID) register. + * @param __HANDLE__ CRC handle + * @note Refer to the Reference Manual to get the authorized __VALUE__ length in bits + * @retval Value of the ID register + */ +#define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR) +/** + * @} + */ + + +/* Private macros --------------------------------------------------------*/ +/** @defgroup CRC_Private_Macros CRC Private Macros + * @{ + */ + +#define IS_DEFAULT_POLYNOMIAL(DEFAULT) (((DEFAULT) == DEFAULT_POLYNOMIAL_ENABLE) || \ + ((DEFAULT) == DEFAULT_POLYNOMIAL_DISABLE)) + +#define IS_DEFAULT_INIT_VALUE(VALUE) (((VALUE) == DEFAULT_INIT_VALUE_ENABLE) || \ + ((VALUE) == DEFAULT_INIT_VALUE_DISABLE)) + +#define IS_CRC_POL_LENGTH(LENGTH) (((LENGTH) == CRC_POLYLENGTH_32B) || \ + ((LENGTH) == CRC_POLYLENGTH_16B) || \ + ((LENGTH) == CRC_POLYLENGTH_8B) || \ + ((LENGTH) == CRC_POLYLENGTH_7B)) + +#define IS_CRC_INPUTDATA_FORMAT(FORMAT) (((FORMAT) == CRC_INPUTDATA_FORMAT_BYTES) || \ + ((FORMAT) == CRC_INPUTDATA_FORMAT_HALFWORDS) || \ + ((FORMAT) == CRC_INPUTDATA_FORMAT_WORDS)) + +/** + * @} + */ + +/* Include CRC HAL Extended module */ +#include "stm32l4xx_hal_crc_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup CRC_Exported_Functions CRC Exported Functions + * @{ + */ + +/* Initialization and de-initialization functions ****************************/ +/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc); +HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc); +void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc); +void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc); +/** + * @} + */ + +/* Peripheral Control functions ***********************************************/ +/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions + * @{ + */ +uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength); +uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength); +/** + * @} + */ + +/* Peripheral State and Error functions ***************************************/ +/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions + * @{ + */ +HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32L4xx_HAL_CRC_H */ diff --git a/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_crc_ex.h b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_crc_ex.h new file mode 100644 index 0000000..4fec05b --- /dev/null +++ b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_crc_ex.h @@ -0,0 +1,150 @@ +/** + ****************************************************************************** + * @file stm32l4xx_hal_crc_ex.h + * @author MCD Application Team + * @brief Header file of CRC HAL extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32L4xx_HAL_CRC_EX_H +#define STM32L4xx_HAL_CRC_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx_hal_def.h" + +/** @addtogroup STM32L4xx_HAL_Driver + * @{ + */ + +/** @addtogroup CRCEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup CRCEx_Exported_Constants CRC Extended Exported Constants + * @{ + */ + +/** @defgroup CRCEx_Input_Data_Inversion Input Data Inversion Modes + * @{ + */ +#define CRC_INPUTDATA_INVERSION_NONE 0x00000000U /*!< No input data inversion */ +#define CRC_INPUTDATA_INVERSION_BYTE CRC_CR_REV_IN_0 /*!< Byte-wise input data inversion */ +#define CRC_INPUTDATA_INVERSION_HALFWORD CRC_CR_REV_IN_1 /*!< HalfWord-wise input data inversion */ +#define CRC_INPUTDATA_INVERSION_WORD CRC_CR_REV_IN /*!< Word-wise input data inversion */ +/** + * @} + */ + +/** @defgroup CRCEx_Output_Data_Inversion Output Data Inversion Modes + * @{ + */ +#define CRC_OUTPUTDATA_INVERSION_DISABLE 0x00000000U /*!< No output data inversion */ +#define CRC_OUTPUTDATA_INVERSION_ENABLE CRC_CR_REV_OUT /*!< Bit-wise output data inversion */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup CRCEx_Exported_Macros CRC Extended Exported Macros + * @{ + */ + +/** + * @brief Set CRC output reversal + * @param __HANDLE__ CRC handle + * @retval None + */ +#define __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT) + +/** + * @brief Unset CRC output reversal + * @param __HANDLE__ CRC handle + * @retval None + */ +#define __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT)) + +/** + * @brief Set CRC non-default polynomial + * @param __HANDLE__ CRC handle + * @param __POLYNOMIAL__ 7, 8, 16 or 32-bit polynomial + * @retval None + */ +#define __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__)) + +/** + * @} + */ + +/* Private macros --------------------------------------------------------*/ +/** @defgroup CRCEx_Private_Macros CRC Extended Private Macros + * @{ + */ + +#define IS_CRC_INPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_INPUTDATA_INVERSION_NONE) || \ + ((MODE) == CRC_INPUTDATA_INVERSION_BYTE) || \ + ((MODE) == CRC_INPUTDATA_INVERSION_HALFWORD) || \ + ((MODE) == CRC_INPUTDATA_INVERSION_WORD)) + +#define IS_CRC_OUTPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_OUTPUTDATA_INVERSION_DISABLE) || \ + ((MODE) == CRC_OUTPUTDATA_INVERSION_ENABLE)) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup CRCEx_Exported_Functions + * @{ + */ + +/** @addtogroup CRCEx_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions ****************************/ +HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength); +HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode); +HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32L4xx_HAL_CRC_EX_H */ diff --git a/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_bus.h b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_bus.h new file mode 100644 index 0000000..55927f3 --- /dev/null +++ b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_bus.h @@ -0,0 +1,1954 @@ +/** + ****************************************************************************** + * @file stm32l4xx_ll_bus.h + * @author MCD Application Team + * @brief Header file of BUS LL module. + + @verbatim + ##### RCC Limitations ##### + ============================================================================== + [..] + A delay between an RCC peripheral clock enable and the effective peripheral + enabling should be taken into account in order to manage the peripheral read/write + from/to registers. + (+) This delay depends on the peripheral mapping. + (++) AHB & APB peripherals, 1 dummy read is necessary + + [..] + Workarounds: + (#) For AHB & APB peripherals, a dummy read to the peripheral register has been + inserted in each LL_{BUS}_GRP{x}_EnableClock() function. + + @endverbatim + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32L4xx_LL_BUS_H +#define STM32L4xx_LL_BUS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx.h" + +/** @addtogroup STM32L4xx_LL_Driver + * @{ + */ + +#if defined(RCC) + +/** @defgroup BUS_LL BUS + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup BUS_LL_Exported_Constants BUS Exported Constants + * @{ + */ + +/** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH + * @{ + */ +#define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU +#define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN +#define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN +#if defined(DMAMUX1) +#define LL_AHB1_GRP1_PERIPH_DMAMUX1 RCC_AHB1ENR_DMAMUX1EN +#endif /* DMAMUX1 */ +#define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHB1ENR_FLASHEN +#define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN +#define LL_AHB1_GRP1_PERIPH_TSC RCC_AHB1ENR_TSCEN +#if defined(DMA2D) +#define LL_AHB1_GRP1_PERIPH_DMA2D RCC_AHB1ENR_DMA2DEN +#endif /* DMA2D */ +#if defined(GFXMMU) +#define LL_AHB1_GRP1_PERIPH_GFXMMU RCC_AHB1ENR_GFXMMUEN +#endif /* GFXMMU */ +#define LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1SMENR_SRAM1SMEN +/** + * @} + */ + +/** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH + * @{ + */ +#define LL_AHB2_GRP1_PERIPH_ALL 0xFFFFFFFFU +#define LL_AHB2_GRP1_PERIPH_GPIOA RCC_AHB2ENR_GPIOAEN +#define LL_AHB2_GRP1_PERIPH_GPIOB RCC_AHB2ENR_GPIOBEN +#define LL_AHB2_GRP1_PERIPH_GPIOC RCC_AHB2ENR_GPIOCEN +#if defined(GPIOD) +#define LL_AHB2_GRP1_PERIPH_GPIOD RCC_AHB2ENR_GPIODEN +#endif /*GPIOD*/ +#if defined(GPIOE) +#define LL_AHB2_GRP1_PERIPH_GPIOE RCC_AHB2ENR_GPIOEEN +#endif /*GPIOE*/ +#if defined(GPIOF) +#define LL_AHB2_GRP1_PERIPH_GPIOF RCC_AHB2ENR_GPIOFEN +#endif /* GPIOF */ +#if defined(GPIOG) +#define LL_AHB2_GRP1_PERIPH_GPIOG RCC_AHB2ENR_GPIOGEN +#endif /* GPIOG */ +#define LL_AHB2_GRP1_PERIPH_GPIOH RCC_AHB2ENR_GPIOHEN +#if defined(GPIOI) +#define LL_AHB2_GRP1_PERIPH_GPIOI RCC_AHB2ENR_GPIOIEN +#endif /* GPIOI */ +#if defined(USB_OTG_FS) +#define LL_AHB2_GRP1_PERIPH_OTGFS RCC_AHB2ENR_OTGFSEN +#endif /* USB_OTG_FS */ +#define LL_AHB2_GRP1_PERIPH_ADC RCC_AHB2ENR_ADCEN +#if defined(DCMI) +#define LL_AHB2_GRP1_PERIPH_DCMI RCC_AHB2ENR_DCMIEN +#endif /* DCMI */ +#if defined(AES) +#define LL_AHB2_GRP1_PERIPH_AES RCC_AHB2ENR_AESEN +#endif /* AES */ +#if defined(HASH) +#define LL_AHB2_GRP1_PERIPH_HASH RCC_AHB2ENR_HASHEN +#endif /* HASH */ +#define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN +#if defined(OCTOSPIM) +#define LL_AHB2_GRP1_PERIPH_OSPIM RCC_AHB2ENR_OSPIMEN +#endif /* OCTOSPIM */ +#if defined(PKA) +#define LL_AHB2_GRP1_PERIPH_PKA RCC_AHB2ENR_PKAEN +#endif /* PKA */ +#if defined(SDMMC1) && defined(RCC_AHB2ENR_SDMMC1EN) +#define LL_AHB2_GRP1_PERIPH_SDMMC1 RCC_AHB2ENR_SDMMC1EN +#endif /* SDMMC1 && RCC_AHB2ENR_SDMMC1EN */ +#define LL_AHB2_GRP1_PERIPH_SRAM2 RCC_AHB2SMENR_SRAM2SMEN +#if defined(SRAM3_BASE) +#define LL_AHB2_GRP1_PERIPH_SRAM3 RCC_AHB2SMENR_SRAM3SMEN +#endif /* SRAM3_BASE */ +/** + * @} + */ + +/** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH AHB3 GRP1 PERIPH + * @{ + */ +#define LL_AHB3_GRP1_PERIPH_ALL 0xFFFFFFFFU +#if defined(FMC_Bank1_R) +#define LL_AHB3_GRP1_PERIPH_FMC RCC_AHB3ENR_FMCEN +#endif /* FMC_Bank1_R */ +#if defined(QUADSPI) +#define LL_AHB3_GRP1_PERIPH_QSPI RCC_AHB3ENR_QSPIEN +#endif /* QUADSPI */ +#if defined(OCTOSPI1) +#define LL_AHB3_GRP1_PERIPH_OSPI1 RCC_AHB3ENR_OSPI1EN +#endif /* OCTOSPI1 */ +#if defined(OCTOSPI2) +#define LL_AHB3_GRP1_PERIPH_OSPI2 RCC_AHB3ENR_OSPI2EN +#endif /* OCTOSPI2 */ +/** + * @} + */ + +/** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH + * @{ + */ +#define LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU +#define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR1_TIM2EN +#if defined(TIM3) +#define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR1_TIM3EN +#endif /* TIM3 */ +#if defined(TIM4) +#define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR1_TIM4EN +#endif /* TIM4 */ +#if defined(TIM5) +#define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR1_TIM5EN +#endif /* TIM5 */ +#define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR1_TIM6EN +#define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR1_TIM7EN +#if defined(LCD) +#define LL_APB1_GRP1_PERIPH_LCD RCC_APB1ENR1_LCDEN +#endif /* LCD */ +#if defined(RCC_APB1ENR1_RTCAPBEN) +#define LL_APB1_GRP1_PERIPH_RTCAPB RCC_APB1ENR1_RTCAPBEN +#endif /* RCC_APB1ENR1_RTCAPBEN */ +#define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR1_WWDGEN +#if defined(SPI2) +#define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR1_SPI2EN +#endif /* SPI2 */ +#define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR1_SPI3EN +#define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR1_USART2EN +#if defined(USART3) +#define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR1_USART3EN +#endif /* USART3 */ +#if defined(UART4) +#define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR1_UART4EN +#endif /* UART4 */ +#if defined(UART5) +#define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR1_UART5EN +#endif /* UART5 */ +#define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR1_I2C1EN +#if defined(I2C2) +#define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR1_I2C2EN +#endif /* I2C2 */ +#define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR1_I2C3EN +#if defined(CRS) +#define LL_APB1_GRP1_PERIPH_CRS RCC_APB1ENR1_CRSEN +#endif /* CRS */ +#define LL_APB1_GRP1_PERIPH_CAN1 RCC_APB1ENR1_CAN1EN +#if defined(CAN2) +#define LL_APB1_GRP1_PERIPH_CAN2 RCC_APB1ENR1_CAN2EN +#endif /* CAN2 */ +#if defined(USB) +#define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR1_USBFSEN +#endif /* USB */ +#define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR1_PWREN +#define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR1_DAC1EN +#define LL_APB1_GRP1_PERIPH_OPAMP RCC_APB1ENR1_OPAMPEN +#define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR1_LPTIM1EN +/** + * @} + */ + + +/** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH APB1 GRP2 PERIPH + * @{ + */ +#define LL_APB1_GRP2_PERIPH_ALL 0xFFFFFFFFU +#define LL_APB1_GRP2_PERIPH_LPUART1 RCC_APB1ENR2_LPUART1EN +#if defined(I2C4) +#define LL_APB1_GRP2_PERIPH_I2C4 RCC_APB1ENR2_I2C4EN +#endif /* I2C4 */ +#if defined(SWPMI1) +#define LL_APB1_GRP2_PERIPH_SWPMI1 RCC_APB1ENR2_SWPMI1EN +#endif /* SWPMI1 */ +#define LL_APB1_GRP2_PERIPH_LPTIM2 RCC_APB1ENR2_LPTIM2EN +/** + * @} + */ + +/** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH + * @{ + */ +#define LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU +#define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN +#define LL_APB2_GRP1_PERIPH_FW RCC_APB2ENR_FWEN +#if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN) +#define LL_APB2_GRP1_PERIPH_SDMMC1 RCC_APB2ENR_SDMMC1EN +#endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */ +#define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN +#define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN +#if defined(TIM8) +#define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN +#endif /* TIM8 */ +#define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN +#define LL_APB2_GRP1_PERIPH_TIM15 RCC_APB2ENR_TIM15EN +#define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN +#if defined(TIM17) +#define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN +#endif /* TIM17 */ +#define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN +#if defined(SAI2) +#define LL_APB2_GRP1_PERIPH_SAI2 RCC_APB2ENR_SAI2EN +#endif /* SAI2 */ +#if defined(DFSDM1_Channel0) +#define LL_APB2_GRP1_PERIPH_DFSDM1 RCC_APB2ENR_DFSDM1EN +#endif /* DFSDM1_Channel0 */ +#if defined(LTDC) +#define LL_APB2_GRP1_PERIPH_LTDC RCC_APB2ENR_LTDCEN +#endif /* LTDC */ +#if defined(DSI) +#define LL_APB2_GRP1_PERIPH_DSI RCC_APB2ENR_DSIEN +#endif /* DSI */ +/** + * @} + */ + +/** Legacy definitions for compatibility purpose +@cond 0 +*/ +#if defined(DFSDM1_Channel0) +#define LL_APB2_GRP1_PERIPH_DFSDM LL_APB2_GRP1_PERIPH_DFSDM1 +#endif /* DFSDM1_Channel0 */ +/** +@endcond + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @defgroup BUS_LL_Exported_Functions BUS Exported Functions + * @{ + */ + +/** @defgroup BUS_LL_EF_AHB1 AHB1 + * @{ + */ + +/** + * @brief Enable AHB1 peripherals clock. + * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR DMAMUX1EN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR FLASHEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR TSCEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR DMA2DEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR GFXMMUEN LL_AHB1_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_TSC + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB1ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB1ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if AHB1 peripheral clock is enabled or not + * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR DMAMUX1EN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR FLASHEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR TSCEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR DMA2DEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR GFXMMUEN LL_AHB1_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_TSC + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*) + * + * (*) value not defined in all devices. + * @retval State of Periphs (1 or 0). +*/ +__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->AHB1ENR, Periphs) == Periphs) ? 1UL : 0UL); +} + +/** + * @brief Disable AHB1 peripherals clock. + * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR DMAMUX1EN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR FLASHEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR TSCEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR DMA2DEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR GFXMMUEN LL_AHB1_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_TSC + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB1ENR, Periphs); +} + +/** + * @brief Force AHB1 peripherals reset. + * @rmtoll AHB1RSTR DMA1RST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR DMA2RST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR DMAMUX1RST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR FLASHRST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR TSCRST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR GFXMMURST LL_AHB1_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_TSC + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->AHB1RSTR, Periphs); +} + +/** + * @brief Release AHB1 peripherals reset. + * @rmtoll AHB1RSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR DMA2RST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR DMAMUX1RST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR FLASHRST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR TSCRST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR GFXMMURST LL_AHB1_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_TSC + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB1RSTR, Periphs); +} + +/** + * @brief Enable AHB1 peripheral clocks in Sleep and Stop modes + * @rmtoll AHB1SMENR DMA1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n + * AHB1SMENR DMA2SMEN LL_AHB1_GRP1_EnableClockStopSleep\n + * AHB1SMENR DMAMUX1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n + * AHB1SMENR FLASHSMEN LL_AHB1_GRP1_EnableClockStopSleep\n + * AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n + * AHB1SMENR CRCSMEN LL_AHB1_GRP1_EnableClockStopSleep\n + * AHB1SMENR TSCSMEN LL_AHB1_GRP1_EnableClockStopSleep\n + * AHB1SMENR DMA2DSMEN LL_AHB1_GRP1_EnableClockStopSleep\n + * AHB1SMENR GFXMMUSMEN LL_AHB1_GRP1_EnableClockStopSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_TSC + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB1_GRP1_EnableClockStopSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB1SMENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB1SMENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable AHB1 peripheral clocks in Sleep and Stop modes + * @rmtoll AHB1SMENR DMA1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n + * AHB1SMENR DMA2SMEN LL_AHB1_GRP1_DisableClockStopSleep\n + * AHB1SMENR DMAMUX1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n + * AHB1SMENR FLASHSMEN LL_AHB1_GRP1_DisableClockStopSleep\n + * AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n + * AHB1SMENR CRCSMEN LL_AHB1_GRP1_DisableClockStopSleep\n + * AHB1SMENR TSCSMEN LL_AHB1_GRP1_DisableClockStopSleep\n + * AHB1SMENR DMA2DSMEN LL_AHB1_GRP1_DisableClockStopSleep\n + * AHB1SMENR GFXMMUSMEN LL_AHB1_GRP1_DisableClockStopSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_TSC + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB1_GRP1_DisableClockStopSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB1SMENR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_AHB2 AHB2 + * @{ + */ + +/** + * @brief Enable AHB2 peripherals clock. + * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR GPIOBEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR GPIOCEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR GPIODEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR GPIOEEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR GPIOFEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR GPIOGEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR GPIOHEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR GPIOIEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR OTGFSEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR ADCEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR DCMIEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR AESEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR HASHEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR OSPIMEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR SDMMC1EN LL_AHB2_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_ADC + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB2ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB2ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if AHB2 peripheral clock is enabled or not + * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR GPIOBEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR GPIOCEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR GPIODEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR GPIOEEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR GPIOFEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR GPIOGEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR GPIOHEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR GPIOIEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR OTGFSEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR ADCEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR DCMIEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR AESEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR HASHEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR OSPIMEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR SDMMC1EN LL_AHB2_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_ADC + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*) + * + * (*) value not defined in all devices. + * @retval State of Periphs (1 or 0). +*/ +__STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->AHB2ENR, Periphs) == Periphs) ? 1UL : 0UL); +} + +/** + * @brief Disable AHB2 peripherals clock. + * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR GPIOBEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR GPIOCEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR GPIODEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR GPIOEEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR GPIOFEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR GPIOGEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR GPIOHEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR GPIOIEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR OTGFSEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR ADCEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR DCMIEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR AESEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR HASHEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR OSPIMEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR SDMMC1EN LL_AHB2_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_ADC + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB2ENR, Periphs); +} + +/** + * @brief Force AHB2 peripherals reset. + * @rmtoll AHB2RSTR GPIOARST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR GPIOBRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR GPIOCRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR GPIODRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR GPIOERST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR GPIOFRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR GPIOGRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR GPIOHRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR GPIOIRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR ADCRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR DCMIRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR AESRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR HASHRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR OSPIMRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR SDMMC1RST LL_AHB2_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_ALL + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_ADC + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->AHB2RSTR, Periphs); +} + +/** + * @brief Release AHB2 peripherals reset. + * @rmtoll AHB2RSTR GPIOARST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR GPIOBRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR GPIOCRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR GPIODRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR GPIOERST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR GPIOFRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR GPIOGRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR GPIOHRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR GPIOIRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR ADCRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR DCMIRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR AESRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR HASHRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR OSPIMRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR SDMMC1RST LL_AHB2_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_ALL + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_ADC + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB2RSTR, Periphs); +} + +/** + * @brief Enable AHB2 peripheral clocks in Sleep and Stop modes + * @rmtoll AHB2SMENR GPIOASMEN LL_AHB2_GRP1_EnableClockStopSleep\n + * AHB2SMENR GPIOBSMEN LL_AHB2_GRP1_EnableClockStopSleep\n + * AHB2SMENR GPIOCSMEN LL_AHB2_GRP1_EnableClockStopSleep\n + * AHB2SMENR GPIODSMEN LL_AHB2_GRP1_EnableClockStopSleep\n + * AHB2SMENR GPIOESMEN LL_AHB2_GRP1_EnableClockStopSleep\n + * AHB2SMENR GPIOFSMEN LL_AHB2_GRP1_EnableClockStopSleep\n + * AHB2SMENR GPIOGSMEN LL_AHB2_GRP1_EnableClockStopSleep\n + * AHB2SMENR GPIOHSMEN LL_AHB2_GRP1_EnableClockStopSleep\n + * AHB2SMENR GPIOISMEN LL_AHB2_GRP1_EnableClockStopSleep\n + * AHB2SMENR SRAM2SMEN LL_AHB2_GRP1_EnableClockStopSleep\n + * AHB2SMENR SRAM3SMEN LL_AHB2_GRP1_EnableClockStopSleep\n + * AHB2SMENR OTGFSSMEN LL_AHB2_GRP1_EnableClockStopSleep\n + * AHB2SMENR ADCSMEN LL_AHB2_GRP1_EnableClockStopSleep\n + * AHB2SMENR DCMISMEN LL_AHB2_GRP1_EnableClockStopSleep\n + * AHB2SMENR AESSMEN LL_AHB2_GRP1_EnableClockStopSleep\n + * AHB2SMENR HASHSMEN LL_AHB2_GRP1_EnableClockStopSleep\n + * AHB2SMENR RNGSMEN LL_AHB2_GRP1_EnableClockStopSleep\n + * AHB2SMENR OSPIMSMEN LL_AHB2_GRP1_EnableClockStopSleep\n + * AHB2SMENR SDMMC1SMEN LL_AHB2_GRP1_EnableClockStopSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2 + * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM3 (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_ADC + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB2_GRP1_EnableClockStopSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB2SMENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB2SMENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable AHB2 peripheral clocks in Sleep and Stop modes + * @rmtoll AHB2SMENR GPIOASMEN LL_AHB2_GRP1_DisableClockStopSleep\n + * AHB2SMENR GPIOBSMEN LL_AHB2_GRP1_DisableClockStopSleep\n + * AHB2SMENR GPIOCSMEN LL_AHB2_GRP1_DisableClockStopSleep\n + * AHB2SMENR GPIODSMEN LL_AHB2_GRP1_DisableClockStopSleep\n + * AHB2SMENR GPIOESMEN LL_AHB2_GRP1_DisableClockStopSleep\n + * AHB2SMENR GPIOFSMEN LL_AHB2_GRP1_DisableClockStopSleep\n + * AHB2SMENR GPIOGSMEN LL_AHB2_GRP1_DisableClockStopSleep\n + * AHB2SMENR GPIOHSMEN LL_AHB2_GRP1_DisableClockStopSleep\n + * AHB2SMENR GPIOISMEN LL_AHB2_GRP1_DisableClockStopSleep\n + * AHB2SMENR SRAM2SMEN LL_AHB2_GRP1_DisableClockStopSleep\n + * AHB2SMENR SRAM3SMEN LL_AHB2_GRP1_DisableClockStopSleep\n + * AHB2SMENR OTGFSSMEN LL_AHB2_GRP1_DisableClockStopSleep\n + * AHB2SMENR ADCSMEN LL_AHB2_GRP1_DisableClockStopSleep\n + * AHB2SMENR DCMISMEN LL_AHB2_GRP1_DisableClockStopSleep\n + * AHB2SMENR AESSMEN LL_AHB2_GRP1_DisableClockStopSleep\n + * AHB2SMENR HASHSMEN LL_AHB2_GRP1_DisableClockStopSleep\n + * AHB2SMENR RNGSMEN LL_AHB2_GRP1_DisableClockStopSleep\n + * AHB2SMENR OSPIMSMEN LL_AHB2_GRP1_DisableClockStopSleep\n + * AHB2SMENR SDMMC1SMEN LL_AHB2_GRP1_DisableClockStopSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2 + * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM3 (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_ADC + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB2_GRP1_DisableClockStopSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB2SMENR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_AHB3 AHB3 + * @{ + */ + +/** + * @brief Enable AHB3 peripherals clock. + * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_EnableClock\n + * AHB3ENR QSPIEN LL_AHB3_GRP1_EnableClock\n + * AHB3ENR OSPI1EN LL_AHB3_GRP1_EnableClock\n + * AHB3ENR OSPI2EN LL_AHB3_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB3ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB3ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if AHB3 peripheral clock is enabled or not + * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR QSPIEN LL_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR OSPI1EN LL_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR OSPI2EN LL_AHB3_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) + * + * (*) value not defined in all devices. + * @retval State of Periphs (1 or 0). +*/ +__STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->AHB3ENR, Periphs) == Periphs) ? 1UL : 0UL); +} + +/** + * @brief Disable AHB3 peripherals clock. + * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_DisableClock\n + * AHB3ENR QSPIEN LL_AHB3_GRP1_DisableClock\n + * AHB3ENR OSPI1EN LL_AHB3_GRP1_DisableClock\n + * AHB3ENR OSPI2EN LL_AHB3_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB3ENR, Periphs); +} + +/** + * @brief Force AHB3 peripherals reset. + * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ForceReset\n + * AHB3RSTR QSPIRST LL_AHB3_GRP1_ForceReset\n + * AHB3RSTR OSPI1RST LL_AHB3_GRP1_ForceReset\n + * AHB3RSTR OSPI2RST LL_AHB3_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_ALL + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->AHB3RSTR, Periphs); +} + +/** + * @brief Release AHB3 peripherals reset. + * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ReleaseReset\n + * AHB3RSTR QSPIRST LL_AHB3_GRP1_ReleaseReset\n + * AHB3RSTR OSPI1RST LL_AHB3_GRP1_ReleaseReset\n + * AHB3RSTR OSPI2RST LL_AHB3_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_ALL + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB3RSTR, Periphs); +} + +/** + * @brief Enable AHB3 peripheral clocks in Sleep and Stop modes + * @rmtoll AHB3SMENR FMCSMEN LL_AHB3_GRP1_EnableClockStopSleep\n + * AHB3SMENR QSPISMEN LL_AHB3_GRP1_EnableClockStopSleep\n + * AHB3SMENR OSPI1SMEN LL_AHB3_GRP1_EnableClockStopSleep\n + * AHB3SMENR OSPI2SMEN LL_AHB3_GRP1_EnableClockStopSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB3_GRP1_EnableClockStopSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB3SMENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB3SMENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable AHB3 peripheral clocks in Sleep and Stop modes + * @rmtoll AHB3SMENR FMCSMEN LL_AHB3_GRP1_DisableClockStopSleep\n + * AHB3SMENR QSPISMEN LL_AHB3_GRP1_DisableClockStopSleep\n + * AHB3SMENR OSPI1SMEN LL_AHB3_GRP1_DisableClockStopSleep\n + * AHB3SMENR OSPI2SMEN LL_AHB3_GRP1_DisableClockStopSleep\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB3_GRP1_DisableClockStopSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB3SMENR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_APB1 APB1 + * @{ + */ + +/** + * @brief Enable APB1 peripherals clock. + * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_EnableClock\n + * APB1ENR1 TIM3EN LL_APB1_GRP1_EnableClock\n + * APB1ENR1 TIM4EN LL_APB1_GRP1_EnableClock\n + * APB1ENR1 TIM5EN LL_APB1_GRP1_EnableClock\n + * APB1ENR1 TIM6EN LL_APB1_GRP1_EnableClock\n + * APB1ENR1 TIM7EN LL_APB1_GRP1_EnableClock\n + * APB1ENR1 LCDEN LL_APB1_GRP1_EnableClock\n + * APB1ENR1 RTCAPBEN LL_APB1_GRP1_EnableClock\n + * APB1ENR1 WWDGEN LL_APB1_GRP1_EnableClock\n + * APB1ENR1 SPI2EN LL_APB1_GRP1_EnableClock\n + * APB1ENR1 SPI3EN LL_APB1_GRP1_EnableClock\n + * APB1ENR1 USART2EN LL_APB1_GRP1_EnableClock\n + * APB1ENR1 USART3EN LL_APB1_GRP1_EnableClock\n + * APB1ENR1 UART4EN LL_APB1_GRP1_EnableClock\n + * APB1ENR1 UART5EN LL_APB1_GRP1_EnableClock\n + * APB1ENR1 I2C1EN LL_APB1_GRP1_EnableClock\n + * APB1ENR1 I2C2EN LL_APB1_GRP1_EnableClock\n + * APB1ENR1 I2C3EN LL_APB1_GRP1_EnableClock\n + * APB1ENR1 CRSEN LL_APB1_GRP1_EnableClock\n + * APB1ENR1 CAN1EN LL_APB1_GRP1_EnableClock\n + * APB1ENR1 USBFSEN LL_APB1_GRP1_EnableClock\n + * APB1ENR1 CAN2EN LL_APB1_GRP1_EnableClock\n + * APB1ENR1 PWREN LL_APB1_GRP1_EnableClock\n + * APB1ENR1 DAC1EN LL_APB1_GRP1_EnableClock\n + * APB1ENR1 OPAMPEN LL_APB1_GRP1_EnableClock\n + * APB1ENR1 LPTIM1EN LL_APB1_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 + * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 + * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB1ENR1, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB1ENR1, Periphs); + (void)tmpreg; +} + +/** + * @brief Enable APB1 peripherals clock. + * @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_EnableClock\n + * APB1ENR2 I2C4EN LL_APB1_GRP2_EnableClock\n + * APB1ENR2 SWPMI1EN LL_APB1_GRP2_EnableClock\n + * APB1ENR2 LPTIM2EN LL_APB1_GRP2_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 + * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB1ENR2, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB1ENR2, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if APB1 peripheral clock is enabled or not + * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 TIM3EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 TIM4EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 TIM5EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 TIM6EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 TIM7EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 LCDEN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 RTCAPBEN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 WWDGEN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 SPI2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 SPI3EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 USART2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 USART3EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 UART4EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 UART5EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 I2C1EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 I2C2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 I2C3EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 CRSEN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 CAN1EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 USBFSEN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 CAN2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 PWREN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 DAC1EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 OPAMPEN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 LPTIM1EN LL_APB1_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 + * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 + * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * + * (*) value not defined in all devices. + * @retval State of Periphs (1 or 0). +*/ +__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->APB1ENR1, Periphs) == Periphs) ? 1UL : 0UL); +} + +/** + * @brief Check if APB1 peripheral clock is enabled or not + * @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_IsEnabledClock\n + * APB1ENR2 I2C4EN LL_APB1_GRP2_IsEnabledClock\n + * APB1ENR2 SWPMI1EN LL_APB1_GRP2_IsEnabledClock\n + * APB1ENR2 LPTIM2EN LL_APB1_GRP2_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 + * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 + * + * (*) value not defined in all devices. + * @retval State of Periphs (1 or 0). +*/ +__STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->APB1ENR2, Periphs) == Periphs) ? 1UL : 0UL); +} + +/** + * @brief Disable APB1 peripherals clock. + * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_DisableClock\n + * APB1ENR1 TIM3EN LL_APB1_GRP1_DisableClock\n + * APB1ENR1 TIM4EN LL_APB1_GRP1_DisableClock\n + * APB1ENR1 TIM5EN LL_APB1_GRP1_DisableClock\n + * APB1ENR1 TIM6EN LL_APB1_GRP1_DisableClock\n + * APB1ENR1 TIM7EN LL_APB1_GRP1_DisableClock\n + * APB1ENR1 LCDEN LL_APB1_GRP1_DisableClock\n + * APB1ENR1 RTCAPBEN LL_APB1_GRP1_DisableClock\n + * APB1ENR1 WWDGEN LL_APB1_GRP1_DisableClock\n + * APB1ENR1 SPI2EN LL_APB1_GRP1_DisableClock\n + * APB1ENR1 SPI3EN LL_APB1_GRP1_DisableClock\n + * APB1ENR1 USART2EN LL_APB1_GRP1_DisableClock\n + * APB1ENR1 USART3EN LL_APB1_GRP1_DisableClock\n + * APB1ENR1 UART4EN LL_APB1_GRP1_DisableClock\n + * APB1ENR1 UART5EN LL_APB1_GRP1_DisableClock\n + * APB1ENR1 I2C1EN LL_APB1_GRP1_DisableClock\n + * APB1ENR1 I2C2EN LL_APB1_GRP1_DisableClock\n + * APB1ENR1 I2C3EN LL_APB1_GRP1_DisableClock\n + * APB1ENR1 CRSEN LL_APB1_GRP1_DisableClock\n + * APB1ENR1 CAN1EN LL_APB1_GRP1_DisableClock\n + * APB1ENR1 USBFSEN LL_APB1_GRP1_DisableClock\n + * APB1ENR1 CAN2EN LL_APB1_GRP1_DisableClock\n + * APB1ENR1 PWREN LL_APB1_GRP1_DisableClock\n + * APB1ENR1 DAC1EN LL_APB1_GRP1_DisableClock\n + * APB1ENR1 OPAMPEN LL_APB1_GRP1_DisableClock\n + * APB1ENR1 LPTIM1EN LL_APB1_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 + * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 + * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1ENR1, Periphs); +} + +/** + * @brief Disable APB1 peripherals clock. + * @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_DisableClock\n + * APB1ENR2 I2C4EN LL_APB1_GRP2_DisableClock\n + * APB1ENR2 SWPMI1EN LL_APB1_GRP2_DisableClock\n + * APB1ENR2 LPTIM2EN LL_APB1_GRP2_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 + * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1ENR2, Periphs); +} + +/** + * @brief Force APB1 peripherals reset. + * @rmtoll APB1RSTR1 TIM2RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR1 TIM3RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR1 TIM4RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR1 TIM5RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR1 TIM6RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR1 TIM7RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR1 LCDRST LL_APB1_GRP1_ForceReset\n + * APB1RSTR1 SPI2RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR1 SPI3RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR1 USART2RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR1 USART3RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR1 UART4RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR1 UART5RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR1 I2C1RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR1 I2C2RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR1 I2C3RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR1 CRSRST LL_APB1_GRP1_ForceReset\n + * APB1RSTR1 CAN1RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR1 USBFSRST LL_APB1_GRP1_ForceReset\n + * APB1RSTR1 CAN2RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR1 PWRRST LL_APB1_GRP1_ForceReset\n + * APB1RSTR1 DAC1RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR1 OPAMPRST LL_APB1_GRP1_ForceReset\n + * APB1RSTR1 LPTIM1RST LL_APB1_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_ALL + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 + * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 + * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->APB1RSTR1, Periphs); +} + +/** + * @brief Force APB1 peripherals reset. + * @rmtoll APB1RSTR2 LPUART1RST LL_APB1_GRP2_ForceReset\n + * APB1RSTR2 I2C4RST LL_APB1_GRP2_ForceReset\n + * APB1RSTR2 SWPMI1RST LL_APB1_GRP2_ForceReset\n + * APB1RSTR2 LPTIM2RST LL_APB1_GRP2_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_ALL + * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 + * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->APB1RSTR2, Periphs); +} + +/** + * @brief Release APB1 peripherals reset. + * @rmtoll APB1RSTR1 TIM2RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR1 TIM3RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR1 TIM4RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR1 TIM5RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR1 TIM6RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR1 TIM7RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR1 LCDRST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR1 SPI2RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR1 SPI3RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR1 USART2RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR1 USART3RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR1 UART4RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR1 UART5RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR1 I2C1RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR1 I2C2RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR1 I2C3RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR1 CRSRST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR1 CAN1RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR1 USBFSRST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR1 CAN2RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR1 PWRRST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR1 DAC1RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR1 OPAMPRST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR1 LPTIM1RST LL_APB1_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_ALL + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 + * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 + * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1RSTR1, Periphs); +} + +/** + * @brief Release APB1 peripherals reset. + * @rmtoll APB1RSTR2 LPUART1RST LL_APB1_GRP2_ReleaseReset\n + * APB1RSTR2 I2C4RST LL_APB1_GRP2_ReleaseReset\n + * APB1RSTR2 SWPMI1RST LL_APB1_GRP2_ReleaseReset\n + * APB1RSTR2 LPTIM2RST LL_APB1_GRP2_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_ALL + * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 + * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1RSTR2, Periphs); +} + +/** + * @brief Enable APB1 peripheral clocks in Sleep and Stop modes + * @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_EnableClockStopSleep\n + * APB1SMENR1 TIM3SMEN LL_APB1_GRP1_EnableClockStopSleep\n + * APB1SMENR1 TIM4SMEN LL_APB1_GRP1_EnableClockStopSleep\n + * APB1SMENR1 TIM5SMEN LL_APB1_GRP1_EnableClockStopSleep\n + * APB1SMENR1 TIM6SMEN LL_APB1_GRP1_EnableClockStopSleep\n + * APB1SMENR1 TIM7SMEN LL_APB1_GRP1_EnableClockStopSleep\n + * APB1SMENR1 LCDSMEN LL_APB1_GRP1_EnableClockStopSleep\n + * APB1SMENR1 RTCAPBSMEN LL_APB1_GRP1_EnableClockStopSleep\n + * APB1SMENR1 WWDGSMEN LL_APB1_GRP1_EnableClockStopSleep\n + * APB1SMENR1 SPI2SMEN LL_APB1_GRP1_EnableClockStopSleep\n + * APB1SMENR1 SPI3SMEN LL_APB1_GRP1_EnableClockStopSleep\n + * APB1SMENR1 USART2SMEN LL_APB1_GRP1_EnableClockStopSleep\n + * APB1SMENR1 USART3SMEN LL_APB1_GRP1_EnableClockStopSleep\n + * APB1SMENR1 UART4SMEN LL_APB1_GRP1_EnableClockStopSleep\n + * APB1SMENR1 UART5SMEN LL_APB1_GRP1_EnableClockStopSleep\n + * APB1SMENR1 I2C1SMEN LL_APB1_GRP1_EnableClockStopSleep\n + * APB1SMENR1 I2C2SMEN LL_APB1_GRP1_EnableClockStopSleep\n + * APB1SMENR1 I2C3SMEN LL_APB1_GRP1_EnableClockStopSleep\n + * APB1SMENR1 CRSSMEN LL_APB1_GRP1_EnableClockStopSleep\n + * APB1SMENR1 CAN1SMEN LL_APB1_GRP1_EnableClockStopSleep\n + * APB1SMENR1 USBFSSMEN LL_APB1_GRP1_EnableClockStopSleep\n + * APB1SMENR1 CAN2SMEN LL_APB1_GRP1_EnableClockStopSleep\n + * APB1SMENR1 PWRSMEN LL_APB1_GRP1_EnableClockStopSleep\n + * APB1SMENR1 DAC1SMEN LL_APB1_GRP1_EnableClockStopSleep\n + * APB1SMENR1 OPAMPSMEN LL_APB1_GRP1_EnableClockStopSleep\n + * APB1SMENR1 LPTIM1SMEN LL_APB1_GRP1_EnableClockStopSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 + * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 + * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP1_EnableClockStopSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB1SMENR1, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB1SMENR1, Periphs); + (void)tmpreg; +} + +/** + * @brief Enable APB1 peripheral clocks in Sleep and Stop modes + * @rmtoll APB1SMENR2 LPUART1SMEN LL_APB1_GRP2_EnableClockStopSleep\n + * APB1SMENR2 I2C4SMEN LL_APB1_GRP2_EnableClockStopSleep\n + * APB1SMENR2 SWPMI1SMEN LL_APB1_GRP2_EnableClockStopSleep\n + * APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_EnableClockStopSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 + * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP2_EnableClockStopSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB1SMENR2, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB1SMENR2, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable APB1 peripheral clocks in Sleep and Stop modes + * @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_DisableClockStopSleep\n + * APB1SMENR1 TIM3SMEN LL_APB1_GRP1_DisableClockStopSleep\n + * APB1SMENR1 TIM4SMEN LL_APB1_GRP1_DisableClockStopSleep\n + * APB1SMENR1 TIM5SMEN LL_APB1_GRP1_DisableClockStopSleep\n + * APB1SMENR1 TIM6SMEN LL_APB1_GRP1_DisableClockStopSleep\n + * APB1SMENR1 TIM7SMEN LL_APB1_GRP1_DisableClockStopSleep\n + * APB1SMENR1 LCDSMEN LL_APB1_GRP1_DisableClockStopSleep\n + * APB1SMENR1 RTCAPBSMEN LL_APB1_GRP1_DisableClockStopSleep\n + * APB1SMENR1 WWDGSMEN LL_APB1_GRP1_DisableClockStopSleep\n + * APB1SMENR1 SPI2SMEN LL_APB1_GRP1_DisableClockStopSleep\n + * APB1SMENR1 SPI3SMEN LL_APB1_GRP1_DisableClockStopSleep\n + * APB1SMENR1 USART2SMEN LL_APB1_GRP1_DisableClockStopSleep\n + * APB1SMENR1 USART3SMEN LL_APB1_GRP1_DisableClockStopSleep\n + * APB1SMENR1 UART4SMEN LL_APB1_GRP1_DisableClockStopSleep\n + * APB1SMENR1 UART5SMEN LL_APB1_GRP1_DisableClockStopSleep\n + * APB1SMENR1 I2C1SMEN LL_APB1_GRP1_DisableClockStopSleep\n + * APB1SMENR1 I2C2SMEN LL_APB1_GRP1_DisableClockStopSleep\n + * APB1SMENR1 I2C3SMEN LL_APB1_GRP1_DisableClockStopSleep\n + * APB1SMENR1 CRSSMEN LL_APB1_GRP1_DisableClockStopSleep\n + * APB1SMENR1 CAN1SMEN LL_APB1_GRP1_DisableClockStopSleep\n + * APB1SMENR1 USBFSSMEN LL_APB1_GRP1_DisableClockStopSleep\n + * APB1SMENR1 CAN2SMEN LL_APB1_GRP1_DisableClockStopSleep\n + * APB1SMENR1 PWRSMEN LL_APB1_GRP1_DisableClockStopSleep\n + * APB1SMENR1 DAC1SMEN LL_APB1_GRP1_DisableClockStopSleep\n + * APB1SMENR1 OPAMPSMEN LL_APB1_GRP1_DisableClockStopSleep\n + * APB1SMENR1 LPTIM1SMEN LL_APB1_GRP1_DisableClockStopSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 + * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 + * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP1_DisableClockStopSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1SMENR1, Periphs); +} + +/** + * @brief Disable APB1 peripheral clocks in Sleep and Stop modes + * @rmtoll APB1SMENR2 LPUART1SMEN LL_APB1_GRP2_DisableClockStopSleep\n + * APB1SMENR2 I2C4SMEN LL_APB1_GRP2_DisableClockStopSleep\n + * APB1SMENR2 SWPMI1SMEN LL_APB1_GRP2_DisableClockStopSleep\n + * APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_DisableClockStopSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 + * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP2_DisableClockStopSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1SMENR2, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_APB2 APB2 + * @{ + */ + +/** + * @brief Enable APB2 peripherals clock. + * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock\n + * APB2ENR FWEN LL_APB2_GRP1_EnableClock\n + * APB2ENR SDMMC1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n + * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR TIM15EN LL_APB2_GRP1_EnableClock\n + * APB2ENR TIM16EN LL_APB2_GRP1_EnableClock\n + * APB2ENR TIM17EN LL_APB2_GRP1_EnableClock\n + * APB2ENR SAI1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR SAI2EN LL_APB2_GRP1_EnableClock\n + * APB2ENR DFSDM1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR LTDCEN LL_APB2_GRP1_EnableClock\n + * APB2ENR DSIEN LL_APB2_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB2_GRP1_PERIPH_FW + * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB2ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB2ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if APB2 peripheral clock is enabled or not + * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR FWEN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SDMMC1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM15EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM16EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SAI2EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR DFSDM1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR LTDCEN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR DSIEN LL_APB2_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB2_GRP1_PERIPH_FW + * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) + * + * (*) value not defined in all devices. + * @retval State of Periphs (1 or 0). +*/ +__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->APB2ENR, Periphs) == Periphs) ? 1UL : 0UL); +} + +/** + * @brief Disable APB2 peripherals clock. + * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_DisableClock\n + * APB2ENR SDMMC1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n + * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR TIM15EN LL_APB2_GRP1_DisableClock\n + * APB2ENR TIM16EN LL_APB2_GRP1_DisableClock\n + * APB2ENR TIM17EN LL_APB2_GRP1_DisableClock\n + * APB2ENR SAI1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR SAI2EN LL_APB2_GRP1_DisableClock\n + * APB2ENR DFSDM1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR LTDCEN LL_APB2_GRP1_DisableClock\n + * APB2ENR DSIEN LL_APB2_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB2ENR, Periphs); +} + +/** + * @brief Force APB2 peripherals reset. + * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SDMMC1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR TIM15RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SAI2RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR DFSDM1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR LTDCRST LL_APB2_GRP1_ForceReset\n + * APB2RSTR DSIRST LL_APB2_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_ALL + * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->APB2RSTR, Periphs); +} + +/** + * @brief Release APB2 peripherals reset. + * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SDMMC1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR TIM15RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR TIM16RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR TIM17RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SAI1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SAI2RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR DFSDM1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR LTDCRST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR DSIRST LL_APB2_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_ALL + * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB2RSTR, Periphs); +} + +/** + * @brief Enable APB2 peripheral clocks in Sleep and Stop modes + * @rmtoll APB2SMENR SYSCFGSMEN LL_APB2_GRP1_EnableClockStopSleep\n + * APB2SMENR SDMMC1SMEN LL_APB2_GRP1_EnableClockStopSleep\n + * APB2SMENR TIM1SMEN LL_APB2_GRP1_EnableClockStopSleep\n + * APB2SMENR SPI1SMEN LL_APB2_GRP1_EnableClockStopSleep\n + * APB2SMENR TIM8SMEN LL_APB2_GRP1_EnableClockStopSleep\n + * APB2SMENR USART1SMEN LL_APB2_GRP1_EnableClockStopSleep\n + * APB2SMENR TIM15SMEN LL_APB2_GRP1_EnableClockStopSleep\n + * APB2SMENR TIM16SMEN LL_APB2_GRP1_EnableClockStopSleep\n + * APB2SMENR TIM17SMEN LL_APB2_GRP1_EnableClockStopSleep\n + * APB2SMENR SAI1SMEN LL_APB2_GRP1_EnableClockStopSleep\n + * APB2SMENR SAI2SMEN LL_APB2_GRP1_EnableClockStopSleep\n + * APB2SMENR DFSDM1SMEN LL_APB2_GRP1_EnableClockStopSleep\n + * APB2SMENR LTDCSMEN LL_APB2_GRP1_EnableClockStopSleep\n + * APB2SMENR DSISMEN LL_APB2_GRP1_EnableClockStopSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB2_GRP1_EnableClockStopSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB2SMENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB2SMENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable APB2 peripheral clocks in Sleep and Stop modes + * @rmtoll APB2SMENR SYSCFGSMEN LL_APB2_GRP1_DisableClockStopSleep\n + * APB2SMENR SDMMC1SMEN LL_APB2_GRP1_DisableClockStopSleep\n + * APB2SMENR TIM1SMEN LL_APB2_GRP1_DisableClockStopSleep\n + * APB2SMENR SPI1SMEN LL_APB2_GRP1_DisableClockStopSleep\n + * APB2SMENR TIM8SMEN LL_APB2_GRP1_DisableClockStopSleep\n + * APB2SMENR USART1SMEN LL_APB2_GRP1_DisableClockStopSleep\n + * APB2SMENR TIM15SMEN LL_APB2_GRP1_DisableClockStopSleep\n + * APB2SMENR TIM16SMEN LL_APB2_GRP1_DisableClockStopSleep\n + * APB2SMENR TIM17SMEN LL_APB2_GRP1_DisableClockStopSleep\n + * APB2SMENR SAI1SMEN LL_APB2_GRP1_DisableClockStopSleep\n + * APB2SMENR SAI2SMEN LL_APB2_GRP1_DisableClockStopSleep\n + * APB2SMENR DFSDM1SMEN LL_APB2_GRP1_DisableClockStopSleep\n + * APB2SMENR LTDCSMEN LL_APB2_GRP1_DisableClockStopSleep\n + * APB2SMENR DSISMEN LL_APB2_GRP1_DisableClockStopSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB2_GRP1_DisableClockStopSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB2SMENR, Periphs); +} + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(RCC) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32L4xx_LL_BUS_H */ + diff --git a/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_cortex.h b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_cortex.h new file mode 100644 index 0000000..4ad94d6 --- /dev/null +++ b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_cortex.h @@ -0,0 +1,637 @@ +/** + ****************************************************************************** + * @file stm32l4xx_ll_cortex.h + * @author MCD Application Team + * @brief Header file of CORTEX LL module. + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The LL CORTEX driver contains a set of generic APIs that can be + used by user: + (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick + functions + (+) Low power mode configuration (SCB register of Cortex-MCU) + (+) MPU API to configure and enable regions + (+) API to access to MCU info (CPUID register) + (+) API to enable fault handler (SHCSR accesses) + + @endverbatim + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32L4xx_LL_CORTEX_H +#define STM32L4xx_LL_CORTEX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx.h" + +/** @addtogroup STM32L4xx_LL_Driver + * @{ + */ + +/** @defgroup CORTEX_LL CORTEX + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants + * @{ + */ + +/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source + * @{ + */ +#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/ +#define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_FAULT Handler Fault type + * @{ + */ +#define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */ +#define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */ +#define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */ +/** + * @} + */ + +#if __MPU_PRESENT + +/** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control + * @{ + */ +#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000U /*!< Disable NMI and privileged SW access */ +#define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */ +#define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */ +#define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_REGION MPU Region Number + * @{ + */ +#define LL_MPU_REGION_NUMBER0 0x00U /*!< REGION Number 0 */ +#define LL_MPU_REGION_NUMBER1 0x01U /*!< REGION Number 1 */ +#define LL_MPU_REGION_NUMBER2 0x02U /*!< REGION Number 2 */ +#define LL_MPU_REGION_NUMBER3 0x03U /*!< REGION Number 3 */ +#define LL_MPU_REGION_NUMBER4 0x04U /*!< REGION Number 4 */ +#define LL_MPU_REGION_NUMBER5 0x05U /*!< REGION Number 5 */ +#define LL_MPU_REGION_NUMBER6 0x06U /*!< REGION Number 6 */ +#define LL_MPU_REGION_NUMBER7 0x07U /*!< REGION Number 7 */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size + * @{ + */ +#define LL_MPU_REGION_SIZE_32B (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_64B (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_128B (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_2KB (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_4KB (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_8KB (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_16KB (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_32KB (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_64KB (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_128KB (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_256KB (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_512KB (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_1MB (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_2MB (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_4MB (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_8MB (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_16MB (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_32MB (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_64MB (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_128MB (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_256MB (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_512MB (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_1GB (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_2GB (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_4GB (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges + * @{ + */ +#define LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos) /*!< No access*/ +#define LL_MPU_REGION_PRIV_RW (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/ +#define LL_MPU_REGION_PRIV_RW_URO (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */ +#define LL_MPU_REGION_FULL_ACCESS (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */ +#define LL_MPU_REGION_PRIV_RO (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/ +#define LL_MPU_REGION_PRIV_RO_URO (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_TEX MPU TEX Level + * @{ + */ +#define LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */ +#define LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */ +#define LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */ +#define LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access + * @{ + */ +#define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00U /*!< Instruction fetches enabled */ +#define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access + * @{ + */ +#define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */ +#define LL_MPU_ACCESS_NOT_SHAREABLE 0x00U /*!< Not Shareable memory attribute */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access + * @{ + */ +#define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */ +#define LL_MPU_ACCESS_NOT_CACHEABLE 0x00U /*!< Not Cacheable memory attribute */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access + * @{ + */ +#define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */ +#define LL_MPU_ACCESS_NOT_BUFFERABLE 0x00U /*!< Not Bufferable memory attribute */ +/** + * @} + */ +#endif /* __MPU_PRESENT */ +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions + * @{ + */ + +/** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK + * @{ + */ + +/** + * @brief This function checks if the Systick counter flag is active or not. + * @note It can be used in timeout function on application side. + * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void) +{ + return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)); +} + +/** + * @brief Configures the SysTick clock source + * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK + * @retval None + */ +__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source) +{ + if (Source == LL_SYSTICK_CLKSOURCE_HCLK) + { + SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); + } + else + { + CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); + } +} + +/** + * @brief Get the SysTick clock source + * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK + */ +__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void) +{ + return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); +} + +/** + * @brief Enable SysTick exception request + * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT + * @retval None + */ +__STATIC_INLINE void LL_SYSTICK_EnableIT(void) +{ + SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief Disable SysTick exception request + * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT + * @retval None + */ +__STATIC_INLINE void LL_SYSTICK_DisableIT(void) +{ + CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief Checks if the SYSTICK interrupt is enabled or disabled. + * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void) +{ + return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)); +} + +/** + * @} + */ + +/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE + * @{ + */ + +/** + * @brief Processor uses sleep as its low power mode + * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableSleep(void) +{ + /* Clear SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); +} + +/** + * @brief Processor uses deep sleep as its low power mode + * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableDeepSleep(void) +{ + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); +} + +/** + * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode. + * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an + * empty main application. + * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void) +{ + /* Set SLEEPONEXIT bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); +} + +/** + * @brief Do not sleep when returning to Thread mode. + * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit + * @retval None + */ +__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void) +{ + /* Clear SLEEPONEXIT bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); +} + +/** + * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the + * processor. + * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableEventOnPend(void) +{ + /* Set SEVEONPEND bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); +} + +/** + * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are + * excluded + * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend + * @retval None + */ +__STATIC_INLINE void LL_LPM_DisableEventOnPend(void) +{ + /* Clear SEVEONPEND bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); +} + +/** + * @} + */ + +/** @defgroup CORTEX_LL_EF_HANDLER HANDLER + * @{ + */ + +/** + * @brief Enable a fault in System handler control register (SHCSR) + * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault + * @param Fault This parameter can be a combination of the following values: + * @arg @ref LL_HANDLER_FAULT_USG + * @arg @ref LL_HANDLER_FAULT_BUS + * @arg @ref LL_HANDLER_FAULT_MEM + * @retval None + */ +__STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault) +{ + /* Enable the system handler fault */ + SET_BIT(SCB->SHCSR, Fault); +} + +/** + * @brief Disable a fault in System handler control register (SHCSR) + * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault + * @param Fault This parameter can be a combination of the following values: + * @arg @ref LL_HANDLER_FAULT_USG + * @arg @ref LL_HANDLER_FAULT_BUS + * @arg @ref LL_HANDLER_FAULT_MEM + * @retval None + */ +__STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault) +{ + /* Disable the system handler fault */ + CLEAR_BIT(SCB->SHCSR, Fault); +} + +/** + * @} + */ + +/** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO + * @{ + */ + +/** + * @brief Get Implementer code + * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer + * @retval Value should be equal to 0x41 for ARM + */ +__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos); +} + +/** + * @brief Get Variant number (The r value in the rnpn product revision identifier) + * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant + * @retval Value between 0 and 255 (0x0: revision 0) + */ +__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos); +} + +/** + * @brief Get Constant number + * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant + * @retval Value should be equal to 0xF for Cortex-M4 devices + */ +__STATIC_INLINE uint32_t LL_CPUID_GetConstant(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos); +} + +/** + * @brief Get Part number + * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo + * @retval Value should be equal to 0xC24 for Cortex-M4 + */ +__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos); +} + +/** + * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release) + * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision + * @retval Value between 0 and 255 (0x1: patch 1) + */ +__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos); +} + +/** + * @} + */ + +#if __MPU_PRESENT +/** @defgroup CORTEX_LL_EF_MPU MPU + * @{ + */ + +/** + * @brief Enable MPU with input options + * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable + * @param Options This parameter can be one of the following values: + * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE + * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI + * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT + * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF + * @retval None + */ +__STATIC_INLINE void LL_MPU_Enable(uint32_t Options) +{ + /* Enable the MPU*/ + WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options)); + /* Ensure MPU settings take effects */ + __DSB(); + /* Sequence instruction fetches using update settings */ + __ISB(); +} + +/** + * @brief Disable MPU + * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable + * @retval None + */ +__STATIC_INLINE void LL_MPU_Disable(void) +{ + /* Make sure outstanding transfers are done */ + __DMB(); + /* Disable MPU*/ + WRITE_REG(MPU->CTRL, 0U); +} + +/** + * @brief Check if MPU is enabled or not + * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_MPU_IsEnabled(void) +{ + return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)); +} + +/** + * @brief Enable a MPU region + * @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @retval None + */ +__STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + /* Enable the MPU region */ + SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); +} + +/** + * @brief Configure and enable a region + * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n + * MPU_RBAR REGION LL_MPU_ConfigRegion\n + * MPU_RBAR ADDR LL_MPU_ConfigRegion\n + * MPU_RASR XN LL_MPU_ConfigRegion\n + * MPU_RASR AP LL_MPU_ConfigRegion\n + * MPU_RASR S LL_MPU_ConfigRegion\n + * MPU_RASR C LL_MPU_ConfigRegion\n + * MPU_RASR B LL_MPU_ConfigRegion\n + * MPU_RASR SIZE LL_MPU_ConfigRegion + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @param Address Value of region base address + * @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF + * @param Attributes This parameter can be a combination of the following values: + * @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B + * or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB + * or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB + * or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB + * or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB + * or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB + * @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS + * or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO + * @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4 + * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE + * @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE + * @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE + * @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE + * @retval None + */ +__STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + /* Set base address */ + WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U)); + /* Configure MPU */ + WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos)); +} + +/** + * @brief Disable a region + * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n + * MPU_RASR ENABLE LL_MPU_DisableRegion + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @retval None + */ +__STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + /* Disable the MPU region */ + CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); +} + +/** + * @} + */ + +#endif /* __MPU_PRESENT */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32L4xx_LL_CORTEX_H */ + diff --git a/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_crc.h b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_crc.h new file mode 100644 index 0000000..18690cf --- /dev/null +++ b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_crc.h @@ -0,0 +1,467 @@ +/** + ****************************************************************************** + * @file stm32l4xx_ll_crc.h + * @author MCD Application Team + * @brief Header file of CRC LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32L4xx_LL_CRC_H +#define STM32L4xx_LL_CRC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx.h" + +/** @addtogroup STM32L4xx_LL_Driver + * @{ + */ + +#if defined(CRC) + +/** @defgroup CRC_LL CRC + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup CRC_LL_Exported_Constants CRC Exported Constants + * @{ + */ + +/** @defgroup CRC_LL_EC_POLYLENGTH Polynomial length + * @{ + */ +#define LL_CRC_POLYLENGTH_32B 0x00000000U /*!< 32 bits Polynomial size */ +#define LL_CRC_POLYLENGTH_16B CRC_CR_POLYSIZE_0 /*!< 16 bits Polynomial size */ +#define LL_CRC_POLYLENGTH_8B CRC_CR_POLYSIZE_1 /*!< 8 bits Polynomial size */ +#define LL_CRC_POLYLENGTH_7B (CRC_CR_POLYSIZE_1 | CRC_CR_POLYSIZE_0) /*!< 7 bits Polynomial size */ +/** + * @} + */ + +/** @defgroup CRC_LL_EC_INDATA_REVERSE Input Data Reverse + * @{ + */ +#define LL_CRC_INDATA_REVERSE_NONE 0x00000000U /*!< Input Data bit order not affected */ +#define LL_CRC_INDATA_REVERSE_BYTE CRC_CR_REV_IN_0 /*!< Input Data bit reversal done by byte */ +#define LL_CRC_INDATA_REVERSE_HALFWORD CRC_CR_REV_IN_1 /*!< Input Data bit reversal done by half-word */ +#define LL_CRC_INDATA_REVERSE_WORD (CRC_CR_REV_IN_1 | CRC_CR_REV_IN_0) /*!< Input Data bit reversal done by word */ +/** + * @} + */ + +/** @defgroup CRC_LL_EC_OUTDATA_REVERSE Output Data Reverse + * @{ + */ +#define LL_CRC_OUTDATA_REVERSE_NONE 0x00000000U /*!< Output Data bit order not affected */ +#define LL_CRC_OUTDATA_REVERSE_BIT CRC_CR_REV_OUT /*!< Output Data bit reversal done by bit */ +/** + * @} + */ + +/** @defgroup CRC_LL_EC_Default_Polynomial_Value Default CRC generating polynomial value + * @brief Normal representation of this polynomial value is + * X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2 + X + 1 . + * @{ + */ +#define LL_CRC_DEFAULT_CRC32_POLY 0x04C11DB7U /*!< Default CRC generating polynomial value */ +/** + * @} + */ + +/** @defgroup CRC_LL_EC_Default_InitValue Default CRC computation initialization value + * @{ + */ +#define LL_CRC_DEFAULT_CRC_INITVALUE 0xFFFFFFFFU /*!< Default CRC computation initialization value */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup CRC_LL_Exported_Macros CRC Exported Macros + * @{ + */ + +/** @defgroup CRC_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in CRC register + * @param __INSTANCE__ CRC Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_CRC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, __VALUE__) + +/** + * @brief Read a value in CRC register + * @param __INSTANCE__ CRC Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_CRC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup CRC_LL_Exported_Functions CRC Exported Functions + * @{ + */ + +/** @defgroup CRC_LL_EF_Configuration CRC Configuration functions + * @{ + */ + +/** + * @brief Reset the CRC calculation unit. + * @note If Programmable Initial CRC value feature + * is available, also set the Data Register to the value stored in the + * CRC_INIT register, otherwise, reset Data Register to its default value. + * @rmtoll CR RESET LL_CRC_ResetCRCCalculationUnit + * @param CRCx CRC Instance + * @retval None + */ +__STATIC_INLINE void LL_CRC_ResetCRCCalculationUnit(CRC_TypeDef *CRCx) +{ + SET_BIT(CRCx->CR, CRC_CR_RESET); +} + +/** + * @brief Configure size of the polynomial. + * @rmtoll CR POLYSIZE LL_CRC_SetPolynomialSize + * @param CRCx CRC Instance + * @param PolySize This parameter can be one of the following values: + * @arg @ref LL_CRC_POLYLENGTH_32B + * @arg @ref LL_CRC_POLYLENGTH_16B + * @arg @ref LL_CRC_POLYLENGTH_8B + * @arg @ref LL_CRC_POLYLENGTH_7B + * @retval None + */ +__STATIC_INLINE void LL_CRC_SetPolynomialSize(CRC_TypeDef *CRCx, uint32_t PolySize) +{ + MODIFY_REG(CRCx->CR, CRC_CR_POLYSIZE, PolySize); +} + +/** + * @brief Return size of the polynomial. + * @rmtoll CR POLYSIZE LL_CRC_GetPolynomialSize + * @param CRCx CRC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_CRC_POLYLENGTH_32B + * @arg @ref LL_CRC_POLYLENGTH_16B + * @arg @ref LL_CRC_POLYLENGTH_8B + * @arg @ref LL_CRC_POLYLENGTH_7B + */ +__STATIC_INLINE uint32_t LL_CRC_GetPolynomialSize(CRC_TypeDef *CRCx) +{ + return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_POLYSIZE)); +} + +/** + * @brief Configure the reversal of the bit order of the input data + * @rmtoll CR REV_IN LL_CRC_SetInputDataReverseMode + * @param CRCx CRC Instance + * @param ReverseMode This parameter can be one of the following values: + * @arg @ref LL_CRC_INDATA_REVERSE_NONE + * @arg @ref LL_CRC_INDATA_REVERSE_BYTE + * @arg @ref LL_CRC_INDATA_REVERSE_HALFWORD + * @arg @ref LL_CRC_INDATA_REVERSE_WORD + * @retval None + */ +__STATIC_INLINE void LL_CRC_SetInputDataReverseMode(CRC_TypeDef *CRCx, uint32_t ReverseMode) +{ + MODIFY_REG(CRCx->CR, CRC_CR_REV_IN, ReverseMode); +} + +/** + * @brief Return type of reversal for input data bit order + * @rmtoll CR REV_IN LL_CRC_GetInputDataReverseMode + * @param CRCx CRC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_CRC_INDATA_REVERSE_NONE + * @arg @ref LL_CRC_INDATA_REVERSE_BYTE + * @arg @ref LL_CRC_INDATA_REVERSE_HALFWORD + * @arg @ref LL_CRC_INDATA_REVERSE_WORD + */ +__STATIC_INLINE uint32_t LL_CRC_GetInputDataReverseMode(CRC_TypeDef *CRCx) +{ + return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_REV_IN)); +} + +/** + * @brief Configure the reversal of the bit order of the Output data + * @rmtoll CR REV_OUT LL_CRC_SetOutputDataReverseMode + * @param CRCx CRC Instance + * @param ReverseMode This parameter can be one of the following values: + * @arg @ref LL_CRC_OUTDATA_REVERSE_NONE + * @arg @ref LL_CRC_OUTDATA_REVERSE_BIT + * @retval None + */ +__STATIC_INLINE void LL_CRC_SetOutputDataReverseMode(CRC_TypeDef *CRCx, uint32_t ReverseMode) +{ + MODIFY_REG(CRCx->CR, CRC_CR_REV_OUT, ReverseMode); +} + +/** + * @brief Return type of reversal of the bit order of the Output data + * @rmtoll CR REV_OUT LL_CRC_GetOutputDataReverseMode + * @param CRCx CRC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_CRC_OUTDATA_REVERSE_NONE + * @arg @ref LL_CRC_OUTDATA_REVERSE_BIT + */ +__STATIC_INLINE uint32_t LL_CRC_GetOutputDataReverseMode(CRC_TypeDef *CRCx) +{ + return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_REV_OUT)); +} + +/** + * @brief Initialize the Programmable initial CRC value. + * @note If the CRC size is less than 32 bits, the least significant bits + * are used to write the correct value + * @note LL_CRC_DEFAULT_CRC_INITVALUE could be used as value for InitCrc parameter. + * @rmtoll INIT INIT LL_CRC_SetInitialData + * @param CRCx CRC Instance + * @param InitCrc Value to be programmed in Programmable initial CRC value register + * @retval None + */ +__STATIC_INLINE void LL_CRC_SetInitialData(CRC_TypeDef *CRCx, uint32_t InitCrc) +{ + WRITE_REG(CRCx->INIT, InitCrc); +} + +/** + * @brief Return current Initial CRC value. + * @note If the CRC size is less than 32 bits, the least significant bits + * are used to read the correct value + * @rmtoll INIT INIT LL_CRC_GetInitialData + * @param CRCx CRC Instance + * @retval Value programmed in Programmable initial CRC value register + */ +__STATIC_INLINE uint32_t LL_CRC_GetInitialData(CRC_TypeDef *CRCx) +{ + return (uint32_t)(READ_REG(CRCx->INIT)); +} + +/** + * @brief Initialize the Programmable polynomial value + * (coefficients of the polynomial to be used for CRC calculation). + * @note LL_CRC_DEFAULT_CRC32_POLY could be used as value for PolynomCoef parameter. + * @note Please check Reference Manual and existing Errata Sheets, + * regarding possible limitations for Polynomial values usage. + * For example, for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65 + * @rmtoll POL POL LL_CRC_SetPolynomialCoef + * @param CRCx CRC Instance + * @param PolynomCoef Value to be programmed in Programmable Polynomial value register + * @retval None + */ +__STATIC_INLINE void LL_CRC_SetPolynomialCoef(CRC_TypeDef *CRCx, uint32_t PolynomCoef) +{ + WRITE_REG(CRCx->POL, PolynomCoef); +} + +/** + * @brief Return current Programmable polynomial value + * @note Please check Reference Manual and existing Errata Sheets, + * regarding possible limitations for Polynomial values usage. + * For example, for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65 + * @rmtoll POL POL LL_CRC_GetPolynomialCoef + * @param CRCx CRC Instance + * @retval Value programmed in Programmable Polynomial value register + */ +__STATIC_INLINE uint32_t LL_CRC_GetPolynomialCoef(CRC_TypeDef *CRCx) +{ + return (uint32_t)(READ_REG(CRCx->POL)); +} + +/** + * @} + */ + +/** @defgroup CRC_LL_EF_Data_Management Data_Management + * @{ + */ + +/** + * @brief Write given 32-bit data to the CRC calculator + * @rmtoll DR DR LL_CRC_FeedData32 + * @param CRCx CRC Instance + * @param InData value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_CRC_FeedData32(CRC_TypeDef *CRCx, uint32_t InData) +{ + WRITE_REG(CRCx->DR, InData); +} + +/** + * @brief Write given 16-bit data to the CRC calculator + * @rmtoll DR DR LL_CRC_FeedData16 + * @param CRCx CRC Instance + * @param InData 16 bit value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFF + * @retval None + */ +__STATIC_INLINE void LL_CRC_FeedData16(CRC_TypeDef *CRCx, uint16_t InData) +{ + __IO uint16_t *pReg; + + pReg = (__IO uint16_t *)(__IO void *)(&CRCx->DR); /* Derogation MisraC2012 R.11.5 */ + *pReg = InData; +} + +/** + * @brief Write given 8-bit data to the CRC calculator + * @rmtoll DR DR LL_CRC_FeedData8 + * @param CRCx CRC Instance + * @param InData 8 bit value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_CRC_FeedData8(CRC_TypeDef *CRCx, uint8_t InData) +{ + *(uint8_t __IO *)(&CRCx->DR) = (uint8_t) InData; +} + +/** + * @brief Return current CRC calculation result. 32 bits value is returned. + * @rmtoll DR DR LL_CRC_ReadData32 + * @param CRCx CRC Instance + * @retval Current CRC calculation result as stored in CRC_DR register (32 bits). + */ +__STATIC_INLINE uint32_t LL_CRC_ReadData32(CRC_TypeDef *CRCx) +{ + return (uint32_t)(READ_REG(CRCx->DR)); +} + +/** + * @brief Return current CRC calculation result. 16 bits value is returned. + * @note This function is expected to be used in a 16 bits CRC polynomial size context. + * @rmtoll DR DR LL_CRC_ReadData16 + * @param CRCx CRC Instance + * @retval Current CRC calculation result as stored in CRC_DR register (16 bits). + */ +__STATIC_INLINE uint16_t LL_CRC_ReadData16(CRC_TypeDef *CRCx) +{ + return (uint16_t)READ_REG(CRCx->DR); +} + +/** + * @brief Return current CRC calculation result. 8 bits value is returned. + * @note This function is expected to be used in a 8 bits CRC polynomial size context. + * @rmtoll DR DR LL_CRC_ReadData8 + * @param CRCx CRC Instance + * @retval Current CRC calculation result as stored in CRC_DR register (8 bits). + */ +__STATIC_INLINE uint8_t LL_CRC_ReadData8(CRC_TypeDef *CRCx) +{ + return (uint8_t)READ_REG(CRCx->DR); +} + +/** + * @brief Return current CRC calculation result. 7 bits value is returned. + * @note This function is expected to be used in a 7 bits CRC polynomial size context. + * @rmtoll DR DR LL_CRC_ReadData7 + * @param CRCx CRC Instance + * @retval Current CRC calculation result as stored in CRC_DR register (7 bits). + */ +__STATIC_INLINE uint8_t LL_CRC_ReadData7(CRC_TypeDef *CRCx) +{ + return (uint8_t)(READ_REG(CRCx->DR) & 0x7FU); +} + +/** + * @brief Return data stored in the Independent Data(IDR) register. + * @note This register can be used as a temporary storage location. + * @note Refer to the Reference Manual to get the authorized data length in bits. + * @rmtoll IDR IDR LL_CRC_Read_IDR + * @param CRCx CRC Instance + * @retval Value stored in CRC_IDR register + */ +__STATIC_INLINE uint32_t LL_CRC_Read_IDR(CRC_TypeDef *CRCx) +{ + return (uint32_t)(READ_REG(CRCx->IDR)); +} + +/** + * @brief Store data in the Independent Data(IDR) register. + * @note This register can be used as a temporary storage location. + * @note Refer to the Reference Manual to get the authorized data length in bits. + * @rmtoll IDR IDR LL_CRC_Write_IDR + * @param CRCx CRC Instance + * @param InData value to be stored in CRC_IDR register + * @retval None + */ +__STATIC_INLINE void LL_CRC_Write_IDR(CRC_TypeDef *CRCx, uint32_t InData) +{ +#if (CRC_IDR_IDR == 0x0FFU) + *((uint8_t __IO *)(&CRCx->IDR)) = (uint8_t) InData; +#else + WRITE_REG(CRCx->IDR, InData); +#endif +} +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup CRC_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(CRC) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32L4xx_LL_CRC_H */ diff --git a/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_crs.h b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_crs.h new file mode 100644 index 0000000..1d2b333 --- /dev/null +++ b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_crs.h @@ -0,0 +1,785 @@ +/** + ****************************************************************************** + * @file stm32l4xx_ll_crs.h + * @author MCD Application Team + * @brief Header file of CRS LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32L4xx_LL_CRS_H +#define STM32L4xx_LL_CRS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx.h" + +/** @addtogroup STM32L4xx_LL_Driver + * @{ + */ + +#if defined(CRS) + +/** @defgroup CRS_LL CRS + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup CRS_LL_Exported_Constants CRS Exported Constants + * @{ + */ + +/** @defgroup CRS_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_CRS_ReadReg function + * @{ + */ +#define LL_CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF +#define LL_CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF +#define LL_CRS_ISR_ERRF CRS_ISR_ERRF +#define LL_CRS_ISR_ESYNCF CRS_ISR_ESYNCF +#define LL_CRS_ISR_SYNCERR CRS_ISR_SYNCERR +#define LL_CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS +#define LL_CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF +/** + * @} + */ + +/** @defgroup CRS_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_CRS_ReadReg and LL_CRS_WriteReg functions + * @{ + */ +#define LL_CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE +#define LL_CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE +#define LL_CRS_CR_ERRIE CRS_CR_ERRIE +#define LL_CRS_CR_ESYNCIE CRS_CR_ESYNCIE +/** + * @} + */ + +/** @defgroup CRS_LL_EC_SYNC_DIV Synchronization Signal Divider + * @{ + */ +#define LL_CRS_SYNC_DIV_1 ((uint32_t)0x00U) /*!< Synchro Signal not divided (default) */ +#define LL_CRS_SYNC_DIV_2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */ +#define LL_CRS_SYNC_DIV_4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */ +#define LL_CRS_SYNC_DIV_8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */ +#define LL_CRS_SYNC_DIV_16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */ +#define LL_CRS_SYNC_DIV_32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */ +#define LL_CRS_SYNC_DIV_64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */ +#define LL_CRS_SYNC_DIV_128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */ +/** + * @} + */ + +/** @defgroup CRS_LL_EC_SYNC_SOURCE Synchronization Signal Source + * @{ + */ +#define LL_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00U) /*!< Synchro Signal source GPIO */ +#define LL_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ +#define LL_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/ +/** + * @} + */ + +/** @defgroup CRS_LL_EC_SYNC_POLARITY Synchronization Signal Polarity + * @{ + */ +#define LL_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00U) /*!< Synchro Active on rising edge (default) */ +#define LL_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ +/** + * @} + */ + +/** @defgroup CRS_LL_EC_FREQERRORDIR Frequency Error Direction + * @{ + */ +#define LL_CRS_FREQ_ERROR_DIR_UP ((uint32_t)0x00U) /*!< Upcounting direction, the actual frequency is above the target */ +#define LL_CRS_FREQ_ERROR_DIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */ +/** + * @} + */ + +/** @defgroup CRS_LL_EC_DEFAULTVALUES Default Values + * @{ + */ +/** + * @brief Reset value of the RELOAD field + * @note The reset value of the RELOAD field corresponds to a target frequency of 48 MHz + * and a synchronization signal frequency of 1 kHz (SOF signal from USB) + */ +#define LL_CRS_RELOADVALUE_DEFAULT ((uint32_t)0xBB7FU) + +/** + * @brief Reset value of Frequency error limit. + */ +#define LL_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x22U) + +/** + * @brief Reset value of the HSI48 Calibration field + * @note The default value is 64 for STM32L412xx/L422xx, 32 otherwise, which corresponds + * to the middle of the trimming interval. + * The trimming step is around 67 kHz between two consecutive TRIM steps. + * A higher TRIM value corresponds to a higher output frequency + */ +#if defined (STM32L412xx) || defined (STM32L422xx) +#define LL_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)64U) +#else +#define LL_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)32U) +#endif +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup CRS_LL_Exported_Macros CRS Exported Macros + * @{ + */ + +/** @defgroup CRS_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in CRS register + * @param __INSTANCE__ CRS Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_CRS_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in CRS register + * @param __INSTANCE__ CRS Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_CRS_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup CRS_LL_EM_Exported_Macros_Calculate_Reload Exported_Macros_Calculate_Reload + * @{ + */ + +/** + * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies + * @note The RELOAD value should be selected according to the ratio between + * the target frequency and the frequency of the synchronization source after + * prescaling. It is then decreased by one in order to reach the expected + * synchronization on the zero value. The formula is the following: + * RELOAD = (fTARGET / fSYNC) -1 + * @param __FTARGET__ Target frequency (value in Hz) + * @param __FSYNC__ Synchronization signal frequency (value in Hz) + * @retval Reload value (in Hz) + */ +#define __LL_CRS_CALC_CALCULATE_RELOADVALUE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup CRS_LL_Exported_Functions CRS Exported Functions + * @{ + */ + +/** @defgroup CRS_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Enable Frequency error counter + * @note When this bit is set, the CRS_CFGR register is write-protected and cannot be modified + * @rmtoll CR CEN LL_CRS_EnableFreqErrorCounter + * @retval None + */ +__STATIC_INLINE void LL_CRS_EnableFreqErrorCounter(void) +{ + SET_BIT(CRS->CR, CRS_CR_CEN); +} + +/** + * @brief Disable Frequency error counter + * @rmtoll CR CEN LL_CRS_DisableFreqErrorCounter + * @retval None + */ +__STATIC_INLINE void LL_CRS_DisableFreqErrorCounter(void) +{ + CLEAR_BIT(CRS->CR, CRS_CR_CEN); +} + +/** + * @brief Check if Frequency error counter is enabled or not + * @rmtoll CR CEN LL_CRS_IsEnabledFreqErrorCounter + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsEnabledFreqErrorCounter(void) +{ + return (READ_BIT(CRS->CR, CRS_CR_CEN) == (CRS_CR_CEN)); +} + +/** + * @brief Enable Automatic trimming counter + * @rmtoll CR AUTOTRIMEN LL_CRS_EnableAutoTrimming + * @retval None + */ +__STATIC_INLINE void LL_CRS_EnableAutoTrimming(void) +{ + SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN); +} + +/** + * @brief Disable Automatic trimming counter + * @rmtoll CR AUTOTRIMEN LL_CRS_DisableAutoTrimming + * @retval None + */ +__STATIC_INLINE void LL_CRS_DisableAutoTrimming(void) +{ + CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN); +} + +/** + * @brief Check if Automatic trimming is enabled or not + * @rmtoll CR AUTOTRIMEN LL_CRS_IsEnabledAutoTrimming + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsEnabledAutoTrimming(void) +{ + return (READ_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) == (CRS_CR_AUTOTRIMEN)); +} + +/** + * @brief Set HSI48 oscillator smooth trimming + * @note When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only + * @rmtoll CR TRIM LL_CRS_SetHSI48SmoothTrimming + * @param Value a number between Min_Data = 0 and Max_Data = 127 for STM32L412xx/L422xx or 63 otherwise + * @note Default value can be set thanks to @ref LL_CRS_HSI48CALIBRATION_DEFAULT + * @retval None + */ +__STATIC_INLINE void LL_CRS_SetHSI48SmoothTrimming(uint32_t Value) +{ + MODIFY_REG(CRS->CR, CRS_CR_TRIM, Value << CRS_CR_TRIM_Pos); +} + +/** + * @brief Get HSI48 oscillator smooth trimming + * @rmtoll CR TRIM LL_CRS_GetHSI48SmoothTrimming + * @retval a number between Min_Data = 0 and Max_Data = 127 for STM32L412xx/L422xx or 63 otherwise + */ +__STATIC_INLINE uint32_t LL_CRS_GetHSI48SmoothTrimming(void) +{ + return (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos); +} + +/** + * @brief Set counter reload value + * @rmtoll CFGR RELOAD LL_CRS_SetReloadCounter + * @param Value a number between Min_Data = 0 and Max_Data = 0xFFFF + * @note Default value can be set thanks to @ref LL_CRS_RELOADVALUE_DEFAULT + * Otherwise it can be calculated in using macro @ref __LL_CRS_CALC_CALCULATE_RELOADVALUE (_FTARGET_, _FSYNC_) + * @retval None + */ +__STATIC_INLINE void LL_CRS_SetReloadCounter(uint32_t Value) +{ + MODIFY_REG(CRS->CFGR, CRS_CFGR_RELOAD, Value); +} + +/** + * @brief Get counter reload value + * @rmtoll CFGR RELOAD LL_CRS_GetReloadCounter + * @retval a number between Min_Data = 0 and Max_Data = 0xFFFF + */ +__STATIC_INLINE uint32_t LL_CRS_GetReloadCounter(void) +{ + return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD)); +} + +/** + * @brief Set frequency error limit + * @rmtoll CFGR FELIM LL_CRS_SetFreqErrorLimit + * @param Value a number between Min_Data = 0 and Max_Data = 255 + * @note Default value can be set thanks to @ref LL_CRS_ERRORLIMIT_DEFAULT + * @retval None + */ +__STATIC_INLINE void LL_CRS_SetFreqErrorLimit(uint32_t Value) +{ + MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_CFGR_FELIM_Pos); +} + +/** + * @brief Get frequency error limit + * @rmtoll CFGR FELIM LL_CRS_GetFreqErrorLimit + * @retval A number between Min_Data = 0 and Max_Data = 255 + */ +__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorLimit(void) +{ + return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_FELIM) >> CRS_CFGR_FELIM_Pos); +} + +/** + * @brief Set division factor for SYNC signal + * @rmtoll CFGR SYNCDIV LL_CRS_SetSyncDivider + * @param Divider This parameter can be one of the following values: + * @arg @ref LL_CRS_SYNC_DIV_1 + * @arg @ref LL_CRS_SYNC_DIV_2 + * @arg @ref LL_CRS_SYNC_DIV_4 + * @arg @ref LL_CRS_SYNC_DIV_8 + * @arg @ref LL_CRS_SYNC_DIV_16 + * @arg @ref LL_CRS_SYNC_DIV_32 + * @arg @ref LL_CRS_SYNC_DIV_64 + * @arg @ref LL_CRS_SYNC_DIV_128 + * @retval None + */ +__STATIC_INLINE void LL_CRS_SetSyncDivider(uint32_t Divider) +{ + MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCDIV, Divider); +} + +/** + * @brief Get division factor for SYNC signal + * @rmtoll CFGR SYNCDIV LL_CRS_GetSyncDivider + * @retval Returned value can be one of the following values: + * @arg @ref LL_CRS_SYNC_DIV_1 + * @arg @ref LL_CRS_SYNC_DIV_2 + * @arg @ref LL_CRS_SYNC_DIV_4 + * @arg @ref LL_CRS_SYNC_DIV_8 + * @arg @ref LL_CRS_SYNC_DIV_16 + * @arg @ref LL_CRS_SYNC_DIV_32 + * @arg @ref LL_CRS_SYNC_DIV_64 + * @arg @ref LL_CRS_SYNC_DIV_128 + */ +__STATIC_INLINE uint32_t LL_CRS_GetSyncDivider(void) +{ + return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCDIV)); +} + +/** + * @brief Set SYNC signal source + * @rmtoll CFGR SYNCSRC LL_CRS_SetSyncSignalSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_CRS_SYNC_SOURCE_GPIO + * @arg @ref LL_CRS_SYNC_SOURCE_LSE + * @arg @ref LL_CRS_SYNC_SOURCE_USB + * @retval None + */ +__STATIC_INLINE void LL_CRS_SetSyncSignalSource(uint32_t Source) +{ + MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCSRC, Source); +} + +/** + * @brief Get SYNC signal source + * @rmtoll CFGR SYNCSRC LL_CRS_GetSyncSignalSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_CRS_SYNC_SOURCE_GPIO + * @arg @ref LL_CRS_SYNC_SOURCE_LSE + * @arg @ref LL_CRS_SYNC_SOURCE_USB + */ +__STATIC_INLINE uint32_t LL_CRS_GetSyncSignalSource(void) +{ + return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCSRC)); +} + +/** + * @brief Set input polarity for the SYNC signal source + * @rmtoll CFGR SYNCPOL LL_CRS_SetSyncPolarity + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_CRS_SYNC_POLARITY_RISING + * @arg @ref LL_CRS_SYNC_POLARITY_FALLING + * @retval None + */ +__STATIC_INLINE void LL_CRS_SetSyncPolarity(uint32_t Polarity) +{ + MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCPOL, Polarity); +} + +/** + * @brief Get input polarity for the SYNC signal source + * @rmtoll CFGR SYNCPOL LL_CRS_GetSyncPolarity + * @retval Returned value can be one of the following values: + * @arg @ref LL_CRS_SYNC_POLARITY_RISING + * @arg @ref LL_CRS_SYNC_POLARITY_FALLING + */ +__STATIC_INLINE uint32_t LL_CRS_GetSyncPolarity(void) +{ + return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCPOL)); +} + +/** + * @brief Configure CRS for the synchronization + * @rmtoll CR TRIM LL_CRS_ConfigSynchronization\n + * CFGR RELOAD LL_CRS_ConfigSynchronization\n + * CFGR FELIM LL_CRS_ConfigSynchronization\n + * CFGR SYNCDIV LL_CRS_ConfigSynchronization\n + * CFGR SYNCSRC LL_CRS_ConfigSynchronization\n + * CFGR SYNCPOL LL_CRS_ConfigSynchronization + * @param HSI48CalibrationValue a number between Min_Data = 0 and Max_Data = 127 for STM32L412xx/L422xx or 63 otherwise + * @param ErrorLimitValue a number between Min_Data = 0 and Max_Data = 0xFFFF + * @param ReloadValue a number between Min_Data = 0 and Max_Data = 255 + * @param Settings This parameter can be a combination of the following values: + * @arg @ref LL_CRS_SYNC_DIV_1 or @ref LL_CRS_SYNC_DIV_2 or @ref LL_CRS_SYNC_DIV_4 or @ref LL_CRS_SYNC_DIV_8 + * or @ref LL_CRS_SYNC_DIV_16 or @ref LL_CRS_SYNC_DIV_32 or @ref LL_CRS_SYNC_DIV_64 or @ref LL_CRS_SYNC_DIV_128 + * @arg @ref LL_CRS_SYNC_SOURCE_GPIO or @ref LL_CRS_SYNC_SOURCE_LSE or @ref LL_CRS_SYNC_SOURCE_USB + * @arg @ref LL_CRS_SYNC_POLARITY_RISING or @ref LL_CRS_SYNC_POLARITY_FALLING + * @retval None + */ +__STATIC_INLINE void LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue, uint32_t ReloadValue, uint32_t Settings) +{ + MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue); + MODIFY_REG(CRS->CFGR, + CRS_CFGR_RELOAD | CRS_CFGR_FELIM | CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL, + ReloadValue | (ErrorLimitValue << CRS_CFGR_FELIM_Pos) | Settings); +} + +/** + * @} + */ + +/** @defgroup CRS_LL_EF_CRS_Management CRS_Management + * @{ + */ + +/** + * @brief Generate software SYNC event + * @rmtoll CR SWSYNC LL_CRS_GenerateEvent_SWSYNC + * @retval None + */ +__STATIC_INLINE void LL_CRS_GenerateEvent_SWSYNC(void) +{ + SET_BIT(CRS->CR, CRS_CR_SWSYNC); +} + +/** + * @brief Get the frequency error direction latched in the time of the last + * SYNC event + * @rmtoll ISR FEDIR LL_CRS_GetFreqErrorDirection + * @retval Returned value can be one of the following values: + * @arg @ref LL_CRS_FREQ_ERROR_DIR_UP + * @arg @ref LL_CRS_FREQ_ERROR_DIR_DOWN + */ +__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorDirection(void) +{ + return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR)); +} + +/** + * @brief Get the frequency error counter value latched in the time of the last SYNC event + * @rmtoll ISR FECAP LL_CRS_GetFreqErrorCapture + * @retval A number between Min_Data = 0x0000 and Max_Data = 0xFFFF + */ +__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorCapture(void) +{ + return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos); +} + +/** + * @} + */ + +/** @defgroup CRS_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Check if SYNC event OK signal occurred or not + * @rmtoll ISR SYNCOKF LL_CRS_IsActiveFlag_SYNCOK + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCOK(void) +{ + return (READ_BIT(CRS->ISR, CRS_ISR_SYNCOKF) == (CRS_ISR_SYNCOKF)); +} + +/** + * @brief Check if SYNC warning signal occurred or not + * @rmtoll ISR SYNCWARNF LL_CRS_IsActiveFlag_SYNCWARN + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCWARN(void) +{ + return (READ_BIT(CRS->ISR, CRS_ISR_SYNCWARNF) == (CRS_ISR_SYNCWARNF)); +} + +/** + * @brief Check if Synchronization or trimming error signal occurred or not + * @rmtoll ISR ERRF LL_CRS_IsActiveFlag_ERR + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ERR(void) +{ + return (READ_BIT(CRS->ISR, CRS_ISR_ERRF) == (CRS_ISR_ERRF)); +} + +/** + * @brief Check if Expected SYNC signal occurred or not + * @rmtoll ISR ESYNCF LL_CRS_IsActiveFlag_ESYNC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ESYNC(void) +{ + return (READ_BIT(CRS->ISR, CRS_ISR_ESYNCF) == (CRS_ISR_ESYNCF)); +} + +/** + * @brief Check if SYNC error signal occurred or not + * @rmtoll ISR SYNCERR LL_CRS_IsActiveFlag_SYNCERR + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCERR(void) +{ + return (READ_BIT(CRS->ISR, CRS_ISR_SYNCERR) == (CRS_ISR_SYNCERR)); +} + +/** + * @brief Check if SYNC missed error signal occurred or not + * @rmtoll ISR SYNCMISS LL_CRS_IsActiveFlag_SYNCMISS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCMISS(void) +{ + return (READ_BIT(CRS->ISR, CRS_ISR_SYNCMISS) == (CRS_ISR_SYNCMISS)); +} + +/** + * @brief Check if Trimming overflow or underflow occurred or not + * @rmtoll ISR TRIMOVF LL_CRS_IsActiveFlag_TRIMOVF + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_TRIMOVF(void) +{ + return (READ_BIT(CRS->ISR, CRS_ISR_TRIMOVF) == (CRS_ISR_TRIMOVF)); +} + +/** + * @brief Clear the SYNC event OK flag + * @rmtoll ICR SYNCOKC LL_CRS_ClearFlag_SYNCOK + * @retval None + */ +__STATIC_INLINE void LL_CRS_ClearFlag_SYNCOK(void) +{ + WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC); +} + +/** + * @brief Clear the SYNC warning flag + * @rmtoll ICR SYNCWARNC LL_CRS_ClearFlag_SYNCWARN + * @retval None + */ +__STATIC_INLINE void LL_CRS_ClearFlag_SYNCWARN(void) +{ + WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC); +} + +/** + * @brief Clear TRIMOVF, SYNCMISS and SYNCERR bits and consequently also + * the ERR flag + * @rmtoll ICR ERRC LL_CRS_ClearFlag_ERR + * @retval None + */ +__STATIC_INLINE void LL_CRS_ClearFlag_ERR(void) +{ + WRITE_REG(CRS->ICR, CRS_ICR_ERRC); +} + +/** + * @brief Clear Expected SYNC flag + * @rmtoll ICR ESYNCC LL_CRS_ClearFlag_ESYNC + * @retval None + */ +__STATIC_INLINE void LL_CRS_ClearFlag_ESYNC(void) +{ + WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC); +} + +/** + * @} + */ + +/** @defgroup CRS_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable SYNC event OK interrupt + * @rmtoll CR SYNCOKIE LL_CRS_EnableIT_SYNCOK + * @retval None + */ +__STATIC_INLINE void LL_CRS_EnableIT_SYNCOK(void) +{ + SET_BIT(CRS->CR, CRS_CR_SYNCOKIE); +} + +/** + * @brief Disable SYNC event OK interrupt + * @rmtoll CR SYNCOKIE LL_CRS_DisableIT_SYNCOK + * @retval None + */ +__STATIC_INLINE void LL_CRS_DisableIT_SYNCOK(void) +{ + CLEAR_BIT(CRS->CR, CRS_CR_SYNCOKIE); +} + +/** + * @brief Check if SYNC event OK interrupt is enabled or not + * @rmtoll CR SYNCOKIE LL_CRS_IsEnabledIT_SYNCOK + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCOK(void) +{ + return (READ_BIT(CRS->CR, CRS_CR_SYNCOKIE) == (CRS_CR_SYNCOKIE)); +} + +/** + * @brief Enable SYNC warning interrupt + * @rmtoll CR SYNCWARNIE LL_CRS_EnableIT_SYNCWARN + * @retval None + */ +__STATIC_INLINE void LL_CRS_EnableIT_SYNCWARN(void) +{ + SET_BIT(CRS->CR, CRS_CR_SYNCWARNIE); +} + +/** + * @brief Disable SYNC warning interrupt + * @rmtoll CR SYNCWARNIE LL_CRS_DisableIT_SYNCWARN + * @retval None + */ +__STATIC_INLINE void LL_CRS_DisableIT_SYNCWARN(void) +{ + CLEAR_BIT(CRS->CR, CRS_CR_SYNCWARNIE); +} + +/** + * @brief Check if SYNC warning interrupt is enabled or not + * @rmtoll CR SYNCWARNIE LL_CRS_IsEnabledIT_SYNCWARN + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCWARN(void) +{ + return (READ_BIT(CRS->CR, CRS_CR_SYNCWARNIE) == (CRS_CR_SYNCWARNIE)); +} + +/** + * @brief Enable Synchronization or trimming error interrupt + * @rmtoll CR ERRIE LL_CRS_EnableIT_ERR + * @retval None + */ +__STATIC_INLINE void LL_CRS_EnableIT_ERR(void) +{ + SET_BIT(CRS->CR, CRS_CR_ERRIE); +} + +/** + * @brief Disable Synchronization or trimming error interrupt + * @rmtoll CR ERRIE LL_CRS_DisableIT_ERR + * @retval None + */ +__STATIC_INLINE void LL_CRS_DisableIT_ERR(void) +{ + CLEAR_BIT(CRS->CR, CRS_CR_ERRIE); +} + +/** + * @brief Check if Synchronization or trimming error interrupt is enabled or not + * @rmtoll CR ERRIE LL_CRS_IsEnabledIT_ERR + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ERR(void) +{ + return (READ_BIT(CRS->CR, CRS_CR_ERRIE) == (CRS_CR_ERRIE)); +} + +/** + * @brief Enable Expected SYNC interrupt + * @rmtoll CR ESYNCIE LL_CRS_EnableIT_ESYNC + * @retval None + */ +__STATIC_INLINE void LL_CRS_EnableIT_ESYNC(void) +{ + SET_BIT(CRS->CR, CRS_CR_ESYNCIE); +} + +/** + * @brief Disable Expected SYNC interrupt + * @rmtoll CR ESYNCIE LL_CRS_DisableIT_ESYNC + * @retval None + */ +__STATIC_INLINE void LL_CRS_DisableIT_ESYNC(void) +{ + CLEAR_BIT(CRS->CR, CRS_CR_ESYNCIE); +} + +/** + * @brief Check if Expected SYNC interrupt is enabled or not + * @rmtoll CR ESYNCIE LL_CRS_IsEnabledIT_ESYNC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ESYNC(void) +{ + return (READ_BIT(CRS->CR, CRS_CR_ESYNCIE) == (CRS_CR_ESYNCIE)); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup CRS_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_CRS_DeInit(void); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(CRS) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32L4xx_LL_CRS_H */ diff --git a/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_dac.h b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_dac.h new file mode 100644 index 0000000..565e142 --- /dev/null +++ b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_dac.h @@ -0,0 +1,1979 @@ +/** + ****************************************************************************** + * @file stm32l4xx_ll_dac.h + * @author MCD Application Team + * @brief Header file of DAC LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32L4xx_LL_DAC_H +#define STM32L4xx_LL_DAC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx.h" + +/** @addtogroup STM32L4xx_LL_Driver + * @{ + */ + +#if defined (DAC1) + +/** @defgroup DAC_LL DAC + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup DAC_LL_Private_Constants DAC Private Constants + * @{ + */ + +/* Internal masks for DAC channels definition */ +/* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */ +/* - channel bits position into registers CR, MCR, CCR, SHHR, SHRR */ +/* - channel bits position into register SWTRIG */ +/* - channel register offset of data holding register DHRx */ +/* - channel register offset of data output register DORx */ +/* - channel register offset of sample-and-hold sample time register SHSRx */ +#define DAC_CR_CH1_BITOFFSET 0U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */ +#define DAC_CR_CH2_BITOFFSET 16U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */ +#define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET) + +#define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. */ +#if defined(DAC_CHANNEL2_SUPPORT) +#define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. */ +#define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2) +#else +#define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1) +#endif /* DAC_CHANNEL2_SUPPORT */ + +#define DAC_REG_DHR12R1_REGOFFSET 0x00000000U /* Register DHR12Rx channel 1 taken as reference */ +#define DAC_REG_DHR12L1_REGOFFSET 0x00100000U /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */ +#define DAC_REG_DHR8R1_REGOFFSET 0x02000000U /* Register offset of DHR8Rx channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */ +#if defined(DAC_CHANNEL2_SUPPORT) +#define DAC_REG_DHR12R2_REGOFFSET 0x30000000U /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 28 bits) */ +#define DAC_REG_DHR12L2_REGOFFSET 0x00400000U /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */ +#define DAC_REG_DHR8R2_REGOFFSET 0x05000000U /* Register offset of DHR8Rx channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */ +#endif /* DAC_CHANNEL2_SUPPORT */ +#define DAC_REG_DHR12RX_REGOFFSET_MASK 0xF0000000U +#define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000U +#define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000U +#define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK) + +#define DAC_REG_DOR1_REGOFFSET 0x00000000U /* Register DORx channel 1 taken as reference */ +#if defined(DAC_CHANNEL2_SUPPORT) +#define DAC_REG_DOR2_REGOFFSET 0x00000020U /* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 5 bits) */ +#define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET) +#else +#define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET) +#endif /* DAC_CHANNEL2_SUPPORT */ + +#define DAC_REG_SHSR1_REGOFFSET 0x00000000U /* Register SHSRx channel 1 taken as reference */ +#if defined(DAC_CHANNEL2_SUPPORT) +#define DAC_REG_SHSR2_REGOFFSET 0x00000040U /* Register offset of SHSRx channel 1 versus SHSRx channel 2 (shifted left of 6 bits) */ +#define DAC_REG_SHSRX_REGOFFSET_MASK (DAC_REG_SHSR1_REGOFFSET | DAC_REG_SHSR2_REGOFFSET) +#else +#define DAC_REG_SHSRX_REGOFFSET_MASK (DAC_REG_SHSR1_REGOFFSET) +#endif /* DAC_CHANNEL2_SUPPORT */ + +#define DAC_REG_DHR_REGOFFSET_MASK_POSBIT0 0x0000000FU /* Mask of data hold registers offset (DHR12Rx, DHR12Lx, DHR8Rx, ...) when shifted to position 0 */ +#define DAC_REG_DORX_REGOFFSET_MASK_POSBIT0 0x00000001U /* Mask of DORx registers offset when shifted to position 0 */ +#define DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0 0x00000001U /* Mask of SHSRx registers offset when shifted to position 0 */ + +#define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS 28U /* Position of bits register offset of DHR12Rx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 28 bits) */ +#define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS 20U /* Position of bits register offset of DHR12Lx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */ +#define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS 24U /* Position of bits register offset of DHR8Rx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */ +#define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS 5U /* Position of bits register offset of DORx channel 1 or 2 versus DORx channel 1 (shifted left of 5 bits) */ +#define DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS 6U /* Position of bits register offset of SHSRx channel 1 or 2 versus SHSRx channel 1 (shifted left of 6 bits) */ + +/* DAC registers bits positions */ +#if defined(DAC_CHANNEL2_SUPPORT) +#define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS DAC_DHR12RD_DACC2DHR_Pos +#define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS DAC_DHR12LD_DACC2DHR_Pos +#define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS DAC_DHR8RD_DACC2DHR_Pos +#endif /* DAC_CHANNEL2_SUPPORT */ + +/* Miscellaneous data */ +#define DAC_DIGITAL_SCALE_12BITS 4095U /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */ + +/** + * @} + */ + + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup DAC_LL_Private_Macros DAC Private Macros + * @{ + */ + +/** + * @brief Driver macro reserved for internal use: set a pointer to + * a register from a register basis from which an offset + * is applied. + * @param __REG__ Register basis from which the offset is applied. + * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers). + * @retval Pointer to register address +*/ +#define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \ + ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U)))) + +/** + * @} + */ + + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup DAC_LL_ES_INIT DAC Exported Init structure + * @{ + */ + +/** + * @brief Structure definition of some features of DAC instance. + */ +typedef struct +{ + uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel: internal (SW start) or from external peripheral (timer event, external interrupt line). + This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE + + This feature can be modified afterwards using unitary function @ref LL_DAC_SetTriggerSource(). */ + + uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel. + This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE + + This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveAutoGeneration(). */ + + uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel. + If waveform automatic generation mode is set to noise, this parameter can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS + If waveform automatic generation mode is set to triangle, this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE + @note If waveform automatic generation mode is disabled, this parameter is discarded. + + This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveNoiseLFSR(), @ref LL_DAC_SetWaveTriangleAmplitude() + depending on the wave automatic generation selected. */ + + uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel. + This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER + + This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputBuffer(). */ + + uint32_t OutputConnection; /*!< Set the output connection for the selected DAC channel. + This parameter can be a value of @ref DAC_LL_EC_OUTPUT_CONNECTION + + This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputConnection(). */ + + uint32_t OutputMode; /*!< Set the output mode normal or sample-and-hold for the selected DAC channel. + This parameter can be a value of @ref DAC_LL_EC_OUTPUT_MODE + + This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputMode(). */ +} LL_DAC_InitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup DAC_LL_Exported_Constants DAC Exported Constants + * @{ + */ + +/** @defgroup DAC_LL_EC_GET_FLAG DAC flags + * @brief Flags defines which can be used with LL_DAC_ReadReg function + * @{ + */ +/* DAC channel 1 flags */ +#define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) /*!< DAC channel 1 flag DMA underrun */ +#define LL_DAC_FLAG_CAL1 (DAC_SR_CAL_FLAG1) /*!< DAC channel 1 flag offset calibration status */ +#define LL_DAC_FLAG_BWST1 (DAC_SR_BWST1) /*!< DAC channel 1 flag busy writing sample time */ + +#if defined(DAC_CHANNEL2_SUPPORT) +/* DAC channel 2 flags */ +#define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /*!< DAC channel 2 flag DMA underrun */ +#define LL_DAC_FLAG_CAL2 (DAC_SR_CAL_FLAG2) /*!< DAC channel 2 flag offset calibration status */ +#define LL_DAC_FLAG_BWST2 (DAC_SR_BWST2) /*!< DAC channel 2 flag busy writing sample time */ +#endif /* DAC_CHANNEL2_SUPPORT */ +/** + * @} + */ + +/** @defgroup DAC_LL_EC_IT DAC interruptions + * @brief IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions + * @{ + */ +#define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */ +#if defined(DAC_CHANNEL2_SUPPORT) +#define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */ +#endif /* DAC_CHANNEL2_SUPPORT */ +/** + * @} + */ + +/** @defgroup DAC_LL_EC_CHANNEL DAC channels + * @{ + */ +#define LL_DAC_CHANNEL_1 (DAC_REG_SHSR1_REGOFFSET | DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1) /*!< DAC channel 1 */ +#if defined(DAC_CHANNEL2_SUPPORT) +#define LL_DAC_CHANNEL_2 (DAC_REG_SHSR2_REGOFFSET | DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2) /*!< DAC channel 2 */ +#endif /* DAC_CHANNEL2_SUPPORT */ +/** + * @} + */ +#if defined (DAC_CR_HFSEL) /* High frequency interface mode */ + +/** @defgroup DAC_LL_EC_HIGH_FREQUENCY_MODE DAC high frequency interface mode + * @brief High frequency interface mode defines that can be used with LL_DAC_SetHighFrequencyMode and LL_DAC_GetHighFrequencyMode + * @{ + */ +#define LL_DAC_HIGH_FREQ_MODE_DISABLE 0x00000000U /*!< High frequency interface mode disabled */ +#define LL_DAC_HIGH_FREQ_MODE_ABOVE_80MHZ (DAC_CR_HFSEL) /*!< High frequency interface mode compatible to AHB>80MHz enabled */ +/** + * @} + */ +#endif /* High frequency interface mode */ + +/** @defgroup DAC_LL_EC_OPERATING_MODE DAC operating mode + * @{ + */ +#define LL_DAC_MODE_NORMAL_OPERATION 0x00000000U /*!< DAC channel in mode normal operation */ +#define LL_DAC_MODE_CALIBRATION (DAC_CR_CEN1) /*!< DAC channel in mode calibration */ +/** + * @} + */ + +/** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source + * @{ + */ +#if defined (DAC_CR_TSEL1_3) +#define LL_DAC_TRIG_EXT_TIM1_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM1 TRGO. */ +#define LL_DAC_TRIG_EXT_TIM2_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */ +#define LL_DAC_TRIG_EXT_TIM4_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */ +#define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */ +#define LL_DAC_TRIG_EXT_TIM6_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */ +#define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */ +#define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM8 TRGO. */ +#define LL_DAC_TRIG_EXT_TIM15_TRGO (DAC_CR_TSEL1_3 ) /*!< DAC channel conversion trigger from external IP: TIM15 TRGO. */ +#define LL_DAC_TRIG_EXT_LPTIM1_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: LPTIM1 TRGO. */ +#define LL_DAC_TRIG_EXT_LPTIM2_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: LPTIM2 TRGO. */ +#define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */ +#define LL_DAC_TRIG_SOFTWARE 0x00000000U /*!< DAC channel conversion trigger internal (SW start) */ +#else +#define LL_DAC_TRIG_SOFTWARE (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger internal (SW start) */ +#define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */ +#define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */ +#define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */ +#define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */ +#define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */ +#define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM8 TRGO. */ +#define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */ +#endif + +/** + * @} + */ + +/** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode + * @{ + */ +#define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000U /*!< DAC channel wave auto generation mode disabled. */ +#define LL_DAC_WAVE_AUTO_GENERATION_NOISE ( DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */ +#define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1 ) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */ +/** + * @} + */ + +/** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits + * @{ + */ +#define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000U /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */ +#define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */ +#define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */ +#define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */ +#define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel */ +#define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel */ +#define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel */ +#define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel */ +#define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel */ +#define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel */ +#define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel */ +#define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel */ +/** + * @} + */ + +/** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude + * @{ + */ +#define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000U /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */ +#define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */ +#define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */ +#define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */ +#define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel */ +#define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel */ +#define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel */ +#define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel */ +#define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel */ +#define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel */ +#define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel */ +#define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel */ +/** + * @} + */ + +/** @defgroup DAC_LL_EC_OUTPUT_MODE DAC channel output mode + * @{ + */ +#define LL_DAC_OUTPUT_MODE_NORMAL 0x00000000U /*!< The selected DAC channel output is on mode normal. */ +#define LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD (DAC_MCR_MODE1_2) /*!< The selected DAC channel output is on mode sample-and-hold. Mode sample-and-hold requires an external capacitor, refer to description of function @ref LL_DAC_ConfigOutput() or @ref LL_DAC_SetOutputMode(). */ +/** + * @} + */ + +/** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer + * @{ + */ +#define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000U /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */ +#define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_MCR_MODE1_1) /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */ +/** + * @} + */ + +/** @defgroup DAC_LL_EC_OUTPUT_CONNECTION DAC channel output connection + * @{ + */ +#define LL_DAC_OUTPUT_CONNECT_GPIO 0x00000000U /*!< The selected DAC channel output is connected to external pin */ +#define LL_DAC_OUTPUT_CONNECT_INTERNAL (DAC_MCR_MODE1_0) /*!< The selected DAC channel output is connected to on-chip peripherals via internal paths. On this STM32 serie, output connection depends on output mode (normal or sample and hold) and output buffer state. Refer to comments of function @ref LL_DAC_SetOutputConnection(). */ +/** + * @} + */ + +/** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution + * @{ + */ +#define LL_DAC_RESOLUTION_12B 0x00000000U /*!< DAC channel resolution 12 bits */ +#define LL_DAC_RESOLUTION_8B 0x00000002U /*!< DAC channel resolution 8 bits */ +/** + * @} + */ + +/** @defgroup DAC_LL_EC_REGISTERS DAC registers compliant with specific purpose + * @{ + */ +/* List of DAC registers intended to be used (most commonly) with */ +/* DMA transfer. */ +/* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */ +#define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits right aligned */ +#define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits left aligned */ +#define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 8 bits right aligned */ +/** + * @} + */ + +/** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays + * @note Only DAC peripheral HW delays are defined in DAC LL driver driver, + * not timeout values. + * For details on delays values, refer to descriptions in source code + * above each literal definition. + * @{ + */ + +/* Delay for DAC channel voltage settling time from DAC channel startup */ +/* (transition from disable to enable). */ +/* Note: DAC channel startup time depends on board application environment: */ +/* impedance connected to DAC channel output. */ +/* The delay below is specified under conditions: */ +/* - voltage maximum transition (lowest to highest value) */ +/* - until voltage reaches final value +-1LSB */ +/* - DAC channel output buffer enabled */ +/* - load impedance of 5kOhm (min), 50pF (max) */ +/* Literal set to maximum value (refer to device datasheet, */ +/* parameter "tWAKEUP"). */ +/* Unit: us */ +#define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 8U /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */ + + +/* Delay for DAC channel voltage settling time. */ +/* Note: DAC channel startup time depends on board application environment: */ +/* impedance connected to DAC channel output. */ +/* The delay below is specified under conditions: */ +/* - voltage maximum transition (lowest to highest value) */ +/* - until voltage reaches final value +-1LSB */ +/* - DAC channel output buffer enabled */ +/* - load impedance of 5kOhm min, 50pF max */ +/* Literal set to maximum value (refer to device datasheet, */ +/* parameter "tSETTLING"). */ +/* Unit: us */ +#define LL_DAC_DELAY_VOLTAGE_SETTLING_US 3U /*!< Delay for DAC channel voltage settling time */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup DAC_LL_Exported_Macros DAC Exported Macros + * @{ + */ + +/** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros + * @{ + */ + +/** + * @brief Write a value in DAC register + * @param __INSTANCE__ DAC Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in DAC register + * @param __INSTANCE__ DAC Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) + +/** + * @} + */ + +/** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro + * @{ + */ + +/** + * @brief Helper macro to get DAC channel number in decimal format + * from literals LL_DAC_CHANNEL_x. + * Example: + * __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1) + * will return decimal number "1". + * @note The input can be a value from functions where a channel + * number is returned. + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 + * @retval 1...2 + */ +#define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ + ((__CHANNEL__) & DAC_SWTR_CHX_MASK) + +/** + * @brief Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x + * from number in decimal format. + * Example: + * __LL_DAC_DECIMAL_NB_TO_CHANNEL(1) + * will return a data equivalent to "LL_DAC_CHANNEL_1". + * @note If the input parameter does not correspond to a DAC channel, + * this macro returns value '0'. + * @param __DECIMAL_NB__ 1...2 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 + */ +#if defined(DAC_CHANNEL2_SUPPORT) +#define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ + (((__DECIMAL_NB__) == 1U) \ + ? ( \ + LL_DAC_CHANNEL_1 \ + ) \ + : \ + (((__DECIMAL_NB__) == 2U) \ + ? ( \ + LL_DAC_CHANNEL_2 \ + ) \ + : \ + ( \ + 0U \ + ) \ + ) \ + ) +#else +#define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ + (((__DECIMAL_NB__) == 1U) \ + ? ( \ + LL_DAC_CHANNEL_1 \ + ) \ + : \ + ( \ + 0U \ + ) \ + ) +#endif /* DAC_CHANNEL2_SUPPORT */ + +/** + * @brief Helper macro to define the DAC conversion data full-scale digital + * value corresponding to the selected DAC resolution. + * @note DAC conversion data full-scale corresponds to voltage range + * determined by analog voltage references Vref+ and Vref- + * (refer to reference manual). + * @param __DAC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref LL_DAC_RESOLUTION_12B + * @arg @ref LL_DAC_RESOLUTION_8B + * @retval ADC conversion data equivalent voltage value (unit: mVolt) + */ +#define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \ + ((0x00000FFFU) >> ((__DAC_RESOLUTION__) << 1U)) + +/** + * @brief Helper macro to calculate the DAC conversion data (unit: digital + * value) corresponding to a voltage (unit: mVolt). + * @note This helper macro is intended to provide input data in voltage + * rather than digital value, + * to be used with LL DAC functions such as + * @ref LL_DAC_ConvertData12RightAligned(). + * @note Analog reference voltage (Vref+) must be either known from + * user board environment or can be calculated using ADC measurement + * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). + * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) + * @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel + * (unit: mVolt). + * @param __DAC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref LL_DAC_RESOLUTION_12B + * @arg @ref LL_DAC_RESOLUTION_8B + * @retval DAC conversion data (unit: digital value) + */ +#define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\ + __DAC_VOLTAGE__,\ + __DAC_RESOLUTION__) \ + ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \ + / (__VREFANALOG_VOLTAGE__) \ + ) + +/** + * @} + */ + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup DAC_LL_Exported_Functions DAC Exported Functions + * @{ + */ + +#if defined (DAC_CR_HFSEL) /* High frequency interface mode */ + +/** @defgroup DAC_LL_EF_High_Frequency_Configuration High Frequency Configuration of DAC instance + * @{ + */ +/** + * @brief Set the high frequency interface mode for the selected DAC instance + * @rmtoll CR HFSEL LL_DAC_SetHighFrequencyMode + * @param DACx DAC instance + * @param HighFreqMode This parameter can be one of the following values: + * @arg @ref LL_DAC_HIGH_FREQ_MODE_DISABLE + * @arg @ref LL_DAC_HIGH_FREQ_MODE_ABOVE_80MHZ + * @retval None + */ +__STATIC_INLINE void LL_DAC_SetHighFrequencyMode(DAC_TypeDef *DACx, uint32_t HighFreqMode) +{ + MODIFY_REG(DACx->CR, DAC_CR_HFSEL, HighFreqMode); +} + +/** + * @brief Get the high frequency interface mode for the selected DAC instance + * @rmtoll CR HFSEL LL_DAC_GetHighFrequencyMode + * @param DACx DAC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_DAC_HIGH_FREQ_MODE_DISABLE + * @arg @ref LL_DAC_HIGH_FREQ_MODE_ABOVE_80MHZ + */ +__STATIC_INLINE uint32_t LL_DAC_GetHighFrequencyMode(DAC_TypeDef *DACx) +{ + return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_HFSEL)); +} +/** + * @} + */ + +#endif /* High frequency interface mode */ + +/** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels + * @{ + */ + +/** + * @brief Set the operating mode for the selected DAC channel: + * calibration or normal operating mode. + * @rmtoll CR CEN1 LL_DAC_SetMode\n + * CR CEN2 LL_DAC_SetMode + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 + * @param ChannelMode This parameter can be one of the following values: + * @arg @ref LL_DAC_MODE_NORMAL_OPERATION + * @arg @ref LL_DAC_MODE_CALIBRATION + * @retval None + */ +__STATIC_INLINE void LL_DAC_SetMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t ChannelMode) +{ + MODIFY_REG(DACx->CR, + DAC_CR_CEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), + ChannelMode << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); +} + +/** + * @brief Get the operating mode for the selected DAC channel: + * calibration or normal operating mode. + * @rmtoll CR CEN1 LL_DAC_GetMode\n + * CR CEN2 LL_DAC_GetMode + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DAC_MODE_NORMAL_OPERATION + * @arg @ref LL_DAC_MODE_CALIBRATION + */ +__STATIC_INLINE uint32_t LL_DAC_GetMode(DAC_TypeDef *DACx, uint32_t DAC_Channel) +{ + return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_CEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) + >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) + ); +} + +/** + * @brief Set the offset trimming value for the selected DAC channel. + * Trimming has an impact when output buffer is enabled + * and is intended to replace factory calibration default values. + * @rmtoll CCR OTRIM1 LL_DAC_SetTrimmingValue\n + * CCR OTRIM2 LL_DAC_SetTrimmingValue + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 + * @param TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F + * @retval None + */ +__STATIC_INLINE void LL_DAC_SetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TrimmingValue) +{ + MODIFY_REG(DACx->CCR, + DAC_CCR_OTRIM1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), + TrimmingValue << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); +} + +/** + * @brief Get the offset trimming value for the selected DAC channel. + * Trimming has an impact when output buffer is enabled + * and is intended to replace factory calibration default values. + * @rmtoll CCR OTRIM1 LL_DAC_GetTrimmingValue\n + * CCR OTRIM2 LL_DAC_GetTrimmingValue + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 + * @retval TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F + */ +__STATIC_INLINE uint32_t LL_DAC_GetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC_Channel) +{ + return (uint32_t)(READ_BIT(DACx->CCR, DAC_CCR_OTRIM1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) + >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) + ); +} + +/** + * @brief Set the conversion trigger source for the selected DAC channel. + * @note For conversion trigger source to be effective, DAC trigger + * must be enabled using function @ref LL_DAC_EnableTrigger(). + * @note To set conversion trigger source, DAC channel must be disabled. + * Otherwise, the setting is discarded. + * @note Availability of parameters of trigger sources from timer + * depends on timers availability on the selected device. + * @rmtoll CR TSEL1 LL_DAC_SetTriggerSource\n + * CR TSEL2 LL_DAC_SetTriggerSource + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 + * @param TriggerSource This parameter can be one of the following values: + * @arg @ref LL_DAC_TRIG_SOFTWARE + * @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO + * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO + * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO + * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO + * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO + * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO + * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO + * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO + * @arg @ref LL_DAC_TRIG_EXT_LPTIM1_OUT + * @arg @ref LL_DAC_TRIG_EXT_LPTIM2_OUT + * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9 + * @retval None + */ +__STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource) +{ + MODIFY_REG(DACx->CR, + DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), + TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); +} + +/** + * @brief Get the conversion trigger source for the selected DAC channel. + * @note For conversion trigger source to be effective, DAC trigger + * must be enabled using function @ref LL_DAC_EnableTrigger(). + * @note Availability of parameters of trigger sources from timer + * depends on timers availability on the selected device. + * @rmtoll CR TSEL1 LL_DAC_GetTriggerSource\n + * CR TSEL2 LL_DAC_GetTriggerSource + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 (1) + * + * (1) On this STM32 serie, parameter not available on all devices. + * Refer to device datasheet for channels availability. + * @retval Returned value can be one of the following values: + * @arg @ref LL_DAC_TRIG_SOFTWARE + * @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO + * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO + * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO + * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO + * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO + * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO + * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO + * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO + * @arg @ref LL_DAC_TRIG_EXT_LPTIM1_OUT + * @arg @ref LL_DAC_TRIG_EXT_LPTIM2_OUT + * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9 + */ +__STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel) +{ + return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) + >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) + ); +} + +/** + * @brief Set the waveform automatic generation mode + * for the selected DAC channel. + * @rmtoll CR WAVE1 LL_DAC_SetWaveAutoGeneration\n + * CR WAVE2 LL_DAC_SetWaveAutoGeneration + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 (1) + * + * (1) On this STM32 serie, parameter not available on all devices. + * Refer to device datasheet for channels availability. + * @param WaveAutoGeneration This parameter can be one of the following values: + * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE + * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE + * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE + * @retval None + */ +__STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration) +{ + MODIFY_REG(DACx->CR, + DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), + WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); +} + +/** + * @brief Get the waveform automatic generation mode + * for the selected DAC channel. + * @rmtoll CR WAVE1 LL_DAC_GetWaveAutoGeneration\n + * CR WAVE2 LL_DAC_GetWaveAutoGeneration + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 (1) + * + * (1) On this STM32 serie, parameter not available on all devices. + * Refer to device datasheet for channels availability. + * @retval Returned value can be one of the following values: + * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE + * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE + * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE + */ +__STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel) +{ + return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) + >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) + ); +} + +/** + * @brief Set the noise waveform generation for the selected DAC channel: + * Noise mode and parameters LFSR (linear feedback shift register). + * @note For wave generation to be effective, DAC channel + * wave generation mode must be enabled using + * function @ref LL_DAC_SetWaveAutoGeneration(). + * @note This setting can be set when the selected DAC channel is disabled + * (otherwise, the setting operation is ignored). + * @rmtoll CR MAMP1 LL_DAC_SetWaveNoiseLFSR\n + * CR MAMP2 LL_DAC_SetWaveNoiseLFSR + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 (1) + * + * (1) On this STM32 serie, parameter not available on all devices. + * Refer to device datasheet for channels availability. + * @param NoiseLFSRMask This parameter can be one of the following values: + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 + * @retval None + */ +__STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask) +{ + MODIFY_REG(DACx->CR, + DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), + NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); +} + +/** + * @brief Get the noise waveform generation for the selected DAC channel: + * Noise mode and parameters LFSR (linear feedback shift register). + * @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n + * CR MAMP2 LL_DAC_GetWaveNoiseLFSR + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 (1) + * + * (1) On this STM32 serie, parameter not available on all devices. + * Refer to device datasheet for channels availability. + * @retval Returned value can be one of the following values: + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 + */ +__STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel) +{ + return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) + >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) + ); +} + +/** + * @brief Set the triangle waveform generation for the selected DAC channel: + * triangle mode and amplitude. + * @note For wave generation to be effective, DAC channel + * wave generation mode must be enabled using + * function @ref LL_DAC_SetWaveAutoGeneration(). + * @note This setting can be set when the selected DAC channel is disabled + * (otherwise, the setting operation is ignored). + * @rmtoll CR MAMP1 LL_DAC_SetWaveTriangleAmplitude\n + * CR MAMP2 LL_DAC_SetWaveTriangleAmplitude + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 (1) + * + * (1) On this STM32 serie, parameter not available on all devices. + * Refer to device datasheet for channels availability. + * @param TriangleAmplitude This parameter can be one of the following values: + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095 + * @retval None + */ +__STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel, + uint32_t TriangleAmplitude) +{ + MODIFY_REG(DACx->CR, + DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), + TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); +} + +/** + * @brief Get the triangle waveform generation for the selected DAC channel: + * triangle mode and amplitude. + * @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n + * CR MAMP2 LL_DAC_GetWaveTriangleAmplitude + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 (1) + * + * (1) On this STM32 serie, parameter not available on all devices. + * Refer to device datasheet for channels availability. + * @retval Returned value can be one of the following values: + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095 + */ +__STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel) +{ + return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) + >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) + ); +} + +/** + * @brief Set the output for the selected DAC channel. + * @note This function set several features: + * - mode normal or sample-and-hold + * - buffer + * - connection to GPIO or internal path. + * These features can also be set individually using + * dedicated functions: + * - @ref LL_DAC_SetOutputBuffer() + * - @ref LL_DAC_SetOutputMode() + * - @ref LL_DAC_SetOutputConnection() + * @note On this STM32 serie, output connection depends on output mode + * (normal or sample and hold) and output buffer state. + * - if output connection is set to internal path and output buffer + * is enabled (whatever output mode): + * output connection is also connected to GPIO pin + * (both connections to GPIO pin and internal path). + * - if output connection is set to GPIO pin, output buffer + * is disabled, output mode set to sample and hold: + * output connection is also connected to internal path + * (both connections to GPIO pin and internal path). + * @note Mode sample-and-hold requires an external capacitor + * to be connected between DAC channel output and ground. + * Capacitor value depends on load on DAC channel output and + * sample-and-hold timings configured. + * As indication, capacitor typical value is 100nF + * (refer to device datasheet, parameter "CSH"). + * @rmtoll CR MODE1 LL_DAC_ConfigOutput\n + * CR MODE2 LL_DAC_ConfigOutput + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 (1) + * + * (1) On this STM32 serie, parameter not available on all devices. + * Refer to device datasheet for channels availability. + * @param OutputMode This parameter can be one of the following values: + * @arg @ref LL_DAC_OUTPUT_MODE_NORMAL + * @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD + * @param OutputBuffer This parameter can be one of the following values: + * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE + * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE + * @param OutputConnection This parameter can be one of the following values: + * @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO + * @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL + * @retval None + */ +__STATIC_INLINE void LL_DAC_ConfigOutput(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode, + uint32_t OutputBuffer, uint32_t OutputConnection) +{ + MODIFY_REG(DACx->MCR, + (DAC_MCR_MODE1_2 | DAC_MCR_MODE1_1 | DAC_MCR_MODE1_0) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), + (OutputMode | OutputBuffer | OutputConnection) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); +} + +/** + * @brief Set the output mode normal or sample-and-hold + * for the selected DAC channel. + * @note Mode sample-and-hold requires an external capacitor + * to be connected between DAC channel output and ground. + * Capacitor value depends on load on DAC channel output and + * sample-and-hold timings configured. + * As indication, capacitor typical value is 100nF + * (refer to device datasheet, parameter "CSH"). + * @rmtoll CR MODE1 LL_DAC_SetOutputMode\n + * CR MODE2 LL_DAC_SetOutputMode + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 (1) + * + * (1) On this STM32 serie, parameter not available on all devices. + * Refer to device datasheet for channels availability. + * @param OutputMode This parameter can be one of the following values: + * @arg @ref LL_DAC_OUTPUT_MODE_NORMAL + * @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD + * @retval None + */ +__STATIC_INLINE void LL_DAC_SetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode) +{ + MODIFY_REG(DACx->MCR, + (uint32_t)DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), + OutputMode << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); +} + +/** + * @brief Get the output mode normal or sample-and-hold for the selected DAC channel. + * @rmtoll CR MODE1 LL_DAC_GetOutputMode\n + * CR MODE2 LL_DAC_GetOutputMode + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 (1) + * + * (1) On this STM32 serie, parameter not available on all devices. + * Refer to device datasheet for channels availability. + * @retval Returned value can be one of the following values: + * @arg @ref LL_DAC_OUTPUT_MODE_NORMAL + * @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD + */ +__STATIC_INLINE uint32_t LL_DAC_GetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channel) +{ + return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) + >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) + ); +} + +/** + * @brief Set the output buffer for the selected DAC channel. + * @note On this STM32 serie, when buffer is enabled, its offset can be + * trimmed: factory calibration default values can be + * replaced by user trimming values, using function + * @ref LL_DAC_SetTrimmingValue(). + * @rmtoll CR MODE1 LL_DAC_SetOutputBuffer\n + * CR MODE2 LL_DAC_SetOutputBuffer + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 (1) + * + * (1) On this STM32 serie, parameter not available on all devices. + * Refer to device datasheet for channels availability. + * @param OutputBuffer This parameter can be one of the following values: + * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE + * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE + * @retval None + */ +__STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer) +{ + MODIFY_REG(DACx->MCR, + (uint32_t)DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), + OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); +} + +/** + * @brief Get the output buffer state for the selected DAC channel. + * @rmtoll CR MODE1 LL_DAC_GetOutputBuffer\n + * CR MODE2 LL_DAC_GetOutputBuffer + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 (1) + * + * (1) On this STM32 serie, parameter not available on all devices. + * Refer to device datasheet for channels availability. + * @retval Returned value can be one of the following values: + * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE + * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE + */ +__STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel) +{ + return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) + >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) + ); +} + +/** + * @brief Set the output connection for the selected DAC channel. + * @note On this STM32 serie, output connection depends on output mode (normal or + * sample and hold) and output buffer state. + * - if output connection is set to internal path and output buffer + * is enabled (whatever output mode): + * output connection is also connected to GPIO pin + * (both connections to GPIO pin and internal path). + * - if output connection is set to GPIO pin, output buffer + * is disabled, output mode set to sample and hold: + * output connection is also connected to internal path + * (both connections to GPIO pin and internal path). + * @rmtoll CR MODE1 LL_DAC_SetOutputConnection\n + * CR MODE2 LL_DAC_SetOutputConnection + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 (1) + * + * (1) On this STM32 serie, parameter not available on all devices. + * Refer to device datasheet for channels availability. + * @param OutputConnection This parameter can be one of the following values: + * @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO + * @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL + * @retval None + */ +__STATIC_INLINE void LL_DAC_SetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputConnection) +{ + MODIFY_REG(DACx->MCR, + (uint32_t)DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), + OutputConnection << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); +} + +/** + * @brief Get the output connection for the selected DAC channel. + * @note On this STM32 serie, output connection depends on output mode (normal or + * sample and hold) and output buffer state. + * - if output connection is set to internal path and output buffer + * is enabled (whatever output mode): + * output connection is also connected to GPIO pin + * (both connections to GPIO pin and internal path). + * - if output connection is set to GPIO pin, output buffer + * is disabled, output mode set to sample and hold: + * output connection is also connected to internal path + * (both connections to GPIO pin and internal path). + * @rmtoll CR MODE1 LL_DAC_GetOutputConnection\n + * CR MODE2 LL_DAC_GetOutputConnection + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 (1) + * + * (1) On this STM32 serie, parameter not available on all devices. + * Refer to device datasheet for channels availability. + * @retval Returned value can be one of the following values: + * @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO + * @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL + */ +__STATIC_INLINE uint32_t LL_DAC_GetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_Channel) +{ + return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) + >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) + ); +} + +/** + * @brief Set the sample-and-hold timing for the selected DAC channel: + * sample time + * @note Sample time must be set when DAC channel is disabled + * or during DAC operation when DAC channel flag BWSTx is reset, + * otherwise the setting is ignored. + * Check BWSTx flag state using function "LL_DAC_IsActiveFlag_BWSTx()". + * @rmtoll SHSR1 TSAMPLE1 LL_DAC_SetSampleAndHoldSampleTime\n + * SHSR2 TSAMPLE2 LL_DAC_SetSampleAndHoldSampleTime + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 (1) + * + * (1) On this STM32 serie, parameter not available on all devices. + * Refer to device datasheet for channels availability. + * @param SampleTime Value between Min_Data=0x000 and Max_Data=0x3FF + * @retval None + */ +__STATIC_INLINE void LL_DAC_SetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t SampleTime) +{ + __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0); + + MODIFY_REG(*preg, + DAC_SHSR1_TSAMPLE1, + SampleTime); +} + +/** + * @brief Get the sample-and-hold timing for the selected DAC channel: + * sample time + * @rmtoll SHSR1 TSAMPLE1 LL_DAC_GetSampleAndHoldSampleTime\n + * SHSR2 TSAMPLE2 LL_DAC_GetSampleAndHoldSampleTime + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 (1) + * + * (1) On this STM32 serie, parameter not available on all devices. + * Refer to device datasheet for channels availability. + * @retval Value between Min_Data=0x000 and Max_Data=0x3FF + */ +__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel) +{ + __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0); + + return (uint32_t) READ_BIT(*preg, DAC_SHSR1_TSAMPLE1); +} + +/** + * @brief Set the sample-and-hold timing for the selected DAC channel: + * hold time + * @rmtoll SHHR THOLD1 LL_DAC_SetSampleAndHoldHoldTime\n + * SHHR THOLD2 LL_DAC_SetSampleAndHoldHoldTime + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 (1) + * + * (1) On this STM32 serie, parameter not available on all devices. + * Refer to device datasheet for channels availability. + * @param HoldTime Value between Min_Data=0x000 and Max_Data=0x3FF + * @retval None + */ +__STATIC_INLINE void LL_DAC_SetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t HoldTime) +{ + MODIFY_REG(DACx->SHHR, + DAC_SHHR_THOLD1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), + HoldTime << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); +} + +/** + * @brief Get the sample-and-hold timing for the selected DAC channel: + * hold time + * @rmtoll SHHR THOLD1 LL_DAC_GetSampleAndHoldHoldTime\n + * SHHR THOLD2 LL_DAC_GetSampleAndHoldHoldTime + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 (1) + * + * (1) On this STM32 serie, parameter not available on all devices. + * Refer to device datasheet for channels availability. + * @retval Value between Min_Data=0x000 and Max_Data=0x3FF + */ +__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint32_t DAC_Channel) +{ + return (uint32_t)(READ_BIT(DACx->SHHR, DAC_SHHR_THOLD1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) + >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) + ); +} + +/** + * @brief Set the sample-and-hold timing for the selected DAC channel: + * refresh time + * @rmtoll SHRR TREFRESH1 LL_DAC_SetSampleAndHoldRefreshTime\n + * SHRR TREFRESH2 LL_DAC_SetSampleAndHoldRefreshTime + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 (1) + * + * (1) On this STM32 serie, parameter not available on all devices. + * Refer to device datasheet for channels availability. + * @param RefreshTime Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_DAC_SetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t RefreshTime) +{ + MODIFY_REG(DACx->SHRR, + DAC_SHRR_TREFRESH1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), + RefreshTime << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); +} + +/** + * @brief Get the sample-and-hold timing for the selected DAC channel: + * refresh time + * @rmtoll SHRR TREFRESH1 LL_DAC_GetSampleAndHoldRefreshTime\n + * SHRR TREFRESH2 LL_DAC_GetSampleAndHoldRefreshTime + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 (1) + * + * (1) On this STM32 serie, parameter not available on all devices. + * Refer to device datasheet for channels availability. + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, uint32_t DAC_Channel) +{ + return (uint32_t)(READ_BIT(DACx->SHRR, DAC_SHRR_TREFRESH1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) + >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) + ); +} + +/** + * @} + */ + +/** @defgroup DAC_LL_EF_DMA_Management DMA Management + * @{ + */ + +/** + * @brief Enable DAC DMA transfer request of the selected channel. + * @note To configure DMA source address (peripheral address), + * use function @ref LL_DAC_DMA_GetRegAddr(). + * @rmtoll CR DMAEN1 LL_DAC_EnableDMAReq\n + * CR DMAEN2 LL_DAC_EnableDMAReq + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 (1) + * + * (1) On this STM32 serie, parameter not available on all devices. + * Refer to device datasheet for channels availability. + * @retval None + */ +__STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel) +{ + SET_BIT(DACx->CR, + DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); +} + +/** + * @brief Disable DAC DMA transfer request of the selected channel. + * @note To configure DMA source address (peripheral address), + * use function @ref LL_DAC_DMA_GetRegAddr(). + * @rmtoll CR DMAEN1 LL_DAC_DisableDMAReq\n + * CR DMAEN2 LL_DAC_DisableDMAReq + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 (1) + * + * (1) On this STM32 serie, parameter not available on all devices. + * Refer to device datasheet for channels availability. + * @retval None + */ +__STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel) +{ + CLEAR_BIT(DACx->CR, + DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); +} + +/** + * @brief Get DAC DMA transfer request state of the selected channel. + * (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled) + * @rmtoll CR DMAEN1 LL_DAC_IsDMAReqEnabled\n + * CR DMAEN2 LL_DAC_IsDMAReqEnabled + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 (1) + * + * (1) On this STM32 serie, parameter not available on all devices. + * Refer to device datasheet for channels availability. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel) +{ + return ((READ_BIT(DACx->CR, + DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) + == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL); +} + +/** + * @brief Function to help to configure DMA transfer to DAC: retrieve the + * DAC register address from DAC instance and a list of DAC registers + * intended to be used (most commonly) with DMA transfer. + * @note These DAC registers are data holding registers: + * when DAC conversion is requested, DAC generates a DMA transfer + * request to have data available in DAC data holding registers. + * @note This macro is intended to be used with LL DMA driver, refer to + * function "LL_DMA_ConfigAddresses()". + * Example: + * LL_DMA_ConfigAddresses(DMA1, + * LL_DMA_CHANNEL_1, + * (uint32_t)&< array or variable >, + * LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED), + * LL_DMA_DIRECTION_MEMORY_TO_PERIPH); + * @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n + * DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n + * DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n + * DHR12R2 DACC2DHR LL_DAC_DMA_GetRegAddr\n + * DHR12L2 DACC2DHR LL_DAC_DMA_GetRegAddr\n + * DHR8R2 DACC2DHR LL_DAC_DMA_GetRegAddr + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 (1) + * + * (1) On this STM32 serie, parameter not available on all devices. + * Refer to device datasheet for channels availability. + * @param Register This parameter can be one of the following values: + * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED + * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED + * @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED + * @retval DAC register address + */ +__STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register) +{ + /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */ + /* DAC channel selected. */ + return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, + ((DAC_Channel >> (Register & 0x1FUL)) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0)))); +} +/** + * @} + */ + +/** @defgroup DAC_LL_EF_Operation Operation on DAC channels + * @{ + */ + +/** + * @brief Enable DAC selected channel. + * @rmtoll CR EN1 LL_DAC_Enable\n + * CR EN2 LL_DAC_Enable + * @note After enable from off state, DAC channel requires a delay + * for output voltage to reach accuracy +/- 1 LSB. + * Refer to device datasheet, parameter "tWAKEUP". + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 (1) + * + * (1) On this STM32 serie, parameter not available on all devices. + * Refer to device datasheet for channels availability. + * @retval None + */ +__STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel) +{ + SET_BIT(DACx->CR, + DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); +} + +/** + * @brief Disable DAC selected channel. + * @rmtoll CR EN1 LL_DAC_Disable\n + * CR EN2 LL_DAC_Disable + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 (1) + * + * (1) On this STM32 serie, parameter not available on all devices. + * Refer to device datasheet for channels availability. + * @retval None + */ +__STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel) +{ + CLEAR_BIT(DACx->CR, + DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); +} + +/** + * @brief Get DAC enable state of the selected channel. + * (0: DAC channel is disabled, 1: DAC channel is enabled) + * @rmtoll CR EN1 LL_DAC_IsEnabled\n + * CR EN2 LL_DAC_IsEnabled + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 (1) + * + * (1) On this STM32 serie, parameter not available on all devices. + * Refer to device datasheet for channels availability. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel) +{ + return ((READ_BIT(DACx->CR, + DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) + == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL); +} + +/** + * @brief Enable DAC trigger of the selected channel. + * @note - If DAC trigger is disabled, DAC conversion is performed + * automatically once the data holding register is updated, + * using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()": + * @ref LL_DAC_ConvertData12RightAligned(), ... + * - If DAC trigger is enabled, DAC conversion is performed + * only when a hardware of software trigger event is occurring. + * Select trigger source using + * function @ref LL_DAC_SetTriggerSource(). + * @rmtoll CR TEN1 LL_DAC_EnableTrigger\n + * CR TEN2 LL_DAC_EnableTrigger + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 (1) + * + * (1) On this STM32 serie, parameter not available on all devices. + * Refer to device datasheet for channels availability. + * @retval None + */ +__STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel) +{ + SET_BIT(DACx->CR, + DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); +} + +/** + * @brief Disable DAC trigger of the selected channel. + * @rmtoll CR TEN1 LL_DAC_DisableTrigger\n + * CR TEN2 LL_DAC_DisableTrigger + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 (1) + * + * (1) On this STM32 serie, parameter not available on all devices. + * Refer to device datasheet for channels availability. + * @retval None + */ +__STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel) +{ + CLEAR_BIT(DACx->CR, + DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); +} + +/** + * @brief Get DAC trigger state of the selected channel. + * (0: DAC trigger is disabled, 1: DAC trigger is enabled) + * @rmtoll CR TEN1 LL_DAC_IsTriggerEnabled\n + * CR TEN2 LL_DAC_IsTriggerEnabled + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 (1) + * + * (1) On this STM32 serie, parameter not available on all devices. + * Refer to device datasheet for channels availability. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel) +{ + return ((READ_BIT(DACx->CR, + DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) + == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL); +} + +/** + * @brief Trig DAC conversion by software for the selected DAC channel. + * @note Preliminarily, DAC trigger must be set to software trigger + * using function + * @ref LL_DAC_Init() + * @ref LL_DAC_SetTriggerSource() + * with parameter "LL_DAC_TRIGGER_SOFTWARE". + * and DAC trigger must be enabled using + * function @ref LL_DAC_EnableTrigger(). + * @note For devices featuring DAC with 2 channels: this function + * can perform a SW start of both DAC channels simultaneously. + * Two channels can be selected as parameter. + * Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2) + * @rmtoll SWTRIGR SWTRIG1 LL_DAC_TrigSWConversion\n + * SWTRIGR SWTRIG2 LL_DAC_TrigSWConversion + * @param DACx DAC instance + * @param DAC_Channel This parameter can a combination of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 (1) + * + * (1) On this STM32 serie, parameter not available on all devices. + * Refer to device datasheet for channels availability. + * @retval None + */ +__STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel) +{ + SET_BIT(DACx->SWTRIGR, + (DAC_Channel & DAC_SWTR_CHX_MASK)); +} + +/** + * @brief Set the data to be loaded in the data holding register + * in format 12 bits left alignment (LSB aligned on bit 0), + * for the selected DAC channel. + * @rmtoll DHR12R1 DACC1DHR LL_DAC_ConvertData12RightAligned\n + * DHR12R2 DACC2DHR LL_DAC_ConvertData12RightAligned + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 (1) + * + * (1) On this STM32 serie, parameter not available on all devices. + * Refer to device datasheet for channels availability. + * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF + * @retval None + */ +__STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) +{ + __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0); + + MODIFY_REG(*preg, + DAC_DHR12R1_DACC1DHR, + Data); +} + +/** + * @brief Set the data to be loaded in the data holding register + * in format 12 bits left alignment (MSB aligned on bit 15), + * for the selected DAC channel. + * @rmtoll DHR12L1 DACC1DHR LL_DAC_ConvertData12LeftAligned\n + * DHR12L2 DACC2DHR LL_DAC_ConvertData12LeftAligned + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 (1) + * + * (1) On this STM32 serie, parameter not available on all devices. + * Refer to device datasheet for channels availability. + * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF + * @retval None + */ +__STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) +{ + __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0); + + MODIFY_REG(*preg, + DAC_DHR12L1_DACC1DHR, + Data); +} + +/** + * @brief Set the data to be loaded in the data holding register + * in format 8 bits left alignment (LSB aligned on bit 0), + * for the selected DAC channel. + * @rmtoll DHR8R1 DACC1DHR LL_DAC_ConvertData8RightAligned\n + * DHR8R2 DACC2DHR LL_DAC_ConvertData8RightAligned + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 (1) + * + * (1) On this STM32 serie, parameter not available on all devices. + * Refer to device datasheet for channels availability. + * @param Data Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) +{ + __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0); + + MODIFY_REG(*preg, + DAC_DHR8R1_DACC1DHR, + Data); +} + +#if defined(DAC_CHANNEL2_SUPPORT) +/** + * @brief Set the data to be loaded in the data holding register + * in format 12 bits left alignment (LSB aligned on bit 0), + * for both DAC channels. + * @rmtoll DHR12RD DACC1DHR LL_DAC_ConvertDualData12RightAligned\n + * DHR12RD DACC2DHR LL_DAC_ConvertDualData12RightAligned + * @param DACx DAC instance + * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF + * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF + * @retval None + */ +__STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, + uint32_t DataChannel2) +{ + MODIFY_REG(DACx->DHR12RD, + (DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR), + ((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) | DataChannel1)); +} + +/** + * @brief Set the data to be loaded in the data holding register + * in format 12 bits left alignment (MSB aligned on bit 15), + * for both DAC channels. + * @rmtoll DHR12LD DACC1DHR LL_DAC_ConvertDualData12LeftAligned\n + * DHR12LD DACC2DHR LL_DAC_ConvertDualData12LeftAligned + * @param DACx DAC instance + * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF + * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF + * @retval None + */ +__STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2) +{ + /* Note: Data of DAC channel 2 shift value subtracted of 4 because */ + /* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */ + /* the 4 LSB must be taken into account for the shift value. */ + MODIFY_REG(DACx->DHR12LD, + (DAC_DHR12LD_DACC2DHR | DAC_DHR12LD_DACC1DHR), + ((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) | DataChannel1)); +} + +/** + * @brief Set the data to be loaded in the data holding register + * in format 8 bits left alignment (LSB aligned on bit 0), + * for both DAC channels. + * @rmtoll DHR8RD DACC1DHR LL_DAC_ConvertDualData8RightAligned\n + * DHR8RD DACC2DHR LL_DAC_ConvertDualData8RightAligned + * @param DACx DAC instance + * @param DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF + * @param DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2) +{ + MODIFY_REG(DACx->DHR8RD, + (DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR), + ((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1)); +} + +#endif /* DAC_CHANNEL2_SUPPORT */ +/** + * @brief Retrieve output data currently generated for the selected DAC channel. + * @note Whatever alignment and resolution settings + * (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()": + * @ref LL_DAC_ConvertData12RightAligned(), ...), + * output data format is 12 bits right aligned (LSB aligned on bit 0). + * @rmtoll DOR1 DACC1DOR LL_DAC_RetrieveOutputData\n + * DOR2 DACC2DOR LL_DAC_RetrieveOutputData + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 (1) + * + * (1) On this STM32 serie, parameter not available on all devices. + * Refer to device datasheet for channels availability. + * @retval Value between Min_Data=0x000 and Max_Data=0xFFF + */ +__STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel) +{ + __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DORX_REGOFFSET_MASK_POSBIT0); + + return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR); +} + +/** + * @} + */ + +/** @defgroup DAC_LL_EF_FLAG_Management FLAG Management + * @{ + */ +/** + * @brief Get DAC calibration offset flag for DAC channel 1 + * @rmtoll SR CAL_FLAG1 LL_DAC_IsActiveFlag_CAL1 + * @param DACx DAC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL1(DAC_TypeDef *DACx) +{ + return ((READ_BIT(DACx->SR, LL_DAC_FLAG_CAL1) == (LL_DAC_FLAG_CAL1)) ? 1UL : 0UL); +} + +#if defined(DAC_CHANNEL2_SUPPORT) +/** + * @brief Get DAC calibration offset flag for DAC channel 2 + * @rmtoll SR CAL_FLAG2 LL_DAC_IsActiveFlag_CAL2 + * @param DACx DAC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL2(DAC_TypeDef *DACx) +{ + return ((READ_BIT(DACx->SR, LL_DAC_FLAG_CAL2) == (LL_DAC_FLAG_CAL2)) ? 1UL : 0UL); +} + +#endif /* DAC_CHANNEL2_SUPPORT */ +/** + * @brief Get DAC busy writing sample time flag for DAC channel 1 + * @rmtoll SR BWST1 LL_DAC_IsActiveFlag_BWST1 + * @param DACx DAC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST1(DAC_TypeDef *DACx) +{ + return ((READ_BIT(DACx->SR, LL_DAC_FLAG_BWST1) == (LL_DAC_FLAG_BWST1)) ? 1UL : 0UL); +} + +#if defined(DAC_CHANNEL2_SUPPORT) +/** + * @brief Get DAC busy writing sample time flag for DAC channel 2 + * @rmtoll SR BWST2 LL_DAC_IsActiveFlag_BWST2 + * @param DACx DAC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST2(DAC_TypeDef *DACx) +{ + return ((READ_BIT(DACx->SR, LL_DAC_FLAG_BWST2) == (LL_DAC_FLAG_BWST2)) ? 1UL : 0UL); +} + +#endif /* DAC_CHANNEL2_SUPPORT */ +/** + * @brief Get DAC underrun flag for DAC channel 1 + * @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1 + * @param DACx DAC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx) +{ + return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1)) ? 1UL : 0UL); +} + +#if defined(DAC_CHANNEL2_SUPPORT) +/** + * @brief Get DAC underrun flag for DAC channel 2 + * @rmtoll SR DMAUDR2 LL_DAC_IsActiveFlag_DMAUDR2 + * @param DACx DAC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx) +{ + return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2)) ? 1UL : 0UL); +} +#endif /* DAC_CHANNEL2_SUPPORT */ + +/** + * @brief Clear DAC underrun flag for DAC channel 1 + * @rmtoll SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1 + * @param DACx DAC instance + * @retval None + */ +__STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx) +{ + WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1); +} + +#if defined(DAC_CHANNEL2_SUPPORT) +/** + * @brief Clear DAC underrun flag for DAC channel 2 + * @rmtoll SR DMAUDR2 LL_DAC_ClearFlag_DMAUDR2 + * @param DACx DAC instance + * @retval None + */ +__STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx) +{ + WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2); +} +#endif /* DAC_CHANNEL2_SUPPORT */ + +/** + * @} + */ + +/** @defgroup DAC_LL_EF_IT_Management IT management + * @{ + */ + +/** + * @brief Enable DMA underrun interrupt for DAC channel 1 + * @rmtoll CR DMAUDRIE1 LL_DAC_EnableIT_DMAUDR1 + * @param DACx DAC instance + * @retval None + */ +__STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx) +{ + SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1); +} + +#if defined(DAC_CHANNEL2_SUPPORT) +/** + * @brief Enable DMA underrun interrupt for DAC channel 2 + * @rmtoll CR DMAUDRIE2 LL_DAC_EnableIT_DMAUDR2 + * @param DACx DAC instance + * @retval None + */ +__STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx) +{ + SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2); +} +#endif /* DAC_CHANNEL2_SUPPORT */ + +/** + * @brief Disable DMA underrun interrupt for DAC channel 1 + * @rmtoll CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1 + * @param DACx DAC instance + * @retval None + */ +__STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx) +{ + CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1); +} + +#if defined(DAC_CHANNEL2_SUPPORT) +/** + * @brief Disable DMA underrun interrupt for DAC channel 2 + * @rmtoll CR DMAUDRIE2 LL_DAC_DisableIT_DMAUDR2 + * @param DACx DAC instance + * @retval None + */ +__STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx) +{ + CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2); +} +#endif /* DAC_CHANNEL2_SUPPORT */ + +/** + * @brief Get DMA underrun interrupt for DAC channel 1 + * @rmtoll CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1 + * @param DACx DAC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx) +{ + return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1)) ? 1UL : 0UL); +} + +#if defined(DAC_CHANNEL2_SUPPORT) +/** + * @brief Get DMA underrun interrupt for DAC channel 2 + * @rmtoll CR DMAUDRIE2 LL_DAC_IsEnabledIT_DMAUDR2 + * @param DACx DAC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx) +{ + return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2)) ? 1UL : 0UL); +} +#endif /* DAC_CHANNEL2_SUPPORT */ + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx); +ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct); +void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* DAC1 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32L4xx_LL_DAC_H */ + diff --git a/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_dma.h b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_dma.h new file mode 100644 index 0000000..add3c4a --- /dev/null +++ b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_dma.h @@ -0,0 +1,2430 @@ +/** + ****************************************************************************** + * @file stm32l4xx_ll_dma.h + * @author MCD Application Team + * @brief Header file of DMA LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32L4xx_LL_DMA_H +#define STM32L4xx_LL_DMA_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx.h" +#if defined(DMAMUX1) +#include "stm32l4xx_ll_dmamux.h" +#endif /* DMAMUX1 */ + +/** @addtogroup STM32L4xx_LL_Driver + * @{ + */ + +#if defined (DMA1) || defined (DMA2) + +/** @defgroup DMA_LL DMA + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup DMA_LL_Private_Variables DMA Private Variables + * @{ + */ +/* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */ +static const uint8_t CHANNEL_OFFSET_TAB[] = +{ + (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE), + (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE), + (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE), + (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE), + (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE), + (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE), + (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE) +}; +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +#if defined(DMAMUX1) +#else +/** @defgroup DMA_LL_Private_Constants DMA Private Constants + * @{ + */ +/* Define used to get CSELR register offset */ +#define DMA_CSELR_OFFSET (uint32_t)(DMA1_CSELR_BASE - DMA1_BASE) + +/* Defines used for the bit position in the register and perform offsets */ +#define DMA_POSITION_CSELR_CXS POSITION_VAL(DMA_CSELR_C1S << (Channel*4U)) +/** + * @} + */ +#endif /* DMAMUX1 */ +/* Private macros ------------------------------------------------------------*/ +#if defined(DMAMUX1) + +/** @defgroup DMA_LL_Private_Macros DMA Private Macros + * @{ + */ +/** + * @brief Helper macro to convert DMA Instance DMAx into DMAMUX channel + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7. + * @param __DMA_INSTANCE__ DMAx + * @retval Channel_Offset (LL_DMA_CHANNEL_7 or 0). + */ +#define __LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(__DMA_INSTANCE__) \ +(((__DMA_INSTANCE__) == DMA1) ? 0x00000000U : LL_DMA_CHANNEL_7) + +/** + * @} + */ +#else +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup DMA_LL_Private_Macros DMA Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ +#endif /* DMAMUX1 */ +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure + * @{ + */ +typedef struct +{ + uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer + or as Source base address in case of memory to memory transfer direction. + + This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ + + uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer + or as Destination base address in case of memory to memory transfer direction. + + This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ + + uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, + from memory to memory or from peripheral to memory. + This parameter can be a value of @ref DMA_LL_EC_DIRECTION + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */ + + uint32_t Mode; /*!< Specifies the normal or circular operation mode. + This parameter can be a value of @ref DMA_LL_EC_MODE + @note: The circular buffer mode cannot be used if the memory to memory + data transfer direction is configured on the selected Channel + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */ + + uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction + is incremented or not. + This parameter can be a value of @ref DMA_LL_EC_PERIPH + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */ + + uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction + is incremented or not. + This parameter can be a value of @ref DMA_LL_EC_MEMORY + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */ + + uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word) + in case of memory to memory transfer direction. + This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */ + + uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word) + in case of memory to memory transfer direction. + This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */ + + uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit. + The data unit is equal to the source buffer configuration set in PeripheralSize + or MemorySize parameters depending in the transfer direction. + This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */ + +#if defined(DMAMUX1) + uint32_t PeriphRequest; /*!< Specifies the peripheral request. + This parameter can be a value of @ref DMAMUX_LL_EC_REQUEST + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */ +#else + uint32_t PeriphRequest; /*!< Specifies the peripheral request. + This parameter can be a value of @ref DMA_LL_EC_REQUEST + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */ +#endif /* DMAMUX1 */ + + uint32_t Priority; /*!< Specifies the channel priority level. + This parameter can be a value of @ref DMA_LL_EC_PRIORITY + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */ + +} LL_DMA_InitTypeDef; +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants + * @{ + */ +/** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_DMA_WriteReg function + * @{ + */ +#define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 /*!< Channel 1 global flag */ +#define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 /*!< Channel 1 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 /*!< Channel 1 half transfer flag */ +#define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 /*!< Channel 1 transfer error flag */ +#define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 /*!< Channel 2 global flag */ +#define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 /*!< Channel 2 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 /*!< Channel 2 half transfer flag */ +#define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 /*!< Channel 2 transfer error flag */ +#define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 /*!< Channel 3 global flag */ +#define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 /*!< Channel 3 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 /*!< Channel 3 half transfer flag */ +#define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 /*!< Channel 3 transfer error flag */ +#define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4 /*!< Channel 4 global flag */ +#define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4 /*!< Channel 4 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4 /*!< Channel 4 half transfer flag */ +#define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4 /*!< Channel 4 transfer error flag */ +#define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5 /*!< Channel 5 global flag */ +#define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5 /*!< Channel 5 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag */ +#define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5 /*!< Channel 5 transfer error flag */ +#define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6 /*!< Channel 6 global flag */ +#define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6 /*!< Channel 6 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6 /*!< Channel 6 half transfer flag */ +#define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6 /*!< Channel 6 transfer error flag */ +#define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7 /*!< Channel 7 global flag */ +#define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7 /*!< Channel 7 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7 /*!< Channel 7 half transfer flag */ +#define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7 /*!< Channel 7 transfer error flag */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_DMA_ReadReg function + * @{ + */ +#define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /*!< Channel 1 global flag */ +#define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1 /*!< Channel 1 transfer complete flag */ +#define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /*!< Channel 1 half transfer flag */ +#define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /*!< Channel 1 transfer error flag */ +#define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /*!< Channel 2 global flag */ +#define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2 /*!< Channel 2 transfer complete flag */ +#define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /*!< Channel 2 half transfer flag */ +#define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /*!< Channel 2 transfer error flag */ +#define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /*!< Channel 3 global flag */ +#define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3 /*!< Channel 3 transfer complete flag */ +#define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /*!< Channel 3 half transfer flag */ +#define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /*!< Channel 3 transfer error flag */ +#define LL_DMA_ISR_GIF4 DMA_ISR_GIF4 /*!< Channel 4 global flag */ +#define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4 /*!< Channel 4 transfer complete flag */ +#define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4 /*!< Channel 4 half transfer flag */ +#define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4 /*!< Channel 4 transfer error flag */ +#define LL_DMA_ISR_GIF5 DMA_ISR_GIF5 /*!< Channel 5 global flag */ +#define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5 /*!< Channel 5 transfer complete flag */ +#define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5 /*!< Channel 5 half transfer flag */ +#define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5 /*!< Channel 5 transfer error flag */ +#define LL_DMA_ISR_GIF6 DMA_ISR_GIF6 /*!< Channel 6 global flag */ +#define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6 /*!< Channel 6 transfer complete flag */ +#define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6 /*!< Channel 6 half transfer flag */ +#define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6 /*!< Channel 6 transfer error flag */ +#define LL_DMA_ISR_GIF7 DMA_ISR_GIF7 /*!< Channel 7 global flag */ +#define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7 /*!< Channel 7 transfer complete flag */ +#define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7 /*!< Channel 7 half transfer flag */ +#define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7 /*!< Channel 7 transfer error flag */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions + * @{ + */ +#define LL_DMA_CCR_TCIE DMA_CCR_TCIE /*!< Transfer complete interrupt */ +#define LL_DMA_CCR_HTIE DMA_CCR_HTIE /*!< Half Transfer interrupt */ +#define LL_DMA_CCR_TEIE DMA_CCR_TEIE /*!< Transfer error interrupt */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_CHANNEL CHANNEL + * @{ + */ +#define LL_DMA_CHANNEL_1 0x00000000U /*!< DMA Channel 1 */ +#define LL_DMA_CHANNEL_2 0x00000001U /*!< DMA Channel 2 */ +#define LL_DMA_CHANNEL_3 0x00000002U /*!< DMA Channel 3 */ +#define LL_DMA_CHANNEL_4 0x00000003U /*!< DMA Channel 4 */ +#define LL_DMA_CHANNEL_5 0x00000004U /*!< DMA Channel 5 */ +#define LL_DMA_CHANNEL_6 0x00000005U /*!< DMA Channel 6 */ +#define LL_DMA_CHANNEL_7 0x00000006U /*!< DMA Channel 7 */ +#if defined(USE_FULL_LL_DRIVER) +#define LL_DMA_CHANNEL_ALL 0xFFFF0000U /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */ +#endif /*USE_FULL_LL_DRIVER*/ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_DIRECTION Transfer Direction + * @{ + */ +#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ +#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */ +#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_MODE Transfer mode + * @{ + */ +#define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */ +#define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /*!< Circular Mode */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode + * @{ + */ +#define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /*!< Peripheral increment mode Enable */ +#define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_MEMORY Memory increment mode + * @{ + */ +#define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /*!< Memory increment mode Enable */ +#define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment + * @{ + */ +#define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */ +#define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */ +#define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment + * @{ + */ +#define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */ +#define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */ +#define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level + * @{ + */ +#define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ +#define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */ +#define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */ +#define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /*!< Priority level : Very_High */ +/** + * @} + */ + +#if !defined (DMAMUX1) +/** @defgroup DMA_LL_EC_REQUEST Transfer peripheral request + * @{ + */ +#define LL_DMA_REQUEST_0 0x00000000U /*!< DMA peripheral request 0 */ +#define LL_DMA_REQUEST_1 0x00000001U /*!< DMA peripheral request 1 */ +#define LL_DMA_REQUEST_2 0x00000002U /*!< DMA peripheral request 2 */ +#define LL_DMA_REQUEST_3 0x00000003U /*!< DMA peripheral request 3 */ +#define LL_DMA_REQUEST_4 0x00000004U /*!< DMA peripheral request 4 */ +#define LL_DMA_REQUEST_5 0x00000005U /*!< DMA peripheral request 5 */ +#define LL_DMA_REQUEST_6 0x00000006U /*!< DMA peripheral request 6 */ +#define LL_DMA_REQUEST_7 0x00000007U /*!< DMA peripheral request 7 */ +/** + * @} + */ +#endif /* !defined DMAMUX1 */ +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros + * @{ + */ + +/** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros + * @{ + */ +/** + * @brief Write a value in DMA register + * @param __INSTANCE__ DMA Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in DMA register + * @param __INSTANCE__ DMA Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely + * @{ + */ +/** + * @brief Convert DMAx_Channely into DMAx + * @param __CHANNEL_INSTANCE__ DMAx_Channely + * @retval DMAx + */ +#if defined(DMA2) +#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \ +(((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1) +#else +#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1) +#endif + +/** + * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y + * @param __CHANNEL_INSTANCE__ DMAx_Channely + * @retval LL_DMA_CHANNEL_y + */ +#if defined (DMA2) +#if defined (DMA2_Channel6) && defined (DMA2_Channel7) +#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ +(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel6)) ? LL_DMA_CHANNEL_6 : \ + LL_DMA_CHANNEL_7) +#else +#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ +(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \ + LL_DMA_CHANNEL_7) +#endif +#else +#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ +(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \ + LL_DMA_CHANNEL_7) +#endif + +/** + * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely + * @param __DMA_INSTANCE__ DMAx + * @param __CHANNEL__ LL_DMA_CHANNEL_y + * @retval DMAx_Channely + */ +#if defined (DMA2) +#if defined (DMA2_Channel6) && defined (DMA2_Channel7) +#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ +((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA2_Channel6 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) ? DMA1_Channel7 : \ + DMA2_Channel7) +#else +#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ +((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \ + DMA1_Channel7) +#endif +#else +#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ +((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \ + DMA1_Channel7) +#endif + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup DMA_LL_Exported_Functions DMA Exported Functions + * @{ + */ + +/** @defgroup DMA_LL_EF_Configuration Configuration + * @{ + */ +/** + * @brief Enable DMA channel. + * @rmtoll CCR EN LL_DMA_EnableChannel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_EN); +} + +/** + * @brief Disable DMA channel. + * @rmtoll CCR EN LL_DMA_DisableChannel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_EN); +} + +/** + * @brief Check if DMA channel is enabled or disabled. + * @rmtoll CCR EN LL_DMA_IsEnabledChannel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, + DMA_CCR_EN) == (DMA_CCR_EN)) ? 1UL : 0UL); +} + +/** + * @brief Configure all parameters link to DMA transfer. + * @rmtoll CCR DIR LL_DMA_ConfigTransfer\n + * CCR MEM2MEM LL_DMA_ConfigTransfer\n + * CCR CIRC LL_DMA_ConfigTransfer\n + * CCR PINC LL_DMA_ConfigTransfer\n + * CCR MINC LL_DMA_ConfigTransfer\n + * CCR PSIZE LL_DMA_ConfigTransfer\n + * CCR MSIZE LL_DMA_ConfigTransfer\n + * CCR PL LL_DMA_ConfigTransfer + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param Configuration This parameter must be a combination of all the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR + * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT + * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT + * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD + * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD + * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH + * @retval None + */ +__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, + DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL, + Configuration); +} + +/** + * @brief Set Data transfer direction (read from peripheral or from memory). + * @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n + * CCR MEM2MEM LL_DMA_SetDataTransferDirection + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param Direction This parameter can be one of the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, + DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction); +} + +/** + * @brief Get Data transfer direction (read from peripheral or from memory). + * @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n + * CCR MEM2MEM LL_DMA_GetDataTransferDirection + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + */ +__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, + DMA_CCR_DIR | DMA_CCR_MEM2MEM)); +} + +/** + * @brief Set DMA mode circular or normal. + * @note The circular buffer mode cannot be used if the memory-to-memory + * data transfer is configured on the selected Channel. + * @rmtoll CCR CIRC LL_DMA_SetMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_DMA_MODE_NORMAL + * @arg @ref LL_DMA_MODE_CIRCULAR + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_CIRC, + Mode); +} + +/** + * @brief Get DMA mode circular or normal. + * @rmtoll CCR CIRC LL_DMA_GetMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_MODE_NORMAL + * @arg @ref LL_DMA_MODE_CIRCULAR + */ +__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, + DMA_CCR_CIRC)); +} + +/** + * @brief Set Peripheral increment mode. + * @rmtoll CCR PINC LL_DMA_SetPeriphIncMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param PeriphOrM2MSrcIncMode This parameter can be one of the following values: + * @arg @ref LL_DMA_PERIPH_INCREMENT + * @arg @ref LL_DMA_PERIPH_NOINCREMENT + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PINC, + PeriphOrM2MSrcIncMode); +} + +/** + * @brief Get Peripheral increment mode. + * @rmtoll CCR PINC LL_DMA_GetPeriphIncMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_PERIPH_INCREMENT + * @arg @ref LL_DMA_PERIPH_NOINCREMENT + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, + DMA_CCR_PINC)); +} + +/** + * @brief Set Memory increment mode. + * @rmtoll CCR MINC LL_DMA_SetMemoryIncMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param MemoryOrM2MDstIncMode This parameter can be one of the following values: + * @arg @ref LL_DMA_MEMORY_INCREMENT + * @arg @ref LL_DMA_MEMORY_NOINCREMENT + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_MINC, + MemoryOrM2MDstIncMode); +} + +/** + * @brief Get Memory increment mode. + * @rmtoll CCR MINC LL_DMA_GetMemoryIncMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_MEMORY_INCREMENT + * @arg @ref LL_DMA_MEMORY_NOINCREMENT + */ +__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, + DMA_CCR_MINC)); +} + +/** + * @brief Set Peripheral size. + * @rmtoll CCR PSIZE LL_DMA_SetPeriphSize + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param PeriphOrM2MSrcDataSize This parameter can be one of the following values: + * @arg @ref LL_DMA_PDATAALIGN_BYTE + * @arg @ref LL_DMA_PDATAALIGN_HALFWORD + * @arg @ref LL_DMA_PDATAALIGN_WORD + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PSIZE, + PeriphOrM2MSrcDataSize); +} + +/** + * @brief Get Peripheral size. + * @rmtoll CCR PSIZE LL_DMA_GetPeriphSize + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_PDATAALIGN_BYTE + * @arg @ref LL_DMA_PDATAALIGN_HALFWORD + * @arg @ref LL_DMA_PDATAALIGN_WORD + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, + DMA_CCR_PSIZE)); +} + +/** + * @brief Set Memory size. + * @rmtoll CCR MSIZE LL_DMA_SetMemorySize + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param MemoryOrM2MDstDataSize This parameter can be one of the following values: + * @arg @ref LL_DMA_MDATAALIGN_BYTE + * @arg @ref LL_DMA_MDATAALIGN_HALFWORD + * @arg @ref LL_DMA_MDATAALIGN_WORD + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_MSIZE, + MemoryOrM2MDstDataSize); +} + +/** + * @brief Get Memory size. + * @rmtoll CCR MSIZE LL_DMA_GetMemorySize + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_MDATAALIGN_BYTE + * @arg @ref LL_DMA_MDATAALIGN_HALFWORD + * @arg @ref LL_DMA_MDATAALIGN_WORD + */ +__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, + DMA_CCR_MSIZE)); +} + +/** + * @brief Set Channel priority level. + * @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param Priority This parameter can be one of the following values: + * @arg @ref LL_DMA_PRIORITY_LOW + * @arg @ref LL_DMA_PRIORITY_MEDIUM + * @arg @ref LL_DMA_PRIORITY_HIGH + * @arg @ref LL_DMA_PRIORITY_VERYHIGH + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PL, + Priority); +} + +/** + * @brief Get Channel priority level. + * @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_PRIORITY_LOW + * @arg @ref LL_DMA_PRIORITY_MEDIUM + * @arg @ref LL_DMA_PRIORITY_HIGH + * @arg @ref LL_DMA_PRIORITY_VERYHIGH + */ +__STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, + DMA_CCR_PL)); +} + +/** + * @brief Set Number of data to transfer. + * @note This action has no effect if + * channel is enabled. + * @rmtoll CNDTR NDT LL_DMA_SetDataLength + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CNDTR, + DMA_CNDTR_NDT, NbData); +} + +/** + * @brief Get Number of data to transfer. + * @note Once the channel is enabled, the return value indicate the + * remaining bytes to be transmitted. + * @rmtoll CNDTR NDT LL_DMA_GetDataLength + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CNDTR, + DMA_CNDTR_NDT)); +} + +/** + * @brief Configure the Source and Destination addresses. + * @note This API must not be called when the DMA channel is enabled. + * @note Each peripheral using DMA provides an API to get directly the register address (LL_PPP_DMA_GetRegAddr). + * @rmtoll CPAR PA LL_DMA_ConfigAddresses\n + * CMAR MA LL_DMA_ConfigAddresses + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @param Direction This parameter can be one of the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + * @retval None + */ +__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress, + uint32_t DstAddress, uint32_t Direction) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + /* Direction Memory to Periph */ + if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) + { + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR, SrcAddress); + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR, DstAddress); + } + /* Direction Periph to Memory and Memory to Memory */ + else + { + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR, SrcAddress); + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR, DstAddress); + } +} + +/** + * @brief Set the Memory address. + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @note This API must not be called when the DMA channel is enabled. + * @rmtoll CMAR MA LL_DMA_SetMemoryAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR, MemoryAddress); +} + +/** + * @brief Set the Peripheral address. + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @note This API must not be called when the DMA channel is enabled. + * @rmtoll CPAR PA LL_DMA_SetPeriphAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR, PeriphAddress); +} + +/** + * @brief Get Memory address. + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @rmtoll CMAR MA LL_DMA_GetMemoryAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR)); +} + +/** + * @brief Get Peripheral address. + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @rmtoll CPAR PA LL_DMA_GetPeriphAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR)); +} + +/** + * @brief Set the Memory to Memory Source address. + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @note This API must not be called when the DMA channel is enabled. + * @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR, MemoryAddress); +} + +/** + * @brief Set the Memory to Memory Destination address. + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @note This API must not be called when the DMA channel is enabled. + * @rmtoll CMAR MA LL_DMA_SetM2MDstAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR, MemoryAddress); +} + +/** + * @brief Get the Memory to Memory Source address. + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR)); +} + +/** + * @brief Get the Memory to Memory Destination address. + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @rmtoll CMAR MA LL_DMA_GetM2MDstAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR)); +} + +#if defined(DMAMUX1) +/** + * @brief Set DMA request for DMA Channels on DMAMUX Channel x. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7. + * @rmtoll CxCR DMAREQ_ID LL_DMA_SetPeriphRequest + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param Request This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_MEM2MEM + * @arg @ref LL_DMAMUX_REQ_GENERATOR0 + * @arg @ref LL_DMAMUX_REQ_GENERATOR1 + * @arg @ref LL_DMAMUX_REQ_GENERATOR2 + * @arg @ref LL_DMAMUX_REQ_GENERATOR3 + * @arg @ref LL_DMAMUX_REQ_ADC1 + * @arg @ref LL_DMAMUX_REQ_ADC2 + * @arg @ref LL_DMAMUX_REQ_DAC1_CH1 + * @arg @ref LL_DMAMUX_REQ_DAC1_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM6_UP + * @arg @ref LL_DMAMUX_REQ_TIM7_UP + * @arg @ref LL_DMAMUX_REQ_SPI1_RX + * @arg @ref LL_DMAMUX_REQ_SPI1_TX + * @arg @ref LL_DMAMUX_REQ_SPI2_RX + * @arg @ref LL_DMAMUX_REQ_SPI2_TX + * @arg @ref LL_DMAMUX_REQ_SPI3_RX + * @arg @ref LL_DMAMUX_REQ_SPI3_TX + * @arg @ref LL_DMAMUX_REQ_I2C1_RX + * @arg @ref LL_DMAMUX_REQ_I2C1_TX + * @arg @ref LL_DMAMUX_REQ_I2C2_RX + * @arg @ref LL_DMAMUX_REQ_I2C2_TX + * @arg @ref LL_DMAMUX_REQ_I2C3_RX + * @arg @ref LL_DMAMUX_REQ_I2C3_TX + * @arg @ref LL_DMAMUX_REQ_I2C4_RX + * @arg @ref LL_DMAMUX_REQ_I2C4_TX + * @arg @ref LL_DMAMUX_REQ_USART1_RX + * @arg @ref LL_DMAMUX_REQ_USART1_TX + * @arg @ref LL_DMAMUX_REQ_USART2_RX + * @arg @ref LL_DMAMUX_REQ_USART2_TX + * @arg @ref LL_DMAMUX_REQ_USART3_RX + * @arg @ref LL_DMAMUX_REQ_USART3_TX + * @arg @ref LL_DMAMUX_REQ_UART4_RX + * @arg @ref LL_DMAMUX_REQ_UART4_TX + * @arg @ref LL_DMAMUX_REQ_UART5_RX + * @arg @ref LL_DMAMUX_REQ_UART5_TX + * @arg @ref LL_DMAMUX_REQ_LPUART1_RX + * @arg @ref LL_DMAMUX_REQ_LPUART1_TX + * @arg @ref LL_DMAMUX_REQ_SAI1_A + * @arg @ref LL_DMAMUX_REQ_SAI1_B + * @arg @ref LL_DMAMUX_REQ_SAI2_A + * @arg @ref LL_DMAMUX_REQ_SAI2_B + * @arg @ref LL_DMAMUX_REQ_OSPI1 + * @arg @ref LL_DMAMUX_REQ_OSPI2 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM1_UP + * @arg @ref LL_DMAMUX_REQ_TIM1_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM1_COM + * @arg @ref LL_DMAMUX_REQ_TIM8_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM8_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM8_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM8_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM8_UP + * @arg @ref LL_DMAMUX_REQ_TIM8_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM8_COM + * @arg @ref LL_DMAMUX_REQ_TIM2_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM2_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM2_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM2_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM2_UP + * @arg @ref LL_DMAMUX_REQ_TIM3_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM3_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM3_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM3_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM3_UP + * @arg @ref LL_DMAMUX_REQ_TIM3_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM4_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM4_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM4_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM4_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM4_UP + * @arg @ref LL_DMAMUX_REQ_TIM5_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM5_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM5_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM5_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM5_UP + * @arg @ref LL_DMAMUX_REQ_TIM5_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM15_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM15_UP + * @arg @ref LL_DMAMUX_REQ_TIM15_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM15_COM + * @arg @ref LL_DMAMUX_REQ_TIM16_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM16_UP + * @arg @ref LL_DMAMUX_REQ_TIM17_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM17_UP + * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT0 + * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT1 + * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT2 + * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT3 + * @arg @ref LL_DMAMUX_REQ_DCMI + * @arg @ref LL_DMAMUX_REQ_DCMI_PSSI + * @arg @ref LL_DMAMUX_REQ_AES_IN + * @arg @ref LL_DMAMUX_REQ_AES_OUT + * @arg @ref LL_DMAMUX_REQ_HASH_IN + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Request) +{ + uint32_t dmamux_ccr_offset = ((((uint32_t)DMAx ^ (uint32_t)DMA1) >> 10U) * 7U); + MODIFY_REG((DMAMUX1_Channel0 + Channel + dmamux_ccr_offset)->CCR, DMAMUX_CxCR_DMAREQ_ID, Request); +} + +/** + * @brief Get DMA request for DMA Channels on DMAMUX Channel x. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7. + * @rmtoll CxCR DMAREQ_ID LL_DMA_GetPeriphRequest + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_MEM2MEM + * @arg @ref LL_DMAMUX_REQ_GENERATOR0 + * @arg @ref LL_DMAMUX_REQ_GENERATOR1 + * @arg @ref LL_DMAMUX_REQ_GENERATOR2 + * @arg @ref LL_DMAMUX_REQ_GENERATOR3 + * @arg @ref LL_DMAMUX_REQ_ADC1 + * @arg @ref LL_DMAMUX_REQ_ADC2 + * @arg @ref LL_DMAMUX_REQ_DAC1_CH1 + * @arg @ref LL_DMAMUX_REQ_DAC1_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM6_UP + * @arg @ref LL_DMAMUX_REQ_TIM7_UP + * @arg @ref LL_DMAMUX_REQ_SPI1_RX + * @arg @ref LL_DMAMUX_REQ_SPI1_TX + * @arg @ref LL_DMAMUX_REQ_SPI2_RX + * @arg @ref LL_DMAMUX_REQ_SPI2_TX + * @arg @ref LL_DMAMUX_REQ_SPI3_RX + * @arg @ref LL_DMAMUX_REQ_SPI3_TX + * @arg @ref LL_DMAMUX_REQ_I2C1_RX + * @arg @ref LL_DMAMUX_REQ_I2C1_TX + * @arg @ref LL_DMAMUX_REQ_I2C2_RX + * @arg @ref LL_DMAMUX_REQ_I2C2_TX + * @arg @ref LL_DMAMUX_REQ_I2C3_RX + * @arg @ref LL_DMAMUX_REQ_I2C3_TX + * @arg @ref LL_DMAMUX_REQ_I2C4_RX + * @arg @ref LL_DMAMUX_REQ_I2C4_TX + * @arg @ref LL_DMAMUX_REQ_USART1_RX + * @arg @ref LL_DMAMUX_REQ_USART1_TX + * @arg @ref LL_DMAMUX_REQ_USART2_RX + * @arg @ref LL_DMAMUX_REQ_USART2_TX + * @arg @ref LL_DMAMUX_REQ_USART3_RX + * @arg @ref LL_DMAMUX_REQ_USART3_TX + * @arg @ref LL_DMAMUX_REQ_UART4_RX + * @arg @ref LL_DMAMUX_REQ_UART4_TX + * @arg @ref LL_DMAMUX_REQ_UART5_RX + * @arg @ref LL_DMAMUX_REQ_UART5_TX + * @arg @ref LL_DMAMUX_REQ_LPUART1_RX + * @arg @ref LL_DMAMUX_REQ_LPUART1_TX + * @arg @ref LL_DMAMUX_REQ_SAI1_A + * @arg @ref LL_DMAMUX_REQ_SAI1_B + * @arg @ref LL_DMAMUX_REQ_SAI2_A + * @arg @ref LL_DMAMUX_REQ_SAI2_B + * @arg @ref LL_DMAMUX_REQ_OSPI1 + * @arg @ref LL_DMAMUX_REQ_OSPI2 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM1_UP + * @arg @ref LL_DMAMUX_REQ_TIM1_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM1_COM + * @arg @ref LL_DMAMUX_REQ_TIM8_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM8_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM8_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM8_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM8_UP + * @arg @ref LL_DMAMUX_REQ_TIM8_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM8_COM + * @arg @ref LL_DMAMUX_REQ_TIM2_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM2_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM2_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM2_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM2_UP + * @arg @ref LL_DMAMUX_REQ_TIM3_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM3_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM3_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM3_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM3_UP + * @arg @ref LL_DMAMUX_REQ_TIM3_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM4_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM4_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM4_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM4_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM4_UP + * @arg @ref LL_DMAMUX_REQ_TIM5_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM5_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM5_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM5_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM5_UP + * @arg @ref LL_DMAMUX_REQ_TIM5_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM15_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM15_UP + * @arg @ref LL_DMAMUX_REQ_TIM15_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM15_COM + * @arg @ref LL_DMAMUX_REQ_TIM16_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM16_UP + * @arg @ref LL_DMAMUX_REQ_TIM17_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM17_UP + * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT0 + * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT1 + * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT2 + * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT3 + * @arg @ref LL_DMAMUX_REQ_DCMI + * @arg @ref LL_DMAMUX_REQ_DCMI_PSSI + * @arg @ref LL_DMAMUX_REQ_AES_IN + * @arg @ref LL_DMAMUX_REQ_AES_OUT + * @arg @ref LL_DMAMUX_REQ_HASH_IN + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dmamux_ccr_offset = ((((uint32_t)DMAx ^ (uint32_t)DMA1) >> 10U) * 7U); + return (READ_BIT((DMAMUX1_Channel0 + Channel + dmamux_ccr_offset)->CCR, DMAMUX_CxCR_DMAREQ_ID)); +} + +#else +/** + * @brief Set DMA request for DMA instance on Channel x. + * @note Please refer to Reference Manual to get the available mapping of Request value link to Channel Selection. + * @rmtoll CSELR C1S LL_DMA_SetPeriphRequest\n + * CSELR C2S LL_DMA_SetPeriphRequest\n + * CSELR C3S LL_DMA_SetPeriphRequest\n + * CSELR C4S LL_DMA_SetPeriphRequest\n + * CSELR C5S LL_DMA_SetPeriphRequest\n + * CSELR C6S LL_DMA_SetPeriphRequest\n + * CSELR C7S LL_DMA_SetPeriphRequest + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param PeriphRequest This parameter can be one of the following values: + * @arg @ref LL_DMA_REQUEST_0 + * @arg @ref LL_DMA_REQUEST_1 + * @arg @ref LL_DMA_REQUEST_2 + * @arg @ref LL_DMA_REQUEST_3 + * @arg @ref LL_DMA_REQUEST_4 + * @arg @ref LL_DMA_REQUEST_5 + * @arg @ref LL_DMA_REQUEST_6 + * @arg @ref LL_DMA_REQUEST_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphRequest) +{ + MODIFY_REG(((DMA_Request_TypeDef *)((uint32_t)((uint32_t)DMAx + DMA_CSELR_OFFSET)))->CSELR, + DMA_CSELR_C1S << ((Channel) * 4U), PeriphRequest << DMA_POSITION_CSELR_CXS); +} + +/** + * @brief Get DMA request for DMA instance on Channel x. + * @rmtoll CSELR C1S LL_DMA_GetPeriphRequest\n + * CSELR C2S LL_DMA_GetPeriphRequest\n + * CSELR C3S LL_DMA_GetPeriphRequest\n + * CSELR C4S LL_DMA_GetPeriphRequest\n + * CSELR C5S LL_DMA_GetPeriphRequest\n + * CSELR C6S LL_DMA_GetPeriphRequest\n + * CSELR C7S LL_DMA_GetPeriphRequest + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_REQUEST_0 + * @arg @ref LL_DMA_REQUEST_1 + * @arg @ref LL_DMA_REQUEST_2 + * @arg @ref LL_DMA_REQUEST_3 + * @arg @ref LL_DMA_REQUEST_4 + * @arg @ref LL_DMA_REQUEST_5 + * @arg @ref LL_DMA_REQUEST_6 + * @arg @ref LL_DMA_REQUEST_7 + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Request_TypeDef *)((uint32_t)((uint32_t)DMAx + DMA_CSELR_OFFSET)))->CSELR, + DMA_CSELR_C1S << ((Channel) * 4U)) >> DMA_POSITION_CSELR_CXS); +} + +#endif /* DMAMUX1 */ +/** + * @} + */ + +/** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Get Channel 1 global interrupt flag. + * @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 2 global interrupt flag. + * @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 3 global interrupt flag. + * @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 4 global interrupt flag. + * @rmtoll ISR GIF4 LL_DMA_IsActiveFlag_GI4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 5 global interrupt flag. + * @rmtoll ISR GIF5 LL_DMA_IsActiveFlag_GI5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 6 global interrupt flag. + * @rmtoll ISR GIF6 LL_DMA_IsActiveFlag_GI6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 7 global interrupt flag. + * @rmtoll ISR GIF7 LL_DMA_IsActiveFlag_GI7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 1 transfer complete flag. + * @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 2 transfer complete flag. + * @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 3 transfer complete flag. + * @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 4 transfer complete flag. + * @rmtoll ISR TCIF4 LL_DMA_IsActiveFlag_TC4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 5 transfer complete flag. + * @rmtoll ISR TCIF5 LL_DMA_IsActiveFlag_TC5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 6 transfer complete flag. + * @rmtoll ISR TCIF6 LL_DMA_IsActiveFlag_TC6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 7 transfer complete flag. + * @rmtoll ISR TCIF7 LL_DMA_IsActiveFlag_TC7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 1 half transfer flag. + * @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 2 half transfer flag. + * @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 3 half transfer flag. + * @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 4 half transfer flag. + * @rmtoll ISR HTIF4 LL_DMA_IsActiveFlag_HT4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 5 half transfer flag. + * @rmtoll ISR HTIF5 LL_DMA_IsActiveFlag_HT5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 6 half transfer flag. + * @rmtoll ISR HTIF6 LL_DMA_IsActiveFlag_HT6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 7 half transfer flag. + * @rmtoll ISR HTIF7 LL_DMA_IsActiveFlag_HT7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 1 transfer error flag. + * @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 2 transfer error flag. + * @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 3 transfer error flag. + * @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 4 transfer error flag. + * @rmtoll ISR TEIF4 LL_DMA_IsActiveFlag_TE4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 5 transfer error flag. + * @rmtoll ISR TEIF5 LL_DMA_IsActiveFlag_TE5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 6 transfer error flag. + * @rmtoll ISR TEIF6 LL_DMA_IsActiveFlag_TE6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 7 transfer error flag. + * @rmtoll ISR TEIF7 LL_DMA_IsActiveFlag_TE7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7)) ? 1UL : 0UL); +} + +/** + * @brief Clear Channel 1 global interrupt flag. + * @note Do not Clear Channel 1 global interrupt flag when the channel in ON. + Instead clear specific flags transfer complete, half transfer & transfer + error flag with LL_DMA_ClearFlag_TC1, LL_DMA_ClearFlag_HT1, + LL_DMA_ClearFlag_TE1. bug 2.4.1/2.5.1 in Product Errata Sheet. + * @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1); +} + +/** + * @brief Clear Channel 2 global interrupt flag. + * @note Do not Clear Channel 2 global interrupt flag when the channel in ON. + Instead clear specific flags transfer complete, half transfer & transfer + error flag with LL_DMA_ClearFlag_TC2, LL_DMA_ClearFlag_HT2, + LL_DMA_ClearFlag_TE2. bug id 2.4.1/2.5.1 in Product Errata Sheet. + * @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2); +} + +/** + * @brief Clear Channel 3 global interrupt flag. + * @note Do not Clear Channel 3 global interrupt flag when the channel in ON. + Instead clear specific flags transfer complete, half transfer & transfer + error flag with LL_DMA_ClearFlag_TC3, LL_DMA_ClearFlag_HT3, + LL_DMA_ClearFlag_TE3. bug id 2.4.1/2.5.1 in Product Errata Sheet. + * @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3); +} + +/** + * @brief Clear Channel 4 global interrupt flag. + * @note Do not Clear Channel 4 global interrupt flag when the channel in ON. + Instead clear specific flags transfer complete, half transfer & transfer + error flag with LL_DMA_ClearFlag_TC4, LL_DMA_ClearFlag_HT4, + LL_DMA_ClearFlag_TE4. bug id 2.4.1/2.5.1 in Product Errata Sheet. + * @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4); +} + +/** + * @brief Clear Channel 5 global interrupt flag. + * @note Do not Clear Channel 5 global interrupt flag when the channel in ON. + Instead clear specific flags transfer complete, half transfer & transfer + error flag with LL_DMA_ClearFlag_TC5, LL_DMA_ClearFlag_HT5, + LL_DMA_ClearFlag_TE5. bug id 2.4.1/2.5.1 in Product Errata Sheet. + * @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5); +} + +/** + * @brief Clear Channel 6 global interrupt flag. + * @note Do not Clear Channel 6 global interrupt flag when the channel in ON. + Instead clear specific flags transfer complete, half transfer & transfer + error flag with LL_DMA_ClearFlag_TC6, LL_DMA_ClearFlag_HT6, + LL_DMA_ClearFlag_TE6. bug id 2.4.1/2.5.1 in Product Errata Sheet. + * @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6); +} + +/** + * @brief Clear Channel 7 global interrupt flag. + * @note Do not Clear Channel 7 global interrupt flag when the channel in ON. + Instead clear specific flags transfer complete, half transfer & transfer + error flag with LL_DMA_ClearFlag_TC7, LL_DMA_ClearFlag_HT7, + LL_DMA_ClearFlag_TE7. bug id 2.4.1/2.5.1 in Product Errata Sheet. + * @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7); +} + +/** + * @brief Clear Channel 1 transfer complete flag. + * @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1); +} + +/** + * @brief Clear Channel 2 transfer complete flag. + * @rmtoll IFCR CTCIF2 LL_DMA_ClearFlag_TC2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2); +} + +/** + * @brief Clear Channel 3 transfer complete flag. + * @rmtoll IFCR CTCIF3 LL_DMA_ClearFlag_TC3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3); +} + +/** + * @brief Clear Channel 4 transfer complete flag. + * @rmtoll IFCR CTCIF4 LL_DMA_ClearFlag_TC4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4); +} + +/** + * @brief Clear Channel 5 transfer complete flag. + * @rmtoll IFCR CTCIF5 LL_DMA_ClearFlag_TC5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5); +} + +/** + * @brief Clear Channel 6 transfer complete flag. + * @rmtoll IFCR CTCIF6 LL_DMA_ClearFlag_TC6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6); +} + +/** + * @brief Clear Channel 7 transfer complete flag. + * @rmtoll IFCR CTCIF7 LL_DMA_ClearFlag_TC7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7); +} + +/** + * @brief Clear Channel 1 half transfer flag. + * @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1); +} + +/** + * @brief Clear Channel 2 half transfer flag. + * @rmtoll IFCR CHTIF2 LL_DMA_ClearFlag_HT2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2); +} + +/** + * @brief Clear Channel 3 half transfer flag. + * @rmtoll IFCR CHTIF3 LL_DMA_ClearFlag_HT3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3); +} + +/** + * @brief Clear Channel 4 half transfer flag. + * @rmtoll IFCR CHTIF4 LL_DMA_ClearFlag_HT4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4); +} + +/** + * @brief Clear Channel 5 half transfer flag. + * @rmtoll IFCR CHTIF5 LL_DMA_ClearFlag_HT5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5); +} + +/** + * @brief Clear Channel 6 half transfer flag. + * @rmtoll IFCR CHTIF6 LL_DMA_ClearFlag_HT6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6); +} + +/** + * @brief Clear Channel 7 half transfer flag. + * @rmtoll IFCR CHTIF7 LL_DMA_ClearFlag_HT7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7); +} + +/** + * @brief Clear Channel 1 transfer error flag. + * @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1); +} + +/** + * @brief Clear Channel 2 transfer error flag. + * @rmtoll IFCR CTEIF2 LL_DMA_ClearFlag_TE2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2); +} + +/** + * @brief Clear Channel 3 transfer error flag. + * @rmtoll IFCR CTEIF3 LL_DMA_ClearFlag_TE3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3); +} + +/** + * @brief Clear Channel 4 transfer error flag. + * @rmtoll IFCR CTEIF4 LL_DMA_ClearFlag_TE4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4); +} + +/** + * @brief Clear Channel 5 transfer error flag. + * @rmtoll IFCR CTEIF5 LL_DMA_ClearFlag_TE5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5); +} + +/** + * @brief Clear Channel 6 transfer error flag. + * @rmtoll IFCR CTEIF6 LL_DMA_ClearFlag_TE6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6); +} + +/** + * @brief Clear Channel 7 transfer error flag. + * @rmtoll IFCR CTEIF7 LL_DMA_ClearFlag_TE7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7); +} + +/** + * @} + */ + +/** @defgroup DMA_LL_EF_IT_Management IT_Management + * @{ + */ +/** + * @brief Enable Transfer complete interrupt. + * @rmtoll CCR TCIE LL_DMA_EnableIT_TC + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE); +} + +/** + * @brief Enable Half transfer interrupt. + * @rmtoll CCR HTIE LL_DMA_EnableIT_HT + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE); +} + +/** + * @brief Enable Transfer error interrupt. + * @rmtoll CCR TEIE LL_DMA_EnableIT_TE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TEIE); +} + +/** + * @brief Disable Transfer complete interrupt. + * @rmtoll CCR TCIE LL_DMA_DisableIT_TC + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE); +} + +/** + * @brief Disable Half transfer interrupt. + * @rmtoll CCR HTIE LL_DMA_DisableIT_HT + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE); +} + +/** + * @brief Disable Transfer error interrupt. + * @rmtoll CCR TEIE LL_DMA_DisableIT_TE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TEIE); +} + +/** + * @brief Check if Transfer complete Interrupt is enabled. + * @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, + DMA_CCR_TCIE) == (DMA_CCR_TCIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if Half transfer Interrupt is enabled. + * @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, + DMA_CCR_HTIE) == (DMA_CCR_HTIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if Transfer error Interrupt is enabled. + * @rmtoll CCR TEIE LL_DMA_IsEnabledIT_TE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, + DMA_CCR_TEIE) == (DMA_CCR_TEIE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions + * @{ + */ +ErrorStatus LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct); +ErrorStatus LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel); +void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* DMA1 || DMA2 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32L4xx_LL_DMA_H */ diff --git a/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_dmamux.h b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_dmamux.h new file mode 100644 index 0000000..6de6976 --- /dev/null +++ b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_dmamux.h @@ -0,0 +1,1981 @@ +/** + ****************************************************************************** + * @file stm32l4xx_ll_dmamux.h + * @author MCD Application Team + * @brief Header file of DMAMUX LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32L4xx_LL_DMAMUX_H +#define STM32L4xx_LL_DMAMUX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx.h" + +/** @addtogroup STM32L4xx_LL_Driver + * @{ + */ + +#if defined (DMAMUX1) + +/** @defgroup DMAMUX_LL DMAMUX + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup DMAMUX_LL_Private_Constants DMAMUX Private Constants + * @{ + */ +/* Define used to get DMAMUX CCR register size */ +#define DMAMUX_CCR_SIZE 0x00000004UL + +/* Define used to get DMAMUX RGCR register size */ +#define DMAMUX_RGCR_SIZE 0x00000004UL +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup DMAMUX_LL_Exported_Constants DMAMUX Exported Constants + * @{ + */ +/** @defgroup DMAMUX_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_DMAMUX_WriteReg function + * @{ + */ +#define LL_DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0 /*!< Synchronization Event Overrun Flag Channel 0 */ +#define LL_DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1 /*!< Synchronization Event Overrun Flag Channel 1 */ +#define LL_DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2 /*!< Synchronization Event Overrun Flag Channel 2 */ +#define LL_DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3 /*!< Synchronization Event Overrun Flag Channel 3 */ +#define LL_DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4 /*!< Synchronization Event Overrun Flag Channel 4 */ +#define LL_DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5 /*!< Synchronization Event Overrun Flag Channel 5 */ +#define LL_DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6 /*!< Synchronization Event Overrun Flag Channel 6 */ +#define LL_DMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7 /*!< Synchronization Event Overrun Flag Channel 7 */ +#define LL_DMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8 /*!< Synchronization Event Overrun Flag Channel 8 */ +#define LL_DMAMUX_CFR_CSOF9 DMAMUX_CFR_CSOF9 /*!< Synchronization Event Overrun Flag Channel 9 */ +#define LL_DMAMUX_CFR_CSOF10 DMAMUX_CFR_CSOF10 /*!< Synchronization Event Overrun Flag Channel 10 */ +#define LL_DMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11 /*!< Synchronization Event Overrun Flag Channel 11 */ +#define LL_DMAMUX_CFR_CSOF12 DMAMUX_CFR_CSOF12 /*!< Synchronization Event Overrun Flag Channel 12 */ +#define LL_DMAMUX_CFR_CSOF13 DMAMUX_CFR_CSOF13 /*!< Synchronization Event Overrun Flag Channel 13 */ +#define LL_DMAMUX_RGCFR_RGCOF0 DMAMUX_RGCFR_COF0 /*!< Request Generator 0 Trigger Event Overrun Flag */ +#define LL_DMAMUX_RGCFR_RGCOF1 DMAMUX_RGCFR_COF1 /*!< Request Generator 1 Trigger Event Overrun Flag */ +#define LL_DMAMUX_RGCFR_RGCOF2 DMAMUX_RGCFR_COF2 /*!< Request Generator 2 Trigger Event Overrun Flag */ +#define LL_DMAMUX_RGCFR_RGCOF3 DMAMUX_RGCFR_COF3 /*!< Request Generator 3 Trigger Event Overrun Flag */ +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_DMAMUX_ReadReg function + * @{ + */ +#define LL_DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0 /*!< Synchronization Event Overrun Flag Channel 0 */ +#define LL_DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1 /*!< Synchronization Event Overrun Flag Channel 1 */ +#define LL_DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2 /*!< Synchronization Event Overrun Flag Channel 2 */ +#define LL_DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3 /*!< Synchronization Event Overrun Flag Channel 3 */ +#define LL_DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4 /*!< Synchronization Event Overrun Flag Channel 4 */ +#define LL_DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5 /*!< Synchronization Event Overrun Flag Channel 5 */ +#define LL_DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6 /*!< Synchronization Event Overrun Flag Channel 6 */ +#define LL_DMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7 /*!< Synchronization Event Overrun Flag Channel 7 */ +#define LL_DMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8 /*!< Synchronization Event Overrun Flag Channel 8 */ +#define LL_DMAMUX_CSR_SOF9 DMAMUX_CSR_SOF9 /*!< Synchronization Event Overrun Flag Channel 9 */ +#define LL_DMAMUX_CSR_SOF10 DMAMUX_CSR_SOF10 /*!< Synchronization Event Overrun Flag Channel 10 */ +#define LL_DMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11 /*!< Synchronization Event Overrun Flag Channel 11 */ +#define LL_DMAMUX_CSR_SOF12 DMAMUX_CSR_SOF12 /*!< Synchronization Event Overrun Flag Channel 12 */ +#define LL_DMAMUX_CSR_SOF13 DMAMUX_CSR_SOF13 /*!< Synchronization Event Overrun Flag Channel 13 */ +#define LL_DMAMUX_RGSR_RGOF0 DMAMUX_RGSR_OF0 /*!< Request Generator 0 Trigger Event Overrun Flag */ +#define LL_DMAMUX_RGSR_RGOF1 DMAMUX_RGSR_OF1 /*!< Request Generator 1 Trigger Event Overrun Flag */ +#define LL_DMAMUX_RGSR_RGOF2 DMAMUX_RGSR_OF2 /*!< Request Generator 2 Trigger Event Overrun Flag */ +#define LL_DMAMUX_RGSR_RGOF3 DMAMUX_RGSR_OF3 /*!< Request Generator 3 Trigger Event Overrun Flag */ +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMAMUX_WriteReg functions + * @{ + */ +#define LL_DMAMUX_CCR_SOIE DMAMUX_CxCR_SOIE /*!< Synchronization Event Overrun Interrupt */ +#define LL_DMAMUX_RGCR_RGOIE DMAMUX_RGxCR_OIE /*!< Request Generation Trigger Event Overrun Interrupt */ +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_REQUEST Transfer request + * @{ + */ +#define LL_DMAMUX_REQ_MEM2MEM 0U /*!< Memory to memory transfer */ + +#define LL_DMAMUX_REQ_GENERATOR0 1U /*!< DMAMUX request generator 0 */ +#define LL_DMAMUX_REQ_GENERATOR1 2U /*!< DMAMUX request generator 1 */ +#define LL_DMAMUX_REQ_GENERATOR2 3U /*!< DMAMUX request generator 2 */ +#define LL_DMAMUX_REQ_GENERATOR3 4U /*!< DMAMUX request generator 3 */ + +#define LL_DMAMUX_REQ_ADC1 5U /*!< DMAMUX ADC1 request */ + +#if defined (ADC2) + +#define LL_DMAMUX_REQ_ADC2 6U /*!< DMAMUX ADC1 request */ + +#define LL_DMAMUX_REQ_DAC1_CH1 7U /*!< DMAMUX DAC1 CH1 request */ +#define LL_DMAMUX_REQ_DAC1_CH2 8U /*!< DMAMUX DAC1 CH2 request */ + +#define LL_DMAMUX_REQ_TIM6_UP 9U /*!< DMAMUX TIM6 UP request */ +#define LL_DMAMUX_REQ_TIM7_UP 10U /*!< DMAMUX TIM7 UP request */ + +#define LL_DMAMUX_REQ_SPI1_RX 11U /*!< DMAMUX SPI1 RX request */ +#define LL_DMAMUX_REQ_SPI1_TX 12U /*!< DMAMUX SPI1 TX request */ +#define LL_DMAMUX_REQ_SPI2_RX 13U /*!< DMAMUX SPI2 RX request */ +#define LL_DMAMUX_REQ_SPI2_TX 14U /*!< DMAMUX SPI2 TX request */ +#define LL_DMAMUX_REQ_SPI3_RX 15U /*!< DMAMUX SPI3 RX request */ +#define LL_DMAMUX_REQ_SPI3_TX 16U /*!< DMAMUX SPI3 TX request */ + +#define LL_DMAMUX_REQ_I2C1_RX 17U /*!< DMAMUX I2C1 RX request */ +#define LL_DMAMUX_REQ_I2C1_TX 18U /*!< DMAMUX I2C1 TX request */ +#define LL_DMAMUX_REQ_I2C2_RX 19U /*!< DMAMUX I2C2 RX request */ +#define LL_DMAMUX_REQ_I2C2_TX 20U /*!< DMAMUX I2C2 TX request */ +#define LL_DMAMUX_REQ_I2C3_RX 21U /*!< DMAMUX I2C3 RX request */ +#define LL_DMAMUX_REQ_I2C3_TX 22U /*!< DMAMUX I2C3 TX request */ +#define LL_DMAMUX_REQ_I2C4_RX 23U /*!< DMAMUX I2C4 RX request */ +#define LL_DMAMUX_REQ_I2C4_TX 24U /*!< DMAMUX I2C4 TX request */ + +#define LL_DMAMUX_REQ_USART1_RX 25U /*!< DMAMUX USART1 RX request */ +#define LL_DMAMUX_REQ_USART1_TX 26U /*!< DMAMUX USART1 TX request */ +#define LL_DMAMUX_REQ_USART2_RX 27U /*!< DMAMUX USART2 RX request */ +#define LL_DMAMUX_REQ_USART2_TX 28U /*!< DMAMUX USART2 TX request */ +#define LL_DMAMUX_REQ_USART3_RX 29U /*!< DMAMUX USART3 RX request */ +#define LL_DMAMUX_REQ_USART3_TX 30U /*!< DMAMUX USART3 TX request */ + +#define LL_DMAMUX_REQ_UART4_RX 31U /*!< DMAMUX UART4 RX request */ +#define LL_DMAMUX_REQ_UART4_TX 32U /*!< DMAMUX UART4 TX request */ +#define LL_DMAMUX_REQ_UART5_RX 33U /*!< DMAMUX UART5 RX request */ +#define LL_DMAMUX_REQ_UART5_TX 34U /*!< DMAMUX UART5 TX request */ + +#define LL_DMAMUX_REQ_LPUART1_RX 35U /*!< DMAMUX LPUART1 RX request */ +#define LL_DMAMUX_REQ_LPUART1_TX 36U /*!< DMAMUX LPUART1 TX request */ + +#define LL_DMAMUX_REQ_SAI1_A 37U /*!< DMAMUX SAI1 A request */ +#define LL_DMAMUX_REQ_SAI1_B 38U /*!< DMAMUX SAI1 B request */ +#define LL_DMAMUX_REQ_SAI2_A 39U /*!< DMAMUX SAI2 A request */ +#define LL_DMAMUX_REQ_SAI2_B 40U /*!< DMAMUX SAI2 B request */ + +#define LL_DMAMUX_REQ_OSPI1 41U /*!< DMAMUX OCTOSPI1 request */ +#define LL_DMAMUX_REQ_OSPI2 42U /*!< DMAMUX OCTOSPI2 request */ + +#define LL_DMAMUX_REQ_TIM1_CH1 43U /*!< DMAMUX TIM1 CH1 request */ +#define LL_DMAMUX_REQ_TIM1_CH2 44U /*!< DMAMUX TIM1 CH2 request */ +#define LL_DMAMUX_REQ_TIM1_CH3 45U /*!< DMAMUX TIM1 CH3 request */ +#define LL_DMAMUX_REQ_TIM1_CH4 46U /*!< DMAMUX TIM1 CH4 request */ +#define LL_DMAMUX_REQ_TIM1_UP 47U /*!< DMAMUX TIM1 UP request */ +#define LL_DMAMUX_REQ_TIM1_TRIG 48U /*!< DMAMUX TIM1 TRIG request */ +#define LL_DMAMUX_REQ_TIM1_COM 49U /*!< DMAMUX TIM1 COM request */ + +#define LL_DMAMUX_REQ_TIM8_CH1 50U /*!< DMAMUX TIM8 CH1 request */ +#define LL_DMAMUX_REQ_TIM8_CH2 51U /*!< DMAMUX TIM8 CH2 request */ +#define LL_DMAMUX_REQ_TIM8_CH3 52U /*!< DMAMUX TIM8 CH3 request */ +#define LL_DMAMUX_REQ_TIM8_CH4 53U /*!< DMAMUX TIM8 CH4 request */ +#define LL_DMAMUX_REQ_TIM8_UP 54U /*!< DMAMUX TIM8 UP request */ +#define LL_DMAMUX_REQ_TIM8_TRIG 55U /*!< DMAMUX TIM8 TRIG request */ +#define LL_DMAMUX_REQ_TIM8_COM 56U /*!< DMAMUX TIM8 COM request */ + +#define LL_DMAMUX_REQ_TIM2_CH1 57U /*!< DMAMUX TIM2 CH1 request */ +#define LL_DMAMUX_REQ_TIM2_CH2 58U /*!< DMAMUX TIM2 CH2 request */ +#define LL_DMAMUX_REQ_TIM2_CH3 59U /*!< DMAMUX TIM2 CH3 request */ +#define LL_DMAMUX_REQ_TIM2_CH4 60U /*!< DMAMUX TIM2 CH4 request */ +#define LL_DMAMUX_REQ_TIM2_UP 61U /*!< DMAMUX TIM2 UP request */ + +#define LL_DMAMUX_REQ_TIM3_CH1 62U /*!< DMAMUX TIM3 CH1 request */ +#define LL_DMAMUX_REQ_TIM3_CH2 63U /*!< DMAMUX TIM3 CH2 request */ +#define LL_DMAMUX_REQ_TIM3_CH3 64U /*!< DMAMUX TIM3 CH3 request */ +#define LL_DMAMUX_REQ_TIM3_CH4 65U /*!< DMAMUX TIM3 CH4 request */ +#define LL_DMAMUX_REQ_TIM3_UP 66U /*!< DMAMUX TIM3 UP request */ +#define LL_DMAMUX_REQ_TIM3_TRIG 67U /*!< DMAMUX TIM3 TRIG request */ + +#define LL_DMAMUX_REQ_TIM4_CH1 68U /*!< DMAMUX TIM4 CH1 request */ +#define LL_DMAMUX_REQ_TIM4_CH2 69U /*!< DMAMUX TIM4 CH2 request */ +#define LL_DMAMUX_REQ_TIM4_CH3 70U /*!< DMAMUX TIM4 CH3 request */ +#define LL_DMAMUX_REQ_TIM4_CH4 71U /*!< DMAMUX TIM4 CH4 request */ +#define LL_DMAMUX_REQ_TIM4_UP 72U /*!< DMAMUX TIM4 UP request */ + +#define LL_DMAMUX_REQ_TIM5_CH1 73U /*!< DMAMUX TIM5 CH1 request */ +#define LL_DMAMUX_REQ_TIM5_CH2 74U /*!< DMAMUX TIM5 CH2 request */ +#define LL_DMAMUX_REQ_TIM5_CH3 75U /*!< DMAMUX TIM5 CH3 request */ +#define LL_DMAMUX_REQ_TIM5_CH4 76U /*!< DMAMUX TIM5 CH4 request */ +#define LL_DMAMUX_REQ_TIM5_UP 77U /*!< DMAMUX TIM5 UP request */ +#define LL_DMAMUX_REQ_TIM5_TRIG 78U /*!< DMAMUX TIM5 TRIG request */ +#define LL_DMAMUX_REQ_TIM15_CH1 79U /*!< DMAMUX TIM15 CH1 request */ +#define LL_DMAMUX_REQ_TIM15_UP 80U /*!< DMAMUX TIM15 UP request */ +#define LL_DMAMUX_REQ_TIM15_TRIG 81U /*!< DMAMUX TIM15 TRIG request */ +#define LL_DMAMUX_REQ_TIM15_COM 82U /*!< DMAMUX TIM15 COM request */ + +#define LL_DMAMUX_REQ_TIM16_CH1 83U /*!< DMAMUX TIM16 CH1 request */ +#define LL_DMAMUX_REQ_TIM16_UP 84U /*!< DMAMUX TIM16 UP request */ +#define LL_DMAMUX_REQ_TIM17_CH1 85U /*!< DMAMUX TIM17 CH1 request */ +#define LL_DMAMUX_REQ_TIM17_UP 86U /*!< DMAMUX TIM17 UP request */ + +#define LL_DMAMUX_REQ_DFSDM1_FLT0 87U /*!< DMAMUX DFSDM1_FLT0 request */ +#define LL_DMAMUX_REQ_DFSDM1_FLT1 88U /*!< DMAMUX DFSDM1_FLT1 request */ +#define LL_DMAMUX_REQ_DFSDM1_FLT2 89U /*!< DMAMUX DFSDM1_FLT2 request */ +#define LL_DMAMUX_REQ_DFSDM1_FLT3 90U /*!< DMAMUX DFSDM1_FLT3 request */ + +#define LL_DMAMUX_REQ_DCMI 91U /*!< DMAMUX DCMI request */ +#define LL_DMAMUX_REQ_DCMI_PSSI 91U /*!< DMAMUX PSSI request */ + +#define LL_DMAMUX_REQ_AES_IN 92U /*!< DMAMUX AES_IN request */ +#define LL_DMAMUX_REQ_AES_OUT 93U /*!< DMAMUX AES_OUT request */ + +#define LL_DMAMUX_REQ_HASH_IN 94U /*!< DMAMUX HASH_IN request */ + +#else + +#define LL_DMAMUX_REQ_DAC1_CH1 6U /*!< DMAMUX DAC1 CH1 request */ +#define LL_DMAMUX_REQ_DAC1_CH2 7U /*!< DMAMUX DAC1 CH2 request */ + +#define LL_DMAMUX_REQ_TIM6_UP 8U /*!< DMAMUX TIM6 UP request */ +#define LL_DMAMUX_REQ_TIM7_UP 9U /*!< DMAMUX TIM7 UP request */ + +#define LL_DMAMUX_REQ_SPI1_RX 10U /*!< DMAMUX SPI1 RX request */ +#define LL_DMAMUX_REQ_SPI1_TX 11U /*!< DMAMUX SPI1 TX request */ +#define LL_DMAMUX_REQ_SPI2_RX 12U /*!< DMAMUX SPI2 RX request */ +#define LL_DMAMUX_REQ_SPI2_TX 13U /*!< DMAMUX SPI2 TX request */ +#define LL_DMAMUX_REQ_SPI3_RX 14U /*!< DMAMUX SPI3 RX request */ +#define LL_DMAMUX_REQ_SPI3_TX 15U /*!< DMAMUX SPI3 TX request */ + +#define LL_DMAMUX_REQ_I2C1_RX 16U /*!< DMAMUX I2C1 RX request */ +#define LL_DMAMUX_REQ_I2C1_TX 17U /*!< DMAMUX I2C1 TX request */ +#define LL_DMAMUX_REQ_I2C2_RX 18U /*!< DMAMUX I2C2 RX request */ +#define LL_DMAMUX_REQ_I2C2_TX 19U /*!< DMAMUX I2C2 TX request */ +#define LL_DMAMUX_REQ_I2C3_RX 20U /*!< DMAMUX I2C3 RX request */ +#define LL_DMAMUX_REQ_I2C3_TX 21U /*!< DMAMUX I2C3 TX request */ +#define LL_DMAMUX_REQ_I2C4_RX 22U /*!< DMAMUX I2C4 RX request */ +#define LL_DMAMUX_REQ_I2C4_TX 23U /*!< DMAMUX I2C4 TX request */ + +#define LL_DMAMUX_REQ_USART1_RX 24U /*!< DMAMUX USART1 RX request */ +#define LL_DMAMUX_REQ_USART1_TX 25U /*!< DMAMUX USART1 TX request */ +#define LL_DMAMUX_REQ_USART2_RX 26U /*!< DMAMUX USART2 RX request */ +#define LL_DMAMUX_REQ_USART2_TX 27U /*!< DMAMUX USART2 TX request */ +#define LL_DMAMUX_REQ_USART3_RX 28U /*!< DMAMUX USART3 RX request */ +#define LL_DMAMUX_REQ_USART3_TX 29U /*!< DMAMUX USART3 TX request */ + +#define LL_DMAMUX_REQ_UART4_RX 30U /*!< DMAMUX UART4 RX request */ +#define LL_DMAMUX_REQ_UART4_TX 31U /*!< DMAMUX UART4 TX request */ +#define LL_DMAMUX_REQ_UART5_RX 32U /*!< DMAMUX UART5 RX request */ +#define LL_DMAMUX_REQ_UART5_TX 33U /*!< DMAMUX UART5 TX request */ + +#define LL_DMAMUX_REQ_LPUART1_RX 34U /*!< DMAMUX LPUART1 RX request */ +#define LL_DMAMUX_REQ_LPUART1_TX 35U /*!< DMAMUX LPUART1 TX request */ + +#define LL_DMAMUX_REQ_SAI1_A 36U /*!< DMAMUX SAI1 A request */ +#define LL_DMAMUX_REQ_SAI1_B 37U /*!< DMAMUX SAI1 B request */ +#define LL_DMAMUX_REQ_SAI2_A 38U /*!< DMAMUX SAI2 A request */ +#define LL_DMAMUX_REQ_SAI2_B 39U /*!< DMAMUX SAI2 B request */ + +#define LL_DMAMUX_REQ_OSPI1 40U /*!< DMAMUX OCTOSPI1 request */ +#define LL_DMAMUX_REQ_OSPI2 41U /*!< DMAMUX OCTOSPI2 request */ + +#define LL_DMAMUX_REQ_TIM1_CH1 42U /*!< DMAMUX TIM1 CH1 request */ +#define LL_DMAMUX_REQ_TIM1_CH2 43U /*!< DMAMUX TIM1 CH2 request */ +#define LL_DMAMUX_REQ_TIM1_CH3 44U /*!< DMAMUX TIM1 CH3 request */ +#define LL_DMAMUX_REQ_TIM1_CH4 45U /*!< DMAMUX TIM1 CH4 request */ +#define LL_DMAMUX_REQ_TIM1_UP 46U /*!< DMAMUX TIM1 UP request */ +#define LL_DMAMUX_REQ_TIM1_TRIG 47U /*!< DMAMUX TIM1 TRIG request */ +#define LL_DMAMUX_REQ_TIM1_COM 48U /*!< DMAMUX TIM1 COM request */ + +#define LL_DMAMUX_REQ_TIM8_CH1 49U /*!< DMAMUX TIM8 CH1 request */ +#define LL_DMAMUX_REQ_TIM8_CH2 50U /*!< DMAMUX TIM8 CH2 request */ +#define LL_DMAMUX_REQ_TIM8_CH3 51U /*!< DMAMUX TIM8 CH3 request */ +#define LL_DMAMUX_REQ_TIM8_CH4 52U /*!< DMAMUX TIM8 CH4 request */ +#define LL_DMAMUX_REQ_TIM8_UP 53U /*!< DMAMUX TIM8 UP request */ +#define LL_DMAMUX_REQ_TIM8_TRIG 54U /*!< DMAMUX TIM8 TRIG request */ +#define LL_DMAMUX_REQ_TIM8_COM 55U /*!< DMAMUX TIM8 COM request */ + +#define LL_DMAMUX_REQ_TIM2_CH1 56U /*!< DMAMUX TIM2 CH1 request */ +#define LL_DMAMUX_REQ_TIM2_CH2 57U /*!< DMAMUX TIM2 CH2 request */ +#define LL_DMAMUX_REQ_TIM2_CH3 58U /*!< DMAMUX TIM2 CH3 request */ +#define LL_DMAMUX_REQ_TIM2_CH4 59U /*!< DMAMUX TIM2 CH4 request */ +#define LL_DMAMUX_REQ_TIM2_UP 60U /*!< DMAMUX TIM2 UP request */ + +#define LL_DMAMUX_REQ_TIM3_CH1 61U /*!< DMAMUX TIM3 CH1 request */ +#define LL_DMAMUX_REQ_TIM3_CH2 62U /*!< DMAMUX TIM3 CH2 request */ +#define LL_DMAMUX_REQ_TIM3_CH3 63U /*!< DMAMUX TIM3 CH3 request */ +#define LL_DMAMUX_REQ_TIM3_CH4 64U /*!< DMAMUX TIM3 CH4 request */ +#define LL_DMAMUX_REQ_TIM3_UP 65U /*!< DMAMUX TIM3 UP request */ +#define LL_DMAMUX_REQ_TIM3_TRIG 66U /*!< DMAMUX TIM3 TRIG request */ + +#define LL_DMAMUX_REQ_TIM4_CH1 67U /*!< DMAMUX TIM4 CH1 request */ +#define LL_DMAMUX_REQ_TIM4_CH2 68U /*!< DMAMUX TIM4 CH2 request */ +#define LL_DMAMUX_REQ_TIM4_CH3 69U /*!< DMAMUX TIM4 CH3 request */ +#define LL_DMAMUX_REQ_TIM4_CH4 70U /*!< DMAMUX TIM4 CH4 request */ +#define LL_DMAMUX_REQ_TIM4_UP 71U /*!< DMAMUX TIM4 UP request */ + +#define LL_DMAMUX_REQ_TIM5_CH1 72U /*!< DMAMUX TIM5 CH1 request */ +#define LL_DMAMUX_REQ_TIM5_CH2 73U /*!< DMAMUX TIM5 CH2 request */ +#define LL_DMAMUX_REQ_TIM5_CH3 74U /*!< DMAMUX TIM5 CH3 request */ +#define LL_DMAMUX_REQ_TIM5_CH4 75U /*!< DMAMUX TIM5 CH4 request */ +#define LL_DMAMUX_REQ_TIM5_UP 76U /*!< DMAMUX TIM5 UP request */ +#define LL_DMAMUX_REQ_TIM5_TRIG 77U /*!< DMAMUX TIM5 TRIG request */ +#define LL_DMAMUX_REQ_TIM15_CH1 78U /*!< DMAMUX TIM15 CH1 request */ +#define LL_DMAMUX_REQ_TIM15_UP 79U /*!< DMAMUX TIM15 UP request */ +#define LL_DMAMUX_REQ_TIM15_TRIG 80U /*!< DMAMUX TIM15 TRIG request */ +#define LL_DMAMUX_REQ_TIM15_COM 81U /*!< DMAMUX TIM15 COM request */ + +#define LL_DMAMUX_REQ_TIM16_CH1 82U /*!< DMAMUX TIM16 CH1 request */ +#define LL_DMAMUX_REQ_TIM16_UP 83U /*!< DMAMUX TIM16 UP request */ +#define LL_DMAMUX_REQ_TIM17_CH1 84U /*!< DMAMUX TIM17 CH1 request */ +#define LL_DMAMUX_REQ_TIM17_UP 85U /*!< DMAMUX TIM17 UP request */ + +#define LL_DMAMUX_REQ_DFSDM1_FLT0 86U /*!< DMAMUX DFSDM1_FLT0 request */ +#define LL_DMAMUX_REQ_DFSDM1_FLT1 87U /*!< DMAMUX DFSDM1_FLT1 request */ +#define LL_DMAMUX_REQ_DFSDM1_FLT2 88U /*!< DMAMUX DFSDM1_FLT2 request */ +#define LL_DMAMUX_REQ_DFSDM1_FLT3 89U /*!< DMAMUX DFSDM1_FLT3 request */ + +#define LL_DMAMUX_REQ_DCMI 90U /*!< DMAMUX DCMI request */ + +#define LL_DMAMUX_REQ_AES_IN 91U /*!< DMAMUX AES_IN request */ +#define LL_DMAMUX_REQ_AES_OUT 92U /*!< DMAMUX AES_OUT request */ + +#define LL_DMAMUX_REQ_HASH_IN 93U /*!< DMAMUX HASH_IN request */ + +#endif + +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_CHANNEL DMAMUX Channel + * @{ + */ +#define LL_DMAMUX_CHANNEL_0 0x00000000U /*!< DMAMUX Channel 0 connected to DMA1 Channel 1 */ +#define LL_DMAMUX_CHANNEL_1 0x00000001U /*!< DMAMUX Channel 1 connected to DMA1 Channel 2 */ +#define LL_DMAMUX_CHANNEL_2 0x00000002U /*!< DMAMUX Channel 2 connected to DMA1 Channel 3 */ +#define LL_DMAMUX_CHANNEL_3 0x00000003U /*!< DMAMUX Channel 3 connected to DMA1 Channel 4 */ +#define LL_DMAMUX_CHANNEL_4 0x00000004U /*!< DMAMUX Channel 4 connected to DMA1 Channel 5 */ +#define LL_DMAMUX_CHANNEL_5 0x00000005U /*!< DMAMUX Channel 5 connected to DMA1 Channel 6 */ +#define LL_DMAMUX_CHANNEL_6 0x00000006U /*!< DMAMUX Channel 6 connected to DMA1 Channel 7 */ +#define LL_DMAMUX_CHANNEL_7 0x00000007U /*!< DMAMUX Channel 7 connected to DMA2 Channel 1 */ +#define LL_DMAMUX_CHANNEL_8 0x00000008U /*!< DMAMUX Channel 8 connected to DMA2 Channel 2 */ +#define LL_DMAMUX_CHANNEL_9 0x00000009U /*!< DMAMUX Channel 9 connected to DMA2 Channel 3 */ +#define LL_DMAMUX_CHANNEL_10 0x0000000AU /*!< DMAMUX Channel 10 connected to DMA2 Channel 4 */ +#define LL_DMAMUX_CHANNEL_11 0x0000000BU /*!< DMAMUX Channel 11 connected to DMA2 Channel 5 */ +#define LL_DMAMUX_CHANNEL_12 0x0000000CU /*!< DMAMUX Channel 12 connected to DMA2 Channel 6 */ +#define LL_DMAMUX_CHANNEL_13 0x0000000DU /*!< DMAMUX Channel 13 connected to DMA2 Channel 7 */ +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_SYNC_NO Synchronization Signal Polarity + * @{ + */ +#define LL_DMAMUX_SYNC_NO_EVENT 0x00000000U /*!< All requests are blocked */ +#define LL_DMAMUX_SYNC_POL_RISING DMAMUX_CxCR_SPOL_0 /*!< Synchronization on event on rising edge */ +#define LL_DMAMUX_SYNC_POL_FALLING DMAMUX_CxCR_SPOL_1 /*!< Synchronization on event on falling edge */ +#define LL_DMAMUX_SYNC_POL_RISING_FALLING (DMAMUX_CxCR_SPOL_0 | DMAMUX_CxCR_SPOL_1) /*!< Synchronization on event on rising and falling edge */ +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_SYNC_EVT Synchronization Signal Event + * @{ + */ +#define LL_DMAMUX_SYNC_EXTI_LINE0 0x00000000U /*!< Synchronization signal from EXTI Line0 */ +#define LL_DMAMUX_SYNC_EXTI_LINE1 DMAMUX_CxCR_SYNC_ID_0 /*!< Synchronization signal from EXTI Line1 */ +#define LL_DMAMUX_SYNC_EXTI_LINE2 DMAMUX_CxCR_SYNC_ID_1 /*!< Synchronization signal from EXTI Line2 */ +#define LL_DMAMUX_SYNC_EXTI_LINE3 (DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line3 */ +#define LL_DMAMUX_SYNC_EXTI_LINE4 DMAMUX_CxCR_SYNC_ID_2 /*!< Synchronization signal from EXTI Line4 */ +#define LL_DMAMUX_SYNC_EXTI_LINE5 (DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line5 */ +#define LL_DMAMUX_SYNC_EXTI_LINE6 (DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1) /*!< Synchronization signal from EXTI Line6 */ +#define LL_DMAMUX_SYNC_EXTI_LINE7 (DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line7 */ +#define LL_DMAMUX_SYNC_EXTI_LINE8 DMAMUX_CxCR_SYNC_ID_3 /*!< Synchronization signal from EXTI Line8 */ +#define LL_DMAMUX_SYNC_EXTI_LINE9 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line9 */ +#define LL_DMAMUX_SYNC_EXTI_LINE10 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_1) /*!< Synchronization signal from EXTI Line10 */ +#define LL_DMAMUX_SYNC_EXTI_LINE11 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line11 */ +#define LL_DMAMUX_SYNC_EXTI_LINE12 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2) /*!< Synchronization signal from EXTI Line12 */ +#define LL_DMAMUX_SYNC_EXTI_LINE13 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line13 */ +#define LL_DMAMUX_SYNC_EXTI_LINE14 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1) /*!< Synchronization signal from EXTI Line14 */ +#define LL_DMAMUX_SYNC_EXTI_LINE15 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line15 */ +#define LL_DMAMUX_SYNC_DMAMUX_CH0 DMAMUX_CxCR_SYNC_ID_4 /*!< Synchronization signal from DMAMUX channel0 Event */ +#define LL_DMAMUX_SYNC_DMAMUX_CH1 (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from DMAMUX channel1 Event */ +#define LL_DMAMUX_SYNC_DMAMUX_CH2 (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_1) /*!< Synchronization signal from DMAMUX channel2 Event */ +#define LL_DMAMUX_SYNC_DMAMUX_CH3 (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from DMAMUX channel3 Event */ +#define LL_DMAMUX_SYNC_LPTIM1_OUT (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_2) /*!< Synchronization signal from LPTIM1 Output */ +#define LL_DMAMUX_SYNC_LPTIM2_OUT (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from LPTIM2 Output */ +#define LL_DMAMUX_SYNC_DSI_TE (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1) /*!< Synchronization signal from DSI Tearing Effect */ +#define LL_DMAMUX_SYNC_DSI_REFRESH_END (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from DSI End of Refresh */ +#define LL_DMAMUX_SYNC_DMA2D_TX_END (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_3) /*!< Synchronization signal from DMA2D End of Transfer */ +#define LL_DMAMUX_SYNC_LTDC_LINE_IT (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from LTDC Line Interrupt */ +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_REQUEST_GENERATOR Request Generator Channel + * @{ + */ +#define LL_DMAMUX_REQ_GEN_0 0x00000000U +#define LL_DMAMUX_REQ_GEN_1 0x00000001U +#define LL_DMAMUX_REQ_GEN_2 0x00000002U +#define LL_DMAMUX_REQ_GEN_3 0x00000003U +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_REQUEST_GEN_POLARITY External Request Signal Generation Polarity + * @{ + */ +#define LL_DMAMUX_REQ_GEN_NO_EVENT 0x00000000U /*!< No external DMA request generation */ +#define LL_DMAMUX_REQ_GEN_POL_RISING DMAMUX_RGxCR_GPOL_0 /*!< External DMA request generation on event on rising edge */ +#define LL_DMAMUX_REQ_GEN_POL_FALLING DMAMUX_RGxCR_GPOL_1 /*!< External DMA request generation on event on falling edge */ +#define LL_DMAMUX_REQ_GEN_POL_RISING_FALLING (DMAMUX_RGxCR_GPOL_0 | DMAMUX_RGxCR_GPOL_1) /*!< External DMA request generation on rising and falling edge */ +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_REQUEST_GEN External Request Signal Generation + * @{ + */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE0 0x00000000U /*!< Request signal generation from EXTI Line0 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE1 DMAMUX_RGxCR_SIG_ID_0 /*!< Request signal generation from EXTI Line1 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE2 DMAMUX_RGxCR_SIG_ID_1 /*!< Request signal generation from EXTI Line2 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE3 (DMAMUX_RGxCR_SIG_ID_1 |DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line3 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE4 DMAMUX_RGxCR_SIG_ID_2 /*!< Request signal generation from EXTI Line4 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE5 (DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line5 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE6 (DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1) /*!< Request signal generation from EXTI Line6 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE7 (DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line7 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE8 DMAMUX_RGxCR_SIG_ID_3 /*!< Request signal generation from EXTI Line8 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE9 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line9 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE10 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_1) /*!< Request signal generation from EXTI Line10 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE11 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line11 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE12 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2) /*!< Request signal generation from EXTI Line12 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE13 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line13 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE14 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1) /*!< Request signal generation from EXTI Line14 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE15 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line15 */ +#define LL_DMAMUX_REQ_GEN_DMAMUX_CH0 DMAMUX_RGxCR_SIG_ID_4 /*!< Request signal generation from DMAMUX channel0 Event */ +#define LL_DMAMUX_REQ_GEN_DMAMUX_CH1 (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from DMAMUX channel1 Event */ +#define LL_DMAMUX_REQ_GEN_DMAMUX_CH2 (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_1) /*!< Request signal generation from DMAMUX channel2 Event */ +#define LL_DMAMUX_REQ_GEN_DMAMUX_CH3 (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from DMAMUX channel3 Event */ +#define LL_DMAMUX_REQ_GEN_LPTIM1_OUT (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_2) /*!< Request signal generation from LPTIM1 Output */ +#define LL_DMAMUX_REQ_GEN_LPTIM2_OUT (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from LPTIM2 Output */ +#define LL_DMAMUX_REQ_GEN_DSI_TE (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1) /*!< Request signal generation from DSI Tearing Effect */ +#define LL_DMAMUX_REQ_GEN_DSI_REFRESH_END (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from DSI End of Refresh */ +#define LL_DMAMUX_REQ_GEN_DMA2D_TX_END (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_3) /*!< Request signal generation from DMA2D End of Transfer */ +#define LL_DMAMUX_REQ_GEN_LTDC_LINE_IT (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from LTDC Line Interrupt */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup DMAMUX_LL_Exported_Macros DMAMUX Exported Macros + * @{ + */ + +/** @defgroup DMAMUX_LL_EM_WRITE_READ Common Write and read registers macros + * @{ + */ +/** + * @brief Write a value in DMAMUX register + * @param __INSTANCE__ DMAMUX Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_DMAMUX_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in DMAMUX register + * @param __INSTANCE__ DMAMUX Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_DMAMUX_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup DMAMUX_LL_Exported_Functions DMAMUX Exported Functions + * @{ + */ + +/** @defgroup DMAMUX_LL_EF_Configuration Configuration + * @{ + */ +/** + * @brief Set DMAMUX request ID for DMAMUX Channel x. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7. + * @rmtoll CxCR DMAREQ_ID LL_DMAMUX_SetRequestID + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @param Request This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_MEM2MEM + * @arg @ref LL_DMAMUX_REQ_GENERATOR0 + * @arg @ref LL_DMAMUX_REQ_GENERATOR1 + * @arg @ref LL_DMAMUX_REQ_GENERATOR2 + * @arg @ref LL_DMAMUX_REQ_GENERATOR3 + * @arg @ref LL_DMAMUX_REQ_ADC1 + * @arg @ref LL_DMAMUX_REQ_DAC1_CH1 + * @arg @ref LL_DMAMUX_REQ_DAC1_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM6_UP + * @arg @ref LL_DMAMUX_REQ_TIM7_UP + * @arg @ref LL_DMAMUX_REQ_SPI1_RX + * @arg @ref LL_DMAMUX_REQ_SPI1_TX + * @arg @ref LL_DMAMUX_REQ_SPI2_RX + * @arg @ref LL_DMAMUX_REQ_SPI2_TX + * @arg @ref LL_DMAMUX_REQ_SPI3_RX + * @arg @ref LL_DMAMUX_REQ_SPI3_TX + * @arg @ref LL_DMAMUX_REQ_I2C1_RX + * @arg @ref LL_DMAMUX_REQ_I2C1_TX + * @arg @ref LL_DMAMUX_REQ_I2C2_RX + * @arg @ref LL_DMAMUX_REQ_I2C2_TX + * @arg @ref LL_DMAMUX_REQ_I2C3_RX + * @arg @ref LL_DMAMUX_REQ_I2C3_TX + * @arg @ref LL_DMAMUX_REQ_I2C4_RX + * @arg @ref LL_DMAMUX_REQ_I2C4_TX + * @arg @ref LL_DMAMUX_REQ_USART1_RX + * @arg @ref LL_DMAMUX_REQ_USART1_TX + * @arg @ref LL_DMAMUX_REQ_USART2_RX + * @arg @ref LL_DMAMUX_REQ_USART2_TX + * @arg @ref LL_DMAMUX_REQ_USART3_RX + * @arg @ref LL_DMAMUX_REQ_USART3_TX + * @arg @ref LL_DMAMUX_REQ_UART4_RX + * @arg @ref LL_DMAMUX_REQ_UART4_TX + * @arg @ref LL_DMAMUX_REQ_UART5_RX + * @arg @ref LL_DMAMUX_REQ_UART5_TX + * @arg @ref LL_DMAMUX_REQ_LPUART1_RX + * @arg @ref LL_DMAMUX_REQ_LPUART1_TX + * @arg @ref LL_DMAMUX_REQ_SAI1_A + * @arg @ref LL_DMAMUX_REQ_SAI1_B + * @arg @ref LL_DMAMUX_REQ_SAI2_A + * @arg @ref LL_DMAMUX_REQ_SAI2_B + * @arg @ref LL_DMAMUX_REQ_OSPI1 + * @arg @ref LL_DMAMUX_REQ_OSPI2 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM1_UP + * @arg @ref LL_DMAMUX_REQ_TIM1_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM1_COM + * @arg @ref LL_DMAMUX_REQ_TIM8_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM8_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM8_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM8_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM8_UP + * @arg @ref LL_DMAMUX_REQ_TIM8_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM8_COM + * @arg @ref LL_DMAMUX_REQ_TIM2_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM2_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM2_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM2_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM2_UP + * @arg @ref LL_DMAMUX_REQ_TIM3_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM3_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM3_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM3_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM3_UP + * @arg @ref LL_DMAMUX_REQ_TIM3_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM4_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM4_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM4_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM4_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM4_UP + * @arg @ref LL_DMAMUX_REQ_TIM5_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM5_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM5_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM5_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM5_UP + * @arg @ref LL_DMAMUX_REQ_TIM5_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM15_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM15_UP + * @arg @ref LL_DMAMUX_REQ_TIM15_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM15_COM + * @arg @ref LL_DMAMUX_REQ_TIM16_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM16_UP + * @arg @ref LL_DMAMUX_REQ_TIM17_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM17_UP + * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT0 + * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT1 + * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT2 + * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT3 + * @arg @ref LL_DMAMUX_REQ_DCMI + * @arg @ref LL_DMAMUX_REQ_AES_IN + * @arg @ref LL_DMAMUX_REQ_AES_OUT + * @arg @ref LL_DMAMUX_REQ_HASH_IN + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_SetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Request) +{ + (void)(DMAMUXx); + MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_DMAREQ_ID, Request); +} + +/** + * @brief Get DMAMUX request ID for DMAMUX Channel x. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7. + * @rmtoll CxCR DMAREQ_ID LL_DMAMUX_GetRequestID + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_MEM2MEM + * @arg @ref LL_DMAMUX_REQ_GENERATOR0 + * @arg @ref LL_DMAMUX_REQ_GENERATOR1 + * @arg @ref LL_DMAMUX_REQ_GENERATOR2 + * @arg @ref LL_DMAMUX_REQ_GENERATOR3 + * @arg @ref LL_DMAMUX_REQ_ADC1 + * @arg @ref LL_DMAMUX_REQ_DAC1_CH1 + * @arg @ref LL_DMAMUX_REQ_DAC1_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM6_UP + * @arg @ref LL_DMAMUX_REQ_TIM7_UP + * @arg @ref LL_DMAMUX_REQ_SPI1_RX + * @arg @ref LL_DMAMUX_REQ_SPI1_TX + * @arg @ref LL_DMAMUX_REQ_SPI2_RX + * @arg @ref LL_DMAMUX_REQ_SPI2_TX + * @arg @ref LL_DMAMUX_REQ_SPI3_RX + * @arg @ref LL_DMAMUX_REQ_SPI3_TX + * @arg @ref LL_DMAMUX_REQ_I2C1_RX + * @arg @ref LL_DMAMUX_REQ_I2C1_TX + * @arg @ref LL_DMAMUX_REQ_I2C2_RX + * @arg @ref LL_DMAMUX_REQ_I2C2_TX + * @arg @ref LL_DMAMUX_REQ_I2C3_RX + * @arg @ref LL_DMAMUX_REQ_I2C3_TX + * @arg @ref LL_DMAMUX_REQ_I2C4_RX + * @arg @ref LL_DMAMUX_REQ_I2C4_TX + * @arg @ref LL_DMAMUX_REQ_USART1_RX + * @arg @ref LL_DMAMUX_REQ_USART1_TX + * @arg @ref LL_DMAMUX_REQ_USART2_RX + * @arg @ref LL_DMAMUX_REQ_USART2_TX + * @arg @ref LL_DMAMUX_REQ_USART3_RX + * @arg @ref LL_DMAMUX_REQ_USART3_TX + * @arg @ref LL_DMAMUX_REQ_UART4_RX + * @arg @ref LL_DMAMUX_REQ_UART4_TX + * @arg @ref LL_DMAMUX_REQ_UART5_RX + * @arg @ref LL_DMAMUX_REQ_UART5_TX + * @arg @ref LL_DMAMUX_REQ_LPUART1_RX + * @arg @ref LL_DMAMUX_REQ_LPUART1_TX + * @arg @ref LL_DMAMUX_REQ_SAI1_A + * @arg @ref LL_DMAMUX_REQ_SAI1_B + * @arg @ref LL_DMAMUX_REQ_SAI2_A + * @arg @ref LL_DMAMUX_REQ_SAI2_B + * @arg @ref LL_DMAMUX_REQ_OSPI1 + * @arg @ref LL_DMAMUX_REQ_OSPI2 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM1_UP + * @arg @ref LL_DMAMUX_REQ_TIM1_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM1_COM + * @arg @ref LL_DMAMUX_REQ_TIM8_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM8_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM8_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM8_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM8_UP + * @arg @ref LL_DMAMUX_REQ_TIM8_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM8_COM + * @arg @ref LL_DMAMUX_REQ_TIM2_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM2_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM2_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM2_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM2_UP + * @arg @ref LL_DMAMUX_REQ_TIM3_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM3_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM3_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM3_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM3_UP + * @arg @ref LL_DMAMUX_REQ_TIM3_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM4_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM4_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM4_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM4_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM4_UP + * @arg @ref LL_DMAMUX_REQ_TIM5_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM5_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM5_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM5_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM5_UP + * @arg @ref LL_DMAMUX_REQ_TIM5_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM15_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM15_UP + * @arg @ref LL_DMAMUX_REQ_TIM15_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM15_COM + * @arg @ref LL_DMAMUX_REQ_TIM16_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM16_UP + * @arg @ref LL_DMAMUX_REQ_TIM17_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM17_UP + * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT0 + * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT1 + * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT2 + * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT3 + * @arg @ref LL_DMAMUX_REQ_DCMI + * @arg @ref LL_DMAMUX_REQ_AES_IN + * @arg @ref LL_DMAMUX_REQ_AES_OUT + * @arg @ref LL_DMAMUX_REQ_HASH_IN + */ +__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + (void)(DMAMUXx); + return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_DMAREQ_ID)); +} + +/** + * @brief Set the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event. + * @rmtoll CxCR NBREQ LL_DMAMUX_SetSyncRequestNb + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @param RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32. + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_SetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t RequestNb) +{ + (void)(DMAMUXx); + MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_NBREQ, ((RequestNb - 1U) << DMAMUX_CxCR_NBREQ_Pos)); +} + +/** + * @brief Get the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event. + * @rmtoll CxCR NBREQ LL_DMAMUX_GetSyncRequestNb + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @retval Between Min_Data = 1 and Max_Data = 32 + */ +__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + (void)(DMAMUXx); + return (uint32_t)(((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_NBREQ)) >> DMAMUX_CxCR_NBREQ_Pos) + 1U); +} + +/** + * @brief Set the polarity of the signal on which the DMA request is synchronized. + * @rmtoll CxCR SPOL LL_DMAMUX_SetSyncPolarity + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_SYNC_NO_EVENT + * @arg @ref LL_DMAMUX_SYNC_POL_RISING + * @arg @ref LL_DMAMUX_SYNC_POL_FALLING + * @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_SetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Polarity) +{ + (void)(DMAMUXx); + MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SPOL, Polarity); +} + +/** + * @brief Get the polarity of the signal on which the DMA request is synchronized. + * @rmtoll CxCR SPOL LL_DMAMUX_GetSyncPolarity + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMAMUX_SYNC_NO_EVENT + * @arg @ref LL_DMAMUX_SYNC_POL_RISING + * @arg @ref LL_DMAMUX_SYNC_POL_FALLING + * @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING + */ +__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + (void)(DMAMUXx); + return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SPOL)); +} + +/** + * @brief Enable the Event Generation on DMAMUX channel x. + * @rmtoll CxCR EGE LL_DMAMUX_EnableEventGeneration + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_EnableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + (void)(DMAMUXx); + SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE); +} + +/** + * @brief Disable the Event Generation on DMAMUX channel x. + * @rmtoll CxCR EGE LL_DMAMUX_DisableEventGeneration + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_DisableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + (void)(DMAMUXx); + CLEAR_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE); +} + +/** + * @brief Check if the Event Generation on DMAMUX channel x is enabled or disabled. + * @rmtoll CxCR EGE LL_DMAMUX_IsEnabledEventGeneration + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + (void)(DMAMUXx); + return ((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE) == (DMAMUX_CxCR_EGE))? 1UL : 0UL); +} + +/** + * @brief Enable the synchronization mode. + * @rmtoll CxCR SE LL_DMAMUX_EnableSync + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_EnableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + (void)(DMAMUXx); + SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE); +} + +/** + * @brief Disable the synchronization mode. + * @rmtoll CxCR SE LL_DMAMUX_DisableSync + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_DisableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + (void)(DMAMUXx); + CLEAR_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE); +} + +/** + * @brief Check if the synchronization mode is enabled or disabled. + * @rmtoll CxCR SE LL_DMAMUX_IsEnabledSync + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + (void)(DMAMUXx); + return ((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE) == (DMAMUX_CxCR_SE))? 1UL : 0UL); +} + +/** + * @brief Set DMAMUX synchronization ID on DMAMUX Channel x. + * @rmtoll CxCR SYNC_ID LL_DMAMUX_SetSyncID + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @param SyncID This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE0 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE1 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE2 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE3 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE4 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE5 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE6 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE7 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE8 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE9 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE10 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE11 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE12 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE13 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE14 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE15 + * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH0 + * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH1 + * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH2 + * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH3 + * @arg @ref LL_DMAMUX_SYNC_LPTIM1_OUT + * @arg @ref LL_DMAMUX_SYNC_LPTIM2_OUT + * @arg @ref LL_DMAMUX_SYNC_DSI_TE + * @arg @ref LL_DMAMUX_SYNC_DSI_REFRESH_END + * @arg @ref LL_DMAMUX_SYNC_DMA2D_TX_END + * @arg @ref LL_DMAMUX_SYNC_LTDC_LINE_IT + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_SetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t SyncID) +{ + (void)(DMAMUXx); + MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SYNC_ID, SyncID); +} + +/** + * @brief Get DMAMUX synchronization ID on DMAMUX Channel x. + * @rmtoll CxCR SYNC_ID LL_DMAMUX_GetSyncID + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE0 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE1 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE2 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE3 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE4 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE5 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE6 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE7 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE8 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE9 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE10 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE11 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE12 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE13 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE14 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE15 + * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH0 + * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH1 + * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH2 + * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH3 + * @arg @ref LL_DMAMUX_SYNC_LPTIM1_OUT + * @arg @ref LL_DMAMUX_SYNC_LPTIM2_OUT + * @arg @ref LL_DMAMUX_SYNC_DSI_TE + * @arg @ref LL_DMAMUX_SYNC_DSI_REFRESH_END + * @arg @ref LL_DMAMUX_SYNC_DMA2D_TX_END + * @arg @ref LL_DMAMUX_SYNC_LTDC_LINE_IT + */ +__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + (void)(DMAMUXx); + return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SYNC_ID)); +} + +/** + * @brief Enable the Request Generator. + * @rmtoll RGxCR GE LL_DMAMUX_EnableRequestGen + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_EnableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + (void)(DMAMUXx); + SET_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE); +} + +/** + * @brief Disable the Request Generator. + * @rmtoll RGxCR GE LL_DMAMUX_DisableRequestGen + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_DisableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + (void)(DMAMUXx); + CLEAR_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE); +} + +/** + * @brief Check if the Request Generator is enabled or disabled. + * @rmtoll RGxCR GE LL_DMAMUX_IsEnabledRequestGen + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + (void)(DMAMUXx); + return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE) == (DMAMUX_RGxCR_GE))? 1UL : 0UL); +} + +/** + * @brief Set the polarity of the signal on which the DMA request is generated. + * @rmtoll RGxCR GPOL LL_DMAMUX_SetRequestGenPolarity + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_NO_EVENT + * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING + * @arg @ref LL_DMAMUX_REQ_GEN_POL_FALLING + * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_SetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t Polarity) +{ + (void)(DMAMUXx); + MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GPOL, Polarity); +} + +/** + * @brief Get the polarity of the signal on which the DMA request is generated. + * @rmtoll RGxCR GPOL LL_DMAMUX_GetRequestGenPolarity + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_NO_EVENT + * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING + * @arg @ref LL_DMAMUX_REQ_GEN_POL_FALLING + * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING + */ +__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + (void)(DMAMUXx); + return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GPOL)); +} + +/** + * @brief Set the number of DMA request that will be autorized after a generation event. + * @note This field can only be written when Generator is disabled. + * @rmtoll RGxCR GNBREQ LL_DMAMUX_SetGenRequestNb + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @param RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32. + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_SetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestNb) +{ + (void)(DMAMUXx); + MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GNBREQ, (RequestNb - 1U) << DMAMUX_RGxCR_GNBREQ_Pos); +} + +/** + * @brief Get the number of DMA request that will be autorized after a generation event. + * @rmtoll RGxCR GNBREQ LL_DMAMUX_GetGenRequestNb + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @retval Between Min_Data = 1 and Max_Data = 32 + */ +__STATIC_INLINE uint32_t LL_DMAMUX_GetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + (void)(DMAMUXx); + return (uint32_t)((READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GNBREQ) >> DMAMUX_RGxCR_GNBREQ_Pos) + 1U); +} + +/** + * @brief Set DMAMUX external Request Signal ID on DMAMUX Request Generation Trigger Event Channel x. + * @rmtoll RGxCR SIG_ID LL_DMAMUX_SetRequestSignalID + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @param RequestSignalID This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE0 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE1 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE2 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE3 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE4 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE5 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE6 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE7 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE8 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE9 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE10 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE11 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE12 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE13 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE14 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE15 + * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH0 + * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH1 + * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH2 + * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH3 + * @arg @ref LL_DMAMUX_REQ_GEN_LPTIM1_OUT + * @arg @ref LL_DMAMUX_REQ_GEN_LPTIM2_OUT + * @arg @ref LL_DMAMUX_REQ_GEN_DSI_TE + * @arg @ref LL_DMAMUX_REQ_GEN_DSI_REFRESH_END + * @arg @ref LL_DMAMUX_REQ_GEN_DMA2D_TX_END + * @arg @ref LL_DMAMUX_REQ_GEN_LTDC_LINE_IT + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_SetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestSignalID) +{ + (void)(DMAMUXx); + MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_SIG_ID, RequestSignalID); +} + +/** + * @brief Get DMAMUX external Request Signal ID set on DMAMUX Channel x. + * @rmtoll RGxCR SIG_ID LL_DMAMUX_GetRequestSignalID + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE0 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE1 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE2 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE3 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE4 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE5 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE6 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE7 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE8 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE9 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE10 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE11 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE12 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE13 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE14 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE15 + * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH0 + * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH1 + * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH2 + * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH3 + * @arg @ref LL_DMAMUX_REQ_GEN_LPTIM1_OUT + * @arg @ref LL_DMAMUX_REQ_GEN_LPTIM2_OUT + * @arg @ref LL_DMAMUX_REQ_GEN_DSI_TE + * @arg @ref LL_DMAMUX_REQ_GEN_DSI_REFRESH_END + * @arg @ref LL_DMAMUX_REQ_GEN_DMA2D_TX_END + * @arg @ref LL_DMAMUX_REQ_GEN_LTDC_LINE_IT + */ +__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + (void)(DMAMUXx); + return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_SIG_ID)); +} + +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Get Synchronization Event Overrun Flag Channel 0. + * @rmtoll CSR SOF0 LL_DMAMUX_IsActiveFlag_SO0 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF0) == (DMAMUX_CSR_SOF0)) ? 1UL : 0UL); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 1. + * @rmtoll CSR SOF1 LL_DMAMUX_IsActiveFlag_SO1 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF1) == (DMAMUX_CSR_SOF1)) ? 1UL : 0UL); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 2. + * @rmtoll CSR SOF2 LL_DMAMUX_IsActiveFlag_SO2 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF2) == (DMAMUX_CSR_SOF2)) ? 1UL : 0UL); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 3. + * @rmtoll CSR SOF3 LL_DMAMUX_IsActiveFlag_SO3 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF3) == (DMAMUX_CSR_SOF3)) ? 1UL : 0UL); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 4. + * @rmtoll CSR SOF4 LL_DMAMUX_IsActiveFlag_SO4 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF4) == (DMAMUX_CSR_SOF4)) ? 1UL : 0UL); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 5. + * @rmtoll CSR SOF5 LL_DMAMUX_IsActiveFlag_SO5 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF5) == (DMAMUX_CSR_SOF5)) ? 1UL : 0UL); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 6. + * @rmtoll CSR SOF6 LL_DMAMUX_IsActiveFlag_SO6 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF6) == (DMAMUX_CSR_SOF6)) ? 1UL : 0UL); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 7. + * @rmtoll CSR SOF7 LL_DMAMUX_IsActiveFlag_SO7 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF7) == (DMAMUX_CSR_SOF7)) ? 1UL : 0UL); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 8. + * @rmtoll CSR SOF8 LL_DMAMUX_IsActiveFlag_SO8 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF8) == (DMAMUX_CSR_SOF8)) ? 1UL : 0UL); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 9. + * @rmtoll CSR SOF9 LL_DMAMUX_IsActiveFlag_SO9 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF9) == (DMAMUX_CSR_SOF9)) ? 1UL : 0UL); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 10. + * @rmtoll CSR SOF10 LL_DMAMUX_IsActiveFlag_SO10 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF10) == (DMAMUX_CSR_SOF10)) ? 1UL : 0UL); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 11. + * @rmtoll CSR SOF11 LL_DMAMUX_IsActiveFlag_SO11 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF11) == (DMAMUX_CSR_SOF11)) ? 1UL : 0UL); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 12. + * @rmtoll CSR SOF12 LL_DMAMUX_IsActiveFlag_SO12 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF12) == (DMAMUX_CSR_SOF12)) ? 1UL : 0UL); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 13. + * @rmtoll CSR SOF13 LL_DMAMUX_IsActiveFlag_SO13 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF13) == (DMAMUX_CSR_SOF13)) ? 1UL : 0UL); +} + +/** + * @brief Get Request Generator 0 Trigger Event Overrun Flag. + * @rmtoll RGSR OF0 LL_DMAMUX_IsActiveFlag_RGO0 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF0) == (DMAMUX_RGSR_OF0)) ? 1UL : 0UL); +} + +/** + * @brief Get Request Generator 1 Trigger Event Overrun Flag. + * @rmtoll RGSR OF1 LL_DMAMUX_IsActiveFlag_RGO1 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF1) == (DMAMUX_RGSR_OF1)) ? 1UL : 0UL); +} + +/** + * @brief Get Request Generator 2 Trigger Event Overrun Flag. + * @rmtoll RGSR OF2 LL_DMAMUX_IsActiveFlag_RGO2 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF2) == (DMAMUX_RGSR_OF2)) ? 1UL : 0UL); +} + +/** + * @brief Get Request Generator 3 Trigger Event Overrun Flag. + * @rmtoll RGSR OF3 LL_DMAMUX_IsActiveFlag_RGO3 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF3) == (DMAMUX_RGSR_OF3)) ? 1UL : 0UL); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 0. + * @rmtoll CFR CSOF0 LL_DMAMUX_ClearFlag_SO0 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO0(DMAMUX_Channel_TypeDef * DMAMUXx) +{ + (void)(DMAMUXx); + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF0); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 1. + * @rmtoll CFR CSOF1 LL_DMAMUX_ClearFlag_SO1 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF1); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 2. + * @rmtoll CFR CSOF2 LL_DMAMUX_ClearFlag_SO2 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF2); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 3. + * @rmtoll CFR CSOF3 LL_DMAMUX_ClearFlag_SO3 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF3); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 4. + * @rmtoll CFR CSOF4 LL_DMAMUX_ClearFlag_SO4 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF4); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 5. + * @rmtoll CFR CSOF5 LL_DMAMUX_ClearFlag_SO5 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF5); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 6. + * @rmtoll CFR CSOF6 LL_DMAMUX_ClearFlag_SO6 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF6); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 7. + * @rmtoll CFR CSOF7 LL_DMAMUX_ClearFlag_SO7 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF7); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 8. + * @rmtoll CFR CSOF8 LL_DMAMUX_ClearFlag_SO8 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF8); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 9. + * @rmtoll CFR CSOF9 LL_DMAMUX_ClearFlag_SO9 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF9); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 10. + * @rmtoll CFR CSOF10 LL_DMAMUX_ClearFlag_SO10 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF10); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 11. + * @rmtoll CFR CSOF11 LL_DMAMUX_ClearFlag_SO11 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF11); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 12. + * @rmtoll CFR CSOF12 LL_DMAMUX_ClearFlag_SO12 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF12); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 13. + * @rmtoll CFR CSOF13 LL_DMAMUX_ClearFlag_SO13 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF13); +} + +/** + * @brief Clear Request Generator 0 Trigger Event Overrun Flag. + * @rmtoll RGCFR COF0 LL_DMAMUX_ClearFlag_RGO0 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF0); +} + +/** + * @brief Clear Request Generator 1 Trigger Event Overrun Flag. + * @rmtoll RGCFR COF1 LL_DMAMUX_ClearFlag_RGO1 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF1); +} + +/** + * @brief Clear Request Generator 2 Trigger Event Overrun Flag. + * @rmtoll RGCFR COF2 LL_DMAMUX_ClearFlag_RGO2 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF2); +} + +/** + * @brief Clear Request Generator 3 Trigger Event Overrun Flag. + * @rmtoll RGCFR COF3 LL_DMAMUX_ClearFlag_RGO3 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF3); +} + +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable the Synchronization Event Overrun Interrupt on DMAMUX channel x. + * @rmtoll CxCR SOIE LL_DMAMUX_EnableIT_SO + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_EnableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + (void)(DMAMUXx); + SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SOIE); +} + +/** + * @brief Disable the Synchronization Event Overrun Interrupt on DMAMUX channel x. + * @rmtoll CxCR SOIE LL_DMAMUX_DisableIT_SO + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_DisableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + (void)(DMAMUXx); + CLEAR_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SOIE); +} + +/** + * @brief Check if the Synchronization Event Overrun Interrupt on DMAMUX channel x is enabled or disabled. + * @rmtoll CxCR SOIE LL_DMAMUX_IsEnabledIT_SO + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + (void)(DMAMUXx); + return (((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SOIE)) == (DMAMUX_CxCR_SOIE))? 1UL : 0UL); +} + +/** + * @brief Enable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x. + * @rmtoll RGxCR OIE LL_DMAMUX_EnableIT_RGO + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_EnableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + (void)(DMAMUXx); + SET_BIT((DMAMUX1_RequestGenerator0 + RequestGenChannel)->RGCR, DMAMUX_RGxCR_OIE); +} + +/** + * @brief Disable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x. + * @rmtoll RGxCR OIE LL_DMAMUX_DisableIT_RGO + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_DisableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + (void)(DMAMUXx); + CLEAR_BIT((DMAMUX1_RequestGenerator0 + RequestGenChannel)->RGCR, DMAMUX_RGxCR_OIE); +} + +/** + * @brief Check if the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x is enabled or disabled. + * @rmtoll RGxCR OIE LL_DMAMUX_IsEnabledIT_RGO + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + (void)(DMAMUXx); + return ((READ_BIT((DMAMUX1_RequestGenerator0 + RequestGenChannel)->RGCR, DMAMUX_RGxCR_OIE) == (DMAMUX_RGxCR_OIE))? 1UL : 0UL); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* DMAMUX1 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32L4xx_LL_DMAMUX_H */ diff --git a/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_exti.h b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_exti.h new file mode 100644 index 0000000..a1ee112 --- /dev/null +++ b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_exti.h @@ -0,0 +1,1359 @@ +/** + ****************************************************************************** + * @file stm32l4xx_ll_exti.h + * @author MCD Application Team + * @brief Header file of EXTI LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32L4xx_LL_EXTI_H +#define STM32L4xx_LL_EXTI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx.h" + +/** @addtogroup STM32L4xx_LL_Driver + * @{ + */ + +#if defined (EXTI) + +/** @defgroup EXTI_LL EXTI + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private Macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup EXTI_LL_Private_Macros EXTI Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure + * @{ + */ +typedef struct +{ + + uint32_t Line_0_31; /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31 + This parameter can be any combination of @ref EXTI_LL_EC_LINE */ + + uint32_t Line_32_63; /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 32 to 63 + This parameter can be any combination of @ref EXTI_LL_EC_LINE */ + + FunctionalState LineCommand; /*!< Specifies the new state of the selected EXTI lines. + This parameter can be set either to ENABLE or DISABLE */ + + uint8_t Mode; /*!< Specifies the mode for the EXTI lines. + This parameter can be a value of @ref EXTI_LL_EC_MODE. */ + + uint8_t Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. + This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */ +} LL_EXTI_InitTypeDef; + +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants + * @{ + */ + +/** @defgroup EXTI_LL_EC_LINE LINE + * @{ + */ +#define LL_EXTI_LINE_0 EXTI_IMR1_IM0 /*!< Extended line 0 */ +#define LL_EXTI_LINE_1 EXTI_IMR1_IM1 /*!< Extended line 1 */ +#define LL_EXTI_LINE_2 EXTI_IMR1_IM2 /*!< Extended line 2 */ +#define LL_EXTI_LINE_3 EXTI_IMR1_IM3 /*!< Extended line 3 */ +#define LL_EXTI_LINE_4 EXTI_IMR1_IM4 /*!< Extended line 4 */ +#define LL_EXTI_LINE_5 EXTI_IMR1_IM5 /*!< Extended line 5 */ +#define LL_EXTI_LINE_6 EXTI_IMR1_IM6 /*!< Extended line 6 */ +#define LL_EXTI_LINE_7 EXTI_IMR1_IM7 /*!< Extended line 7 */ +#define LL_EXTI_LINE_8 EXTI_IMR1_IM8 /*!< Extended line 8 */ +#define LL_EXTI_LINE_9 EXTI_IMR1_IM9 /*!< Extended line 9 */ +#define LL_EXTI_LINE_10 EXTI_IMR1_IM10 /*!< Extended line 10 */ +#define LL_EXTI_LINE_11 EXTI_IMR1_IM11 /*!< Extended line 11 */ +#define LL_EXTI_LINE_12 EXTI_IMR1_IM12 /*!< Extended line 12 */ +#define LL_EXTI_LINE_13 EXTI_IMR1_IM13 /*!< Extended line 13 */ +#define LL_EXTI_LINE_14 EXTI_IMR1_IM14 /*!< Extended line 14 */ +#define LL_EXTI_LINE_15 EXTI_IMR1_IM15 /*!< Extended line 15 */ +#if defined(EXTI_IMR1_IM16) +#define LL_EXTI_LINE_16 EXTI_IMR1_IM16 /*!< Extended line 16 */ +#endif +#define LL_EXTI_LINE_17 EXTI_IMR1_IM17 /*!< Extended line 17 */ +#if defined(EXTI_IMR1_IM18) +#define LL_EXTI_LINE_18 EXTI_IMR1_IM18 /*!< Extended line 18 */ +#endif +#define LL_EXTI_LINE_19 EXTI_IMR1_IM19 /*!< Extended line 19 */ +#if defined(EXTI_IMR1_IM20) +#define LL_EXTI_LINE_20 EXTI_IMR1_IM20 /*!< Extended line 20 */ +#endif +#if defined(EXTI_IMR1_IM21) +#define LL_EXTI_LINE_21 EXTI_IMR1_IM21 /*!< Extended line 21 */ +#endif +#if defined(EXTI_IMR1_IM22) +#define LL_EXTI_LINE_22 EXTI_IMR1_IM22 /*!< Extended line 22 */ +#endif +#define LL_EXTI_LINE_23 EXTI_IMR1_IM23 /*!< Extended line 23 */ +#if defined(EXTI_IMR1_IM24) +#define LL_EXTI_LINE_24 EXTI_IMR1_IM24 /*!< Extended line 24 */ +#endif +#if defined(EXTI_IMR1_IM25) +#define LL_EXTI_LINE_25 EXTI_IMR1_IM25 /*!< Extended line 25 */ +#endif +#if defined(EXTI_IMR1_IM26) +#define LL_EXTI_LINE_26 EXTI_IMR1_IM26 /*!< Extended line 26 */ +#endif +#if defined(EXTI_IMR1_IM27) +#define LL_EXTI_LINE_27 EXTI_IMR1_IM27 /*!< Extended line 27 */ +#endif +#if defined(EXTI_IMR1_IM28) +#define LL_EXTI_LINE_28 EXTI_IMR1_IM28 /*!< Extended line 28 */ +#endif +#if defined(EXTI_IMR1_IM29) +#define LL_EXTI_LINE_29 EXTI_IMR1_IM29 /*!< Extended line 29 */ +#endif +#if defined(EXTI_IMR1_IM30) +#define LL_EXTI_LINE_30 EXTI_IMR1_IM30 /*!< Extended line 30 */ +#endif +#if defined(EXTI_IMR1_IM31) +#define LL_EXTI_LINE_31 EXTI_IMR1_IM31 /*!< Extended line 31 */ +#endif +#define LL_EXTI_LINE_ALL_0_31 EXTI_IMR1_IM /*!< All Extended line not reserved*/ + +#define LL_EXTI_LINE_32 EXTI_IMR2_IM32 /*!< Extended line 32 */ +#if defined(EXTI_IMR2_IM33) +#define LL_EXTI_LINE_33 EXTI_IMR2_IM33 /*!< Extended line 33 */ +#endif +#if defined(EXTI_IMR2_IM34) +#define LL_EXTI_LINE_34 EXTI_IMR2_IM34 /*!< Extended line 34 */ +#endif +#if defined(EXTI_IMR2_IM35) +#define LL_EXTI_LINE_35 EXTI_IMR2_IM35 /*!< Extended line 35 */ +#endif +#if defined(EXTI_IMR2_IM36) +#define LL_EXTI_LINE_36 EXTI_IMR2_IM36 /*!< Extended line 36 */ +#endif +#if defined(EXTI_IMR2_IM37) +#define LL_EXTI_LINE_37 EXTI_IMR2_IM37 /*!< Extended line 37 */ +#endif +#if defined(EXTI_IMR2_IM38) +#define LL_EXTI_LINE_38 EXTI_IMR2_IM38 /*!< Extended line 38 */ +#endif +#if defined(EXTI_IMR2_IM39) +#define LL_EXTI_LINE_39 EXTI_IMR2_IM39 /*!< Extended line 39 */ +#endif +#if defined(EXTI_IMR2_IM40) +#define LL_EXTI_LINE_40 EXTI_IMR2_IM40 /*!< Extended line 40 */ +#endif +#define LL_EXTI_LINE_ALL_32_63 EXTI_IMR2_IM /*!< All Extended line not reserved*/ + + +#define LL_EXTI_LINE_ALL (0xFFFFFFFFU) /*!< All Extended line */ + +#if defined(USE_FULL_LL_DRIVER) +#define LL_EXTI_LINE_NONE (0x00000000U) /*!< None Extended line */ +#endif /*USE_FULL_LL_DRIVER*/ + +/** + * @} + */ + + +#if defined(USE_FULL_LL_DRIVER) + +/** @defgroup EXTI_LL_EC_MODE Mode + * @{ + */ +#define LL_EXTI_MODE_IT ((uint8_t)0x00U) /*!< Interrupt Mode */ +#define LL_EXTI_MODE_EVENT ((uint8_t)0x01U) /*!< Event Mode */ +#define LL_EXTI_MODE_IT_EVENT ((uint8_t)0x02U) /*!< Interrupt & Event Mode */ +/** + * @} + */ + +/** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger + * @{ + */ +#define LL_EXTI_TRIGGER_NONE ((uint8_t)0x00U) /*!< No Trigger Mode */ +#define LL_EXTI_TRIGGER_RISING ((uint8_t)0x01U) /*!< Trigger Rising Mode */ +#define LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02U) /*!< Trigger Falling Mode */ +#define LL_EXTI_TRIGGER_RISING_FALLING ((uint8_t)0x03U) /*!< Trigger Rising & Falling Mode */ + +/** + * @} + */ + + +#endif /*USE_FULL_LL_DRIVER*/ + + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros + * @{ + */ + +/** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in EXTI register + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__)) + +/** + * @brief Read a value in EXTI register + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__) +/** + * @} + */ + + +/** + * @} + */ + + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions + * @{ + */ +/** @defgroup EXTI_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Interrupt request for Lines in range 0 to 31 + * @note The reset value for the direct or internal lines (see RM) + * is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR1 IMx LL_EXTI_EnableIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->IMR1, ExtiLine); +} +/** + * @brief Enable ExtiLine Interrupt request for Lines in range 32 to 63 + * @note The reset value for the direct lines (lines from 32 to 34, line + * 39) is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR2 IMx LL_EXTI_EnableIT_32_63 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34(*) + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39(*) + * @arg @ref LL_EXTI_LINE_40(*) + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @note (*): Available in some devices + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableIT_32_63(uint32_t ExtiLine) +{ + SET_BIT(EXTI->IMR2, ExtiLine); +} + +/** + * @brief Disable ExtiLine Interrupt request for Lines in range 0 to 31 + * @note The reset value for the direct or internal lines (see RM) + * is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR1 IMx LL_EXTI_DisableIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->IMR1, ExtiLine); +} + +/** + * @brief Disable ExtiLine Interrupt request for Lines in range 32 to 63 + * @note The reset value for the direct lines (lines from 32 to 34, line + * 39) is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR2 IMx LL_EXTI_DisableIT_32_63 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34(*) + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39(*) + * @arg @ref LL_EXTI_LINE_40(*) + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @note (*): Available in some devices + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableIT_32_63(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->IMR2, ExtiLine); +} + +/** + * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31 + * @note The reset value for the direct or internal lines (see RM) + * is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR1 IMx LL_EXTI_IsEnabledIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->IMR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +/** + * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 32 to 63 + * @note The reset value for the direct lines (lines from 32 to 34, line + * 39) is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR2 IMx LL_EXTI_IsEnabledIT_32_63 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34(*) + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39(*) + * @arg @ref LL_EXTI_LINE_40(*) + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @note (*): Available in some devices + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_32_63(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->IMR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Event_Management Event_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Event request for Lines in range 0 to 31 + * @rmtoll EMR1 EMx LL_EXTI_EnableEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->EMR1, ExtiLine); + +} + +/** + * @brief Enable ExtiLine Event request for Lines in range 32 to 63 + * @rmtoll EMR2 EMx LL_EXTI_EnableEvent_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34(*) + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39(*) + * @arg @ref LL_EXTI_LINE_40(*) + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @note (*): Available in some devices + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableEvent_32_63(uint32_t ExtiLine) +{ + SET_BIT(EXTI->EMR2, ExtiLine); +} + +/** + * @brief Disable ExtiLine Event request for Lines in range 0 to 31 + * @rmtoll EMR1 EMx LL_EXTI_DisableEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->EMR1, ExtiLine); +} + +/** + * @brief Disable ExtiLine Event request for Lines in range 32 to 63 + * @rmtoll EMR2 EMx LL_EXTI_DisableEvent_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34(*) + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39(*) + * @arg @ref LL_EXTI_LINE_40(*) + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @note (*): Available in some devices + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableEvent_32_63(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->EMR2, ExtiLine); +} + +/** + * @brief Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31 + * @rmtoll EMR1 EMx LL_EXTI_IsEnabledEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->EMR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); + +} + +/** + * @brief Indicate if ExtiLine Event request is enabled for Lines in range 32 to 63 + * @rmtoll EMR2 EMx LL_EXTI_IsEnabledEvent_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34(*) + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39(*) + * @arg @ref LL_EXTI_LINE_40(*) + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @note (*): Available in some devices + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_32_63(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->EMR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll RTSR1 RTx LL_EXTI_EnableRisingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->RTSR1, ExtiLine); + +} + +/** + * @brief Enable ExtiLine Rising Edge Trigger for Lines in range 32 to 63 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set.Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll RTSR2 RTx LL_EXTI_EnableRisingTrig_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableRisingTrig_32_63(uint32_t ExtiLine) +{ + SET_BIT(EXTI->RTSR2, ExtiLine); +} + +/** + * @brief Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll RTSR1 RTx LL_EXTI_DisableRisingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->RTSR1, ExtiLine); + +} + +/** + * @brief Disable ExtiLine Rising Edge Trigger for Lines in range 32 to 63 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll RTSR2 RTx LL_EXTI_DisableRisingTrig_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableRisingTrig_32_63(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->RTSR2, ExtiLine); +} + +/** + * @brief Check if rising edge trigger is enabled for Lines in range 0 to 31 + * @rmtoll RTSR1 RTx LL_EXTI_IsEnabledRisingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->RTSR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +/** + * @brief Check if rising edge trigger is enabled for Lines in range 32 to 63 + * @rmtoll RTSR2 RTx LL_EXTI_IsEnabledRisingTrig_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_32_63(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->RTSR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll FTSR1 FTx LL_EXTI_EnableFallingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->FTSR1, ExtiLine); +} + +/** + * @brief Enable ExtiLine Falling Edge Trigger for Lines in range 32 to 63 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a Falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll FTSR2 FTx LL_EXTI_EnableFallingTrig_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableFallingTrig_32_63(uint32_t ExtiLine) +{ + SET_BIT(EXTI->FTSR2, ExtiLine); +} + +/** + * @brief Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a Falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for the same interrupt line. + * In this case, both generate a trigger condition. + * @rmtoll FTSR1 FTx LL_EXTI_DisableFallingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->FTSR1, ExtiLine); +} + +/** + * @brief Disable ExtiLine Falling Edge Trigger for Lines in range 32 to 63 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a Falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for the same interrupt line. + * In this case, both generate a trigger condition. + * @rmtoll FTSR2 FTx LL_EXTI_DisableFallingTrig_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableFallingTrig_32_63(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->FTSR2, ExtiLine); +} + +/** + * @brief Check if falling edge trigger is enabled for Lines in range 0 to 31 + * @rmtoll FTSR1 FTx LL_EXTI_IsEnabledFallingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->FTSR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +/** + * @brief Check if falling edge trigger is enabled for Lines in range 32 to 63 + * @rmtoll FTSR2 FTx LL_EXTI_IsEnabledFallingTrig_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_32_63(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->FTSR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management + * @{ + */ + +/** + * @brief Generate a software Interrupt Event for Lines in range 0 to 31 + * @note If the interrupt is enabled on this line in the EXTI_IMR1, writing a 1 to + * this bit when it is at '0' sets the corresponding pending bit in EXTI_PR1 + * resulting in an interrupt request generation. + * This bit is cleared by clearing the corresponding bit in the EXTI_PR1 + * register (by writing a 1 into the bit) + * @rmtoll SWIER1 SWIx LL_EXTI_GenerateSWI_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->SWIER1, ExtiLine); +} + +/** + * @brief Generate a software Interrupt Event for Lines in range 32 to 63 + * @note If the interrupt is enabled on this line in the EXTI_IMR2, writing a 1 to + * this bit when it is at '0' sets the corresponding pending bit in EXTI_PR2 + * resulting in an interrupt request generation. + * This bit is cleared by clearing the corresponding bit in the EXTI_PR2 + * register (by writing a 1 into the bit) + * @rmtoll SWIER2 SWIx LL_EXTI_GenerateSWI_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_GenerateSWI_32_63(uint32_t ExtiLine) +{ + SET_BIT(EXTI->SWIER2, ExtiLine); +} + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Flag_Management Flag_Management + * @{ + */ + +/** + * @brief Check if the ExtLine Flag is set or not for Lines in range 0 to 31 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR1 PIFx LL_EXTI_IsActiveFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->PR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +/** + * @brief Check if the ExtLine Flag is set or not for Lines in range 32 to 63 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR2 PIFx LL_EXTI_IsActiveFlag_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_32_63(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->PR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +/** + * @brief Read ExtLine Combination Flag for Lines in range 0 to 31 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR1 PIFx LL_EXTI_ReadFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval @note This bit is set when the selected edge event arrives on the interrupt + */ +__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_0_31(uint32_t ExtiLine) +{ + return (uint32_t)(READ_BIT(EXTI->PR1, ExtiLine)); +} + +/** + * @brief Read ExtLine Combination Flag for Lines in range 32 to 63 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR2 PIFx LL_EXTI_ReadFlag_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @retval @note This bit is set when the selected edge event arrives on the interrupt + */ +__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_32_63(uint32_t ExtiLine) +{ + return (uint32_t)(READ_BIT(EXTI->PR2, ExtiLine)); +} + +/** + * @brief Clear ExtLine Flags for Lines in range 0 to 31 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR1 PIFx LL_EXTI_ClearFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_ClearFlag_0_31(uint32_t ExtiLine) +{ + WRITE_REG(EXTI->PR1, ExtiLine); +} + +/** + * @brief Clear ExtLine Flags for Lines in range 32 to 63 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR2 PIFx LL_EXTI_ClearFlag_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_ClearFlag_32_63(uint32_t ExtiLine) +{ + WRITE_REG(EXTI->PR2, ExtiLine); +} + + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct); +uint32_t LL_EXTI_DeInit(void); +void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct); + + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* EXTI */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32L4xx_LL_EXTI_H */ + diff --git a/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_gpio.h b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_gpio.h new file mode 100644 index 0000000..72bb307 --- /dev/null +++ b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_gpio.h @@ -0,0 +1,1056 @@ +/** + ****************************************************************************** + * @file stm32l4xx_ll_gpio.h + * @author MCD Application Team + * @brief Header file of GPIO LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32L4xx_LL_GPIO_H +#define STM32L4xx_LL_GPIO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx.h" + +/** @addtogroup STM32L4xx_LL_Driver + * @{ + */ + +#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) + +/** @defgroup GPIO_LL GPIO + * @{ + */ +/** MISRA C:2012 deviation rule has been granted for following rules: + * Rule-18.1_d - Medium: Array pointer `GPIOx' is accessed with index [..,..] + * which may be out of array bounds [..,UNKNOWN] in following APIs: + * LL_GPIO_GetAFPin_0_7 + * LL_GPIO_SetAFPin_0_7 + * LL_GPIO_SetAFPin_8_15 + * LL_GPIO_GetAFPin_8_15 + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup GPIO_LL_Private_Macros GPIO Private Macros + * @{ + */ + +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures + * @{ + */ + +/** + * @brief LL GPIO Init Structure definition + */ +typedef struct +{ + uint32_t Pin; /*!< Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_LL_EC_PIN */ + + uint32_t Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_MODE. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinMode().*/ + + uint32_t Speed; /*!< Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_SPEED. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinSpeed().*/ + + uint32_t OutputType; /*!< Specifies the operating output type for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_OUTPUT. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinOutputType().*/ + + uint32_t Pull; /*!< Specifies the operating Pull-up/Pull down for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_PULL. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinPull().*/ + + uint32_t Alternate; /*!< Specifies the Peripheral to be connected to the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_AF. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetAFPin_0_7() and LL_GPIO_SetAFPin_8_15().*/ +} LL_GPIO_InitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants + * @{ + */ + +/** @defgroup GPIO_LL_EC_PIN PIN + * @{ + */ +#define LL_GPIO_PIN_0 GPIO_BSRR_BS0 /*!< Select pin 0 */ +#define LL_GPIO_PIN_1 GPIO_BSRR_BS1 /*!< Select pin 1 */ +#define LL_GPIO_PIN_2 GPIO_BSRR_BS2 /*!< Select pin 2 */ +#define LL_GPIO_PIN_3 GPIO_BSRR_BS3 /*!< Select pin 3 */ +#define LL_GPIO_PIN_4 GPIO_BSRR_BS4 /*!< Select pin 4 */ +#define LL_GPIO_PIN_5 GPIO_BSRR_BS5 /*!< Select pin 5 */ +#define LL_GPIO_PIN_6 GPIO_BSRR_BS6 /*!< Select pin 6 */ +#define LL_GPIO_PIN_7 GPIO_BSRR_BS7 /*!< Select pin 7 */ +#define LL_GPIO_PIN_8 GPIO_BSRR_BS8 /*!< Select pin 8 */ +#define LL_GPIO_PIN_9 GPIO_BSRR_BS9 /*!< Select pin 9 */ +#define LL_GPIO_PIN_10 GPIO_BSRR_BS10 /*!< Select pin 10 */ +#define LL_GPIO_PIN_11 GPIO_BSRR_BS11 /*!< Select pin 11 */ +#define LL_GPIO_PIN_12 GPIO_BSRR_BS12 /*!< Select pin 12 */ +#define LL_GPIO_PIN_13 GPIO_BSRR_BS13 /*!< Select pin 13 */ +#define LL_GPIO_PIN_14 GPIO_BSRR_BS14 /*!< Select pin 14 */ +#define LL_GPIO_PIN_15 GPIO_BSRR_BS15 /*!< Select pin 15 */ +#define LL_GPIO_PIN_ALL (GPIO_BSRR_BS0 | GPIO_BSRR_BS1 | GPIO_BSRR_BS2 | \ + GPIO_BSRR_BS3 | GPIO_BSRR_BS4 | GPIO_BSRR_BS5 | \ + GPIO_BSRR_BS6 | GPIO_BSRR_BS7 | GPIO_BSRR_BS8 | \ + GPIO_BSRR_BS9 | GPIO_BSRR_BS10 | GPIO_BSRR_BS11 | \ + GPIO_BSRR_BS12 | GPIO_BSRR_BS13 | GPIO_BSRR_BS14 | \ + GPIO_BSRR_BS15) /*!< Select all pins */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_MODE Mode + * @{ + */ +#define LL_GPIO_MODE_INPUT (0x00000000U) /*!< Select input mode */ +#define LL_GPIO_MODE_OUTPUT GPIO_MODER_MODE0_0 /*!< Select output mode */ +#define LL_GPIO_MODE_ALTERNATE GPIO_MODER_MODE0_1 /*!< Select alternate function mode */ +#define LL_GPIO_MODE_ANALOG GPIO_MODER_MODE0 /*!< Select analog mode */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_OUTPUT Output Type + * @{ + */ +#define LL_GPIO_OUTPUT_PUSHPULL (0x00000000U) /*!< Select push-pull as output type */ +#define LL_GPIO_OUTPUT_OPENDRAIN GPIO_OTYPER_OT0 /*!< Select open-drain as output type */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_SPEED Output Speed + * @{ + */ +#define LL_GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< Select I/O low output speed */ +#define LL_GPIO_SPEED_FREQ_MEDIUM GPIO_OSPEEDR_OSPEED0_0 /*!< Select I/O medium output speed */ +#define LL_GPIO_SPEED_FREQ_HIGH GPIO_OSPEEDR_OSPEED0_1 /*!< Select I/O fast output speed */ +#define LL_GPIO_SPEED_FREQ_VERY_HIGH GPIO_OSPEEDR_OSPEED0 /*!< Select I/O high output speed */ +/** + * @} + */ +#define LL_GPIO_SPEED_LOW LL_GPIO_SPEED_FREQ_LOW +#define LL_GPIO_SPEED_MEDIUM LL_GPIO_SPEED_FREQ_MEDIUM +#define LL_GPIO_SPEED_FAST LL_GPIO_SPEED_FREQ_HIGH +#define LL_GPIO_SPEED_HIGH LL_GPIO_SPEED_FREQ_VERY_HIGH + +/** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down + * @{ + */ +#define LL_GPIO_PULL_NO (0x00000000U) /*!< Select I/O no pull */ +#define LL_GPIO_PULL_UP GPIO_PUPDR_PUPD0_0 /*!< Select I/O pull up */ +#define LL_GPIO_PULL_DOWN GPIO_PUPDR_PUPD0_1 /*!< Select I/O pull down */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_AF Alternate Function + * @{ + */ +#define LL_GPIO_AF_0 (0x0000000U) /*!< Select alternate function 0 */ +#define LL_GPIO_AF_1 (0x0000001U) /*!< Select alternate function 1 */ +#define LL_GPIO_AF_2 (0x0000002U) /*!< Select alternate function 2 */ +#define LL_GPIO_AF_3 (0x0000003U) /*!< Select alternate function 3 */ +#define LL_GPIO_AF_4 (0x0000004U) /*!< Select alternate function 4 */ +#define LL_GPIO_AF_5 (0x0000005U) /*!< Select alternate function 5 */ +#define LL_GPIO_AF_6 (0x0000006U) /*!< Select alternate function 6 */ +#define LL_GPIO_AF_7 (0x0000007U) /*!< Select alternate function 7 */ +#define LL_GPIO_AF_8 (0x0000008U) /*!< Select alternate function 8 */ +#define LL_GPIO_AF_9 (0x0000009U) /*!< Select alternate function 9 */ +#define LL_GPIO_AF_10 (0x000000AU) /*!< Select alternate function 10 */ +#define LL_GPIO_AF_11 (0x000000BU) /*!< Select alternate function 11 */ +#define LL_GPIO_AF_12 (0x000000CU) /*!< Select alternate function 12 */ +#define LL_GPIO_AF_13 (0x000000DU) /*!< Select alternate function 13 */ +#define LL_GPIO_AF_14 (0x000000EU) /*!< Select alternate function 14 */ +#define LL_GPIO_AF_15 (0x000000FU) /*!< Select alternate function 15 */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros + * @{ + */ + +/** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in GPIO register + * @param __INSTANCE__ GPIO Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in GPIO register + * @param __INSTANCE__ GPIO Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions + * @{ + */ + +/** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration + * @{ + */ + +/** + * @brief Configure gpio mode for a dedicated pin on dedicated port. + * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll MODER MODEy LL_GPIO_SetPinMode + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_GPIO_MODE_INPUT + * @arg @ref LL_GPIO_MODE_OUTPUT + * @arg @ref LL_GPIO_MODE_ALTERNATE + * @arg @ref LL_GPIO_MODE_ANALOG + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode) +{ + MODIFY_REG(GPIOx->MODER, (GPIO_MODER_MODE0 << (POSITION_VAL(Pin) * 2U)), (Mode << (POSITION_VAL(Pin) * 2U))); +} + +/** + * @brief Return gpio mode for a dedicated pin on dedicated port. + * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll MODER MODEy LL_GPIO_GetPinMode + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_MODE_INPUT + * @arg @ref LL_GPIO_MODE_OUTPUT + * @arg @ref LL_GPIO_MODE_ALTERNATE + * @arg @ref LL_GPIO_MODE_ANALOG + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->MODER, + (GPIO_MODER_MODE0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U)); +} + +/** + * @brief Configure gpio output type for several pins on dedicated port. + * @note Output type as to be set when gpio pin is in output or + * alternate modes. Possible type are Push-pull or Open-drain. + * @rmtoll OTYPER OTy LL_GPIO_SetPinOutputType + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @param OutputType This parameter can be one of the following values: + * @arg @ref LL_GPIO_OUTPUT_PUSHPULL + * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType) +{ + MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType)); +} + +/** + * @brief Return gpio output type for several pins on dedicated port. + * @note Output type as to be set when gpio pin is in output or + * alternate modes. Possible type are Push-pull or Open-drain. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll OTYPER OTy LL_GPIO_GetPinOutputType + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_OUTPUT_PUSHPULL + * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) >> POSITION_VAL(Pin)); +} + +/** + * @brief Configure gpio speed for a dedicated pin on dedicated port. + * @note I/O speed can be Low, Medium, Fast or High speed. + * @note Warning: only one pin can be passed as parameter. + * @note Refer to datasheet for frequency specifications and the power + * supply and load conditions for each speed. + * @rmtoll OSPEEDR OSPEEDy LL_GPIO_SetPinSpeed + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Speed This parameter can be one of the following values: + * @arg @ref LL_GPIO_SPEED_FREQ_LOW + * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM + * @arg @ref LL_GPIO_SPEED_FREQ_HIGH + * @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed) +{ + MODIFY_REG(GPIOx->OSPEEDR, (GPIO_OSPEEDR_OSPEED0 << (POSITION_VAL(Pin) * 2U)), + (Speed << (POSITION_VAL(Pin) * 2U))); +} + +/** + * @brief Return gpio speed for a dedicated pin on dedicated port. + * @note I/O speed can be Low, Medium, Fast or High speed. + * @note Warning: only one pin can be passed as parameter. + * @note Refer to datasheet for frequency specifications and the power + * supply and load conditions for each speed. + * @rmtoll OSPEEDR OSPEEDy LL_GPIO_GetPinSpeed + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_SPEED_FREQ_LOW + * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM + * @arg @ref LL_GPIO_SPEED_FREQ_HIGH + * @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->OSPEEDR, + (GPIO_OSPEEDR_OSPEED0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U)); +} + +/** + * @brief Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll PUPDR PUPDy LL_GPIO_SetPinPull + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Pull This parameter can be one of the following values: + * @arg @ref LL_GPIO_PULL_NO + * @arg @ref LL_GPIO_PULL_UP + * @arg @ref LL_GPIO_PULL_DOWN + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull) +{ + MODIFY_REG(GPIOx->PUPDR, (GPIO_PUPDR_PUPD0 << (POSITION_VAL(Pin) * 2U)), (Pull << (POSITION_VAL(Pin) * 2U))); +} + +/** + * @brief Return gpio pull-up or pull-down for a dedicated pin on a dedicated port + * @note Warning: only one pin can be passed as parameter. + * @rmtoll PUPDR PUPDy LL_GPIO_GetPinPull + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_PULL_NO + * @arg @ref LL_GPIO_PULL_UP + * @arg @ref LL_GPIO_PULL_DOWN + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->PUPDR, + (GPIO_PUPDR_PUPD0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U)); +} + +/** + * @brief Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port. + * @note Possible values are from AF0 to AF15 depending on target. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll AFRL AFSELy LL_GPIO_SetAFPin_0_7 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @param Alternate This parameter can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @arg @ref LL_GPIO_AF_8 + * @arg @ref LL_GPIO_AF_9 + * @arg @ref LL_GPIO_AF_10 + * @arg @ref LL_GPIO_AF_11 + * @arg @ref LL_GPIO_AF_12 + * @arg @ref LL_GPIO_AF_13 + * @arg @ref LL_GPIO_AF_14 + * @arg @ref LL_GPIO_AF_15 + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) +{ + MODIFY_REG(GPIOx->AFR[0], (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * 4U)), + (Alternate << (POSITION_VAL(Pin) * 4U))); +} + +/** + * @brief Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port. + * @rmtoll AFRL AFSELy LL_GPIO_GetAFPin_0_7 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @arg @ref LL_GPIO_AF_8 + * @arg @ref LL_GPIO_AF_9 + * @arg @ref LL_GPIO_AF_10 + * @arg @ref LL_GPIO_AF_11 + * @arg @ref LL_GPIO_AF_12 + * @arg @ref LL_GPIO_AF_13 + * @arg @ref LL_GPIO_AF_14 + * @arg @ref LL_GPIO_AF_15 + */ +__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->AFR[0], + (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U)); +} + +/** + * @brief Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port. + * @note Possible values are from AF0 to AF15 depending on target. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll AFRH AFSELy LL_GPIO_SetAFPin_8_15 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Alternate This parameter can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @arg @ref LL_GPIO_AF_8 + * @arg @ref LL_GPIO_AF_9 + * @arg @ref LL_GPIO_AF_10 + * @arg @ref LL_GPIO_AF_11 + * @arg @ref LL_GPIO_AF_12 + * @arg @ref LL_GPIO_AF_13 + * @arg @ref LL_GPIO_AF_14 + * @arg @ref LL_GPIO_AF_15 + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) +{ + MODIFY_REG(GPIOx->AFR[1], (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * 4U)), + (Alternate << (POSITION_VAL(Pin >> 8U) * 4U))); +} + +/** + * @brief Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port. + * @note Possible values are from AF0 to AF15 depending on target. + * @rmtoll AFRH AFSELy LL_GPIO_GetAFPin_8_15 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @arg @ref LL_GPIO_AF_8 + * @arg @ref LL_GPIO_AF_9 + * @arg @ref LL_GPIO_AF_10 + * @arg @ref LL_GPIO_AF_11 + * @arg @ref LL_GPIO_AF_12 + * @arg @ref LL_GPIO_AF_13 + * @arg @ref LL_GPIO_AF_14 + * @arg @ref LL_GPIO_AF_15 + */ +__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->AFR[1], + (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * 4U))) >> (POSITION_VAL(Pin >> 8U) * 4U)); +} + +#if defined(GPIO_ASCR_ASC0) +/** + * @brief Connect analog switch to ADC input of several pins for a dedicated port. + * @note This bit must be set prior to the ADC conversion. + * Only the IO which connected to the ADC input are effective. + * Other IO must be kept reset value + * @rmtoll ASCR ASCy LL_GPIO_EnablePinAnalogControl + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_EnablePinAnalogControl(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + SET_BIT(GPIOx->ASCR, PinMask); +} + +/** + * @brief Disconnect analog switch to ADC input of several pins for a dedicated port. + * @rmtoll ASCR ASCy LL_GPIO_DisablePinAnalogControl + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_DisablePinAnalogControl(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + CLEAR_BIT(GPIOx->ASCR, PinMask); +} +#endif /* GPIO_ASCR_ASC0 */ + +/** + * @brief Lock configuration of several pins for a dedicated port. + * @note When the lock sequence has been applied on a port bit, the + * value of this port bit can no longer be modified until the + * next reset. + * @note Each lock bit freezes a specific configuration register + * (control and alternate function registers). + * @rmtoll LCKR LCKK LL_GPIO_LockPin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + __IO uint32_t temp; + WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask); + WRITE_REG(GPIOx->LCKR, PinMask); + WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask); + /* Read LCKK register. This read is mandatory to complete key lock sequence */ + temp = READ_REG(GPIOx->LCKR); + (void) temp; +} + +/** + * @brief Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0. + * @rmtoll LCKR LCKy LL_GPIO_IsPinLocked + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + return ((READ_BIT(GPIOx->LCKR, PinMask) == (PinMask)) ? 1UL : 0UL); +} + +/** + * @brief Return 1 if one of the pin of a dedicated port is locked. else return 0. + * @rmtoll LCKR LCKK LL_GPIO_IsAnyPinLocked + * @param GPIOx GPIO Port + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx) +{ + return ((READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup GPIO_LL_EF_Data_Access Data Access + * @{ + */ + +/** + * @brief Return full input data register value for a dedicated port. + * @rmtoll IDR IDy LL_GPIO_ReadInputPort + * @param GPIOx GPIO Port + * @retval Input data register value of port + */ +__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx) +{ + return (uint32_t)(READ_REG(GPIOx->IDR)); +} + +/** + * @brief Return if input data level for several pins of dedicated port is high or low. + * @rmtoll IDR IDy LL_GPIO_IsInputPinSet + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + return ((READ_BIT(GPIOx->IDR, PinMask) == (PinMask)) ? 1UL : 0UL); +} + +/** + * @brief Write output data register for the port. + * @rmtoll ODR ODy LL_GPIO_WriteOutputPort + * @param GPIOx GPIO Port + * @param PortValue Level value for each pin of the port + * @retval None + */ +__STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue) +{ + WRITE_REG(GPIOx->ODR, PortValue); +} + +/** + * @brief Return full output data register value for a dedicated port. + * @rmtoll ODR ODy LL_GPIO_ReadOutputPort + * @param GPIOx GPIO Port + * @retval Output data register value of port + */ +__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx) +{ + return (uint32_t)(READ_REG(GPIOx->ODR)); +} + +/** + * @brief Return if input data level for several pins of dedicated port is high or low. + * @rmtoll ODR ODy LL_GPIO_IsOutputPinSet + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + return ((READ_BIT(GPIOx->ODR, PinMask) == (PinMask)) ? 1UL : 0UL); +} + +/** + * @brief Set several pins to high level on dedicated gpio port. + * @rmtoll BSRR BSy LL_GPIO_SetOutputPin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + WRITE_REG(GPIOx->BSRR, PinMask); +} + +/** + * @brief Set several pins to low level on dedicated gpio port. + * @rmtoll BRR BRy LL_GPIO_ResetOutputPin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + WRITE_REG(GPIOx->BRR, PinMask); +} + +/** + * @brief Toggle data value for several pin of dedicated port. + * @rmtoll ODR ODy LL_GPIO_TogglePin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + uint32_t odr = READ_REG(GPIOx->ODR); + WRITE_REG(GPIOx->BSRR, ((odr & PinMask) << 16u) | (~odr & PinMask)); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx); +ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct); +void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) */ +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32L4xx_LL_GPIO_H */ + diff --git a/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_i2c.h b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_i2c.h new file mode 100644 index 0000000..d67822e --- /dev/null +++ b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_i2c.h @@ -0,0 +1,2272 @@ +/** + ****************************************************************************** + * @file stm32l4xx_ll_i2c.h + * @author MCD Application Team + * @brief Header file of I2C LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32L4xx_LL_I2C_H +#define STM32L4xx_LL_I2C_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx.h" + +/** @addtogroup STM32L4xx_LL_Driver + * @{ + */ + +#if defined (I2C1) || defined (I2C2) || defined (I2C3) || defined (I2C4) + +/** @defgroup I2C_LL I2C + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup I2C_LL_Private_Constants I2C Private Constants + * @{ + */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup I2C_LL_Private_Macros I2C Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup I2C_LL_ES_INIT I2C Exported Init structure + * @{ + */ +typedef struct +{ + uint32_t PeripheralMode; /*!< Specifies the peripheral mode. + This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE. + + This feature can be modified afterwards using unitary function + @ref LL_I2C_SetMode(). */ + + uint32_t Timing; /*!< Specifies the SDA setup, hold time and the SCL high, low period values. + This parameter must be set by referring to the STM32CubeMX Tool and + the helper macro @ref __LL_I2C_CONVERT_TIMINGS(). + + This feature can be modified afterwards using unitary function + @ref LL_I2C_SetTiming(). */ + + uint32_t AnalogFilter; /*!< Enables or disables analog noise filter. + This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION. + + This feature can be modified afterwards using unitary functions + @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */ + + uint32_t DigitalFilter; /*!< Configures the digital noise filter. + This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F. + + This feature can be modified afterwards using unitary function + @ref LL_I2C_SetDigitalFilter(). */ + + uint32_t OwnAddress1; /*!< Specifies the device own address 1. + This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF. + + This feature can be modified afterwards using unitary function + @ref LL_I2C_SetOwnAddress1(). */ + + uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive + match code or next received byte. + This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE. + + This feature can be modified afterwards using unitary function + @ref LL_I2C_AcknowledgeNextData(). */ + + uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit). + This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1. + + This feature can be modified afterwards using unitary function + @ref LL_I2C_SetOwnAddress1(). */ +} LL_I2C_InitTypeDef; +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup I2C_LL_Exported_Constants I2C Exported Constants + * @{ + */ + +/** @defgroup I2C_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_I2C_WriteReg function + * @{ + */ +#define LL_I2C_ICR_ADDRCF I2C_ICR_ADDRCF /*!< Address Matched flag */ +#define LL_I2C_ICR_NACKCF I2C_ICR_NACKCF /*!< Not Acknowledge flag */ +#define LL_I2C_ICR_STOPCF I2C_ICR_STOPCF /*!< Stop detection flag */ +#define LL_I2C_ICR_BERRCF I2C_ICR_BERRCF /*!< Bus error flag */ +#define LL_I2C_ICR_ARLOCF I2C_ICR_ARLOCF /*!< Arbitration Lost flag */ +#define LL_I2C_ICR_OVRCF I2C_ICR_OVRCF /*!< Overrun/Underrun flag */ +#define LL_I2C_ICR_PECCF I2C_ICR_PECCF /*!< PEC error flag */ +#define LL_I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF /*!< Timeout detection flag */ +#define LL_I2C_ICR_ALERTCF I2C_ICR_ALERTCF /*!< Alert flag */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_I2C_ReadReg function + * @{ + */ +#define LL_I2C_ISR_TXE I2C_ISR_TXE /*!< Transmit data register empty */ +#define LL_I2C_ISR_TXIS I2C_ISR_TXIS /*!< Transmit interrupt status */ +#define LL_I2C_ISR_RXNE I2C_ISR_RXNE /*!< Receive data register not empty */ +#define LL_I2C_ISR_ADDR I2C_ISR_ADDR /*!< Address matched (slave mode) */ +#define LL_I2C_ISR_NACKF I2C_ISR_NACKF /*!< Not Acknowledge received flag */ +#define LL_I2C_ISR_STOPF I2C_ISR_STOPF /*!< Stop detection flag */ +#define LL_I2C_ISR_TC I2C_ISR_TC /*!< Transfer Complete (master mode) */ +#define LL_I2C_ISR_TCR I2C_ISR_TCR /*!< Transfer Complete Reload */ +#define LL_I2C_ISR_BERR I2C_ISR_BERR /*!< Bus error */ +#define LL_I2C_ISR_ARLO I2C_ISR_ARLO /*!< Arbitration lost */ +#define LL_I2C_ISR_OVR I2C_ISR_OVR /*!< Overrun/Underrun (slave mode) */ +#define LL_I2C_ISR_PECERR I2C_ISR_PECERR /*!< PEC Error in reception (SMBus mode) */ +#define LL_I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT /*!< Timeout detection flag (SMBus mode) */ +#define LL_I2C_ISR_ALERT I2C_ISR_ALERT /*!< SMBus alert (SMBus mode) */ +#define LL_I2C_ISR_BUSY I2C_ISR_BUSY /*!< Bus busy */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions + * @{ + */ +#define LL_I2C_CR1_TXIE I2C_CR1_TXIE /*!< TX Interrupt enable */ +#define LL_I2C_CR1_RXIE I2C_CR1_RXIE /*!< RX Interrupt enable */ +#define LL_I2C_CR1_ADDRIE I2C_CR1_ADDRIE /*!< Address match Interrupt enable (slave only) */ +#define LL_I2C_CR1_NACKIE I2C_CR1_NACKIE /*!< Not acknowledge received Interrupt enable */ +#define LL_I2C_CR1_STOPIE I2C_CR1_STOPIE /*!< STOP detection Interrupt enable */ +#define LL_I2C_CR1_TCIE I2C_CR1_TCIE /*!< Transfer Complete interrupt enable */ +#define LL_I2C_CR1_ERRIE I2C_CR1_ERRIE /*!< Error interrupts enable */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode + * @{ + */ +#define LL_I2C_MODE_I2C 0x00000000U /*!< I2C Master or Slave mode */ +#define LL_I2C_MODE_SMBUS_HOST I2C_CR1_SMBHEN /*!< SMBus Host address acknowledge */ +#define LL_I2C_MODE_SMBUS_DEVICE 0x00000000U /*!< SMBus Device default mode + (Default address not acknowledge) */ +#define LL_I2C_MODE_SMBUS_DEVICE_ARP I2C_CR1_SMBDEN /*!< SMBus Device Default address acknowledge */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_ANALOGFILTER_SELECTION Analog Filter Selection + * @{ + */ +#define LL_I2C_ANALOGFILTER_ENABLE 0x00000000U /*!< Analog filter is enabled. */ +#define LL_I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF /*!< Analog filter is disabled. */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_ADDRESSING_MODE Master Addressing Mode + * @{ + */ +#define LL_I2C_ADDRESSING_MODE_7BIT 0x00000000U /*!< Master operates in 7-bit addressing mode. */ +#define LL_I2C_ADDRESSING_MODE_10BIT I2C_CR2_ADD10 /*!< Master operates in 10-bit addressing mode.*/ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length + * @{ + */ +#define LL_I2C_OWNADDRESS1_7BIT 0x00000000U /*!< Own address 1 is a 7-bit address. */ +#define LL_I2C_OWNADDRESS1_10BIT I2C_OAR1_OA1MODE /*!< Own address 1 is a 10-bit address.*/ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_OWNADDRESS2 Own Address 2 Masks + * @{ + */ +#define LL_I2C_OWNADDRESS2_NOMASK I2C_OAR2_OA2NOMASK /*!< Own Address2 No mask. */ +#define LL_I2C_OWNADDRESS2_MASK01 I2C_OAR2_OA2MASK01 /*!< Only Address2 bits[7:2] are compared. */ +#define LL_I2C_OWNADDRESS2_MASK02 I2C_OAR2_OA2MASK02 /*!< Only Address2 bits[7:3] are compared. */ +#define LL_I2C_OWNADDRESS2_MASK03 I2C_OAR2_OA2MASK03 /*!< Only Address2 bits[7:4] are compared. */ +#define LL_I2C_OWNADDRESS2_MASK04 I2C_OAR2_OA2MASK04 /*!< Only Address2 bits[7:5] are compared. */ +#define LL_I2C_OWNADDRESS2_MASK05 I2C_OAR2_OA2MASK05 /*!< Only Address2 bits[7:6] are compared. */ +#define LL_I2C_OWNADDRESS2_MASK06 I2C_OAR2_OA2MASK06 /*!< Only Address2 bits[7] are compared. */ +#define LL_I2C_OWNADDRESS2_MASK07 I2C_OAR2_OA2MASK07 /*!< No comparison is done. + All Address2 are acknowledged. */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation + * @{ + */ +#define LL_I2C_ACK 0x00000000U /*!< ACK is sent after current received byte. */ +#define LL_I2C_NACK I2C_CR2_NACK /*!< NACK is sent after current received byte.*/ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_ADDRSLAVE Slave Address Length + * @{ + */ +#define LL_I2C_ADDRSLAVE_7BIT 0x00000000U /*!< Slave Address in 7-bit. */ +#define LL_I2C_ADDRSLAVE_10BIT I2C_CR2_ADD10 /*!< Slave Address in 10-bit.*/ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_REQUEST Transfer Request Direction + * @{ + */ +#define LL_I2C_REQUEST_WRITE 0x00000000U /*!< Master request a write transfer. */ +#define LL_I2C_REQUEST_READ I2C_CR2_RD_WRN /*!< Master request a read transfer. */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_MODE Transfer End Mode + * @{ + */ +#define LL_I2C_MODE_RELOAD I2C_CR2_RELOAD /*!< Enable I2C Reload mode. */ +#define LL_I2C_MODE_AUTOEND I2C_CR2_AUTOEND /*!< Enable I2C Automatic end mode + with no HW PEC comparison. */ +#define LL_I2C_MODE_SOFTEND 0x00000000U /*!< Enable I2C Software end mode + with no HW PEC comparison. */ +#define LL_I2C_MODE_SMBUS_RELOAD LL_I2C_MODE_RELOAD /*!< Enable SMBUS Automatic end mode + with HW PEC comparison. */ +#define LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC LL_I2C_MODE_AUTOEND /*!< Enable SMBUS Automatic end mode + with HW PEC comparison. */ +#define LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC LL_I2C_MODE_SOFTEND /*!< Enable SMBUS Software end mode + with HW PEC comparison. */ +#define LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC (uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE) +/*!< Enable SMBUS Automatic end mode with HW PEC comparison. */ +#define LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC (uint32_t)(LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE) +/*!< Enable SMBUS Software end mode with HW PEC comparison. */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_GENERATE Start And Stop Generation + * @{ + */ +#define LL_I2C_GENERATE_NOSTARTSTOP 0x00000000U +/*!< Don't Generate Stop and Start condition. */ +#define LL_I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP) +/*!< Generate Stop condition (Size should be set to 0). */ +#define LL_I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) +/*!< Generate Start for read request. */ +#define LL_I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) +/*!< Generate Start for write request. */ +#define LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) +/*!< Generate Restart for read request, slave 7Bit address. */ +#define LL_I2C_GENERATE_RESTART_7BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) +/*!< Generate Restart for write request, slave 7Bit address. */ +#define LL_I2C_GENERATE_RESTART_10BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | \ + I2C_CR2_RD_WRN | I2C_CR2_HEAD10R) +/*!< Generate Restart for read request, slave 10Bit address. */ +#define LL_I2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) +/*!< Generate Restart for write request, slave 10Bit address.*/ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_DIRECTION Read Write Direction + * @{ + */ +#define LL_I2C_DIRECTION_WRITE 0x00000000U /*!< Write transfer request by master, + slave enters receiver mode. */ +#define LL_I2C_DIRECTION_READ I2C_ISR_DIR /*!< Read transfer request by master, + slave enters transmitter mode.*/ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_DMA_REG_DATA DMA Register Data + * @{ + */ +#define LL_I2C_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for + transmission */ +#define LL_I2C_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for + reception */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_SMBUS_TIMEOUTA_MODE SMBus TimeoutA Mode SCL SDA Timeout + * @{ + */ +#define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW 0x00000000U /*!< TimeoutA is used to detect + SCL low level timeout. */ +#define LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE /*!< TimeoutA is used to detect + both SCL and SDA high level timeout.*/ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_SMBUS_TIMEOUT_SELECTION SMBus Timeout Selection + * @{ + */ +#define LL_I2C_SMBUS_TIMEOUTA I2C_TIMEOUTR_TIMOUTEN /*!< TimeoutA enable bit */ +#define LL_I2C_SMBUS_TIMEOUTB I2C_TIMEOUTR_TEXTEN /*!< TimeoutB (extended clock) + enable bit */ +#define LL_I2C_SMBUS_ALL_TIMEOUT (uint32_t)(I2C_TIMEOUTR_TIMOUTEN | \ + I2C_TIMEOUTR_TEXTEN) /*!< TimeoutA and TimeoutB +(extended clock) enable bits */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup I2C_LL_Exported_Macros I2C Exported Macros + * @{ + */ + +/** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in I2C register + * @param __INSTANCE__ I2C Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in I2C register + * @param __INSTANCE__ I2C Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup I2C_LL_EM_CONVERT_TIMINGS Convert SDA SCL timings + * @{ + */ +/** + * @brief Configure the SDA setup, hold time and the SCL high, low period. + * @param __PRESCALER__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. + * @param __SETUP_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. + (tscldel = (SCLDEL+1)xtpresc) + * @param __HOLD_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. + (tsdadel = SDADELxtpresc) + * @param __SCLH_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. + (tsclh = (SCLH+1)xtpresc) + * @param __SCLL_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. + (tscll = (SCLL+1)xtpresc) + * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF + */ +#define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __SETUP_TIME__, __HOLD_TIME__, __SCLH_PERIOD__, __SCLL_PERIOD__) \ + ((((uint32_t)(__PRESCALER__) << I2C_TIMINGR_PRESC_Pos) & I2C_TIMINGR_PRESC) | \ + (((uint32_t)(__SETUP_TIME__) << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL) | \ + (((uint32_t)(__HOLD_TIME__) << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL) | \ + (((uint32_t)(__SCLH_PERIOD__) << I2C_TIMINGR_SCLH_Pos) & I2C_TIMINGR_SCLH) | \ + (((uint32_t)(__SCLL_PERIOD__) << I2C_TIMINGR_SCLL_Pos) & I2C_TIMINGR_SCLL)) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup I2C_LL_Exported_Functions I2C Exported Functions + * @{ + */ + +/** @defgroup I2C_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Enable I2C peripheral (PE = 1). + * @rmtoll CR1 PE LL_I2C_Enable + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_PE); +} + +/** + * @brief Disable I2C peripheral (PE = 0). + * @note When PE = 0, the I2C SCL and SDA lines are released. + * Internal state machines and status bits are put back to their reset value. + * When cleared, PE must be kept low for at least 3 APB clock cycles. + * @rmtoll CR1 PE LL_I2C_Disable + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE); +} + +/** + * @brief Check if the I2C peripheral is enabled or disabled. + * @rmtoll CR1 PE LL_I2C_IsEnabled + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE)) ? 1UL : 0UL); +} + +/** + * @brief Configure Noise Filters (Analog and Digital). + * @note If the analog filter is also enabled, the digital filter is added to analog filter. + * The filters can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll CR1 ANFOFF LL_I2C_ConfigFilters\n + * CR1 DNF LL_I2C_ConfigFilters + * @param I2Cx I2C Instance. + * @param AnalogFilter This parameter can be one of the following values: + * @arg @ref LL_I2C_ANALOGFILTER_ENABLE + * @arg @ref LL_I2C_ANALOGFILTER_DISABLE + * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) + and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk). + * This parameter is used to configure the digital noise filter on SDA and SCL input. + * The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter) +{ + MODIFY_REG(I2Cx->CR1, I2C_CR1_ANFOFF | I2C_CR1_DNF, AnalogFilter | (DigitalFilter << I2C_CR1_DNF_Pos)); +} + +/** + * @brief Configure Digital Noise Filter. + * @note If the analog filter is also enabled, the digital filter is added to analog filter. + * This filter can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll CR1 DNF LL_I2C_SetDigitalFilter + * @param I2Cx I2C Instance. + * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) + and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk). + * This parameter is used to configure the digital noise filter on SDA and SCL input. + * The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk. + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t DigitalFilter) +{ + MODIFY_REG(I2Cx->CR1, I2C_CR1_DNF, DigitalFilter << I2C_CR1_DNF_Pos); +} + +/** + * @brief Get the current Digital Noise Filter configuration. + * @rmtoll CR1 DNF LL_I2C_GetDigitalFilter + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x0 and Max_Data=0xF + */ +__STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_DNF) >> I2C_CR1_DNF_Pos); +} + +/** + * @brief Enable Analog Noise Filter. + * @note This filter can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll CR1 ANFOFF LL_I2C_EnableAnalogFilter + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableAnalogFilter(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_ANFOFF); +} + +/** + * @brief Disable Analog Noise Filter. + * @note This filter can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll CR1 ANFOFF LL_I2C_DisableAnalogFilter + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_ANFOFF); +} + +/** + * @brief Check if Analog Noise Filter is enabled or disabled. + * @rmtoll CR1 ANFOFF LL_I2C_IsEnabledAnalogFilter + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_ANFOFF) != (I2C_CR1_ANFOFF)) ? 1UL : 0UL); +} + +/** + * @brief Enable DMA transmission requests. + * @rmtoll CR1 TXDMAEN LL_I2C_EnableDMAReq_TX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN); +} + +/** + * @brief Disable DMA transmission requests. + * @rmtoll CR1 TXDMAEN LL_I2C_DisableDMAReq_TX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN); +} + +/** + * @brief Check if DMA transmission requests are enabled or disabled. + * @rmtoll CR1 TXDMAEN LL_I2C_IsEnabledDMAReq_TX + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN) == (I2C_CR1_TXDMAEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable DMA reception requests. + * @rmtoll CR1 RXDMAEN LL_I2C_EnableDMAReq_RX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN); +} + +/** + * @brief Disable DMA reception requests. + * @rmtoll CR1 RXDMAEN LL_I2C_DisableDMAReq_RX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN); +} + +/** + * @brief Check if DMA reception requests are enabled or disabled. + * @rmtoll CR1 RXDMAEN LL_I2C_IsEnabledDMAReq_RX + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN) == (I2C_CR1_RXDMAEN)) ? 1UL : 0UL); +} + +/** + * @brief Get the data register address used for DMA transfer + * @rmtoll TXDR TXDATA LL_I2C_DMA_GetRegAddr\n + * RXDR RXDATA LL_I2C_DMA_GetRegAddr + * @param I2Cx I2C Instance + * @param Direction This parameter can be one of the following values: + * @arg @ref LL_I2C_DMA_REG_DATA_TRANSMIT + * @arg @ref LL_I2C_DMA_REG_DATA_RECEIVE + * @retval Address of data register + */ +__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx, uint32_t Direction) +{ + uint32_t data_reg_addr; + + if (Direction == LL_I2C_DMA_REG_DATA_TRANSMIT) + { + /* return address of TXDR register */ + data_reg_addr = (uint32_t) &(I2Cx->TXDR); + } + else + { + /* return address of RXDR register */ + data_reg_addr = (uint32_t) &(I2Cx->RXDR); + } + + return data_reg_addr; +} + +/** + * @brief Enable Clock stretching. + * @note This bit can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll CR1 NOSTRETCH LL_I2C_EnableClockStretching + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH); +} + +/** + * @brief Disable Clock stretching. + * @note This bit can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll CR1 NOSTRETCH LL_I2C_DisableClockStretching + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH); +} + +/** + * @brief Check if Clock stretching is enabled or disabled. + * @rmtoll CR1 NOSTRETCH LL_I2C_IsEnabledClockStretching + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH)) ? 1UL : 0UL); +} + +/** + * @brief Enable hardware byte control in slave mode. + * @rmtoll CR1 SBC LL_I2C_EnableSlaveByteControl + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableSlaveByteControl(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_SBC); +} + +/** + * @brief Disable hardware byte control in slave mode. + * @rmtoll CR1 SBC LL_I2C_DisableSlaveByteControl + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableSlaveByteControl(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_SBC); +} + +/** + * @brief Check if hardware byte control in slave mode is enabled or disabled. + * @rmtoll CR1 SBC LL_I2C_IsEnabledSlaveByteControl + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_SBC) == (I2C_CR1_SBC)) ? 1UL : 0UL); +} + +/** + * @brief Enable Wakeup from STOP. + * @note The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not + * WakeUpFromStop feature is supported by the I2Cx Instance. + * @note This bit can only be programmed when Digital Filter is disabled. + * @rmtoll CR1 WUPEN LL_I2C_EnableWakeUpFromStop + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableWakeUpFromStop(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_WUPEN); +} + +/** + * @brief Disable Wakeup from STOP. + * @note The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not + * WakeUpFromStop feature is supported by the I2Cx Instance. + * @rmtoll CR1 WUPEN LL_I2C_DisableWakeUpFromStop + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableWakeUpFromStop(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_WUPEN); +} + +/** + * @brief Check if Wakeup from STOP is enabled or disabled. + * @note The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not + * WakeUpFromStop feature is supported by the I2Cx Instance. + * @rmtoll CR1 WUPEN LL_I2C_IsEnabledWakeUpFromStop + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_WUPEN) == (I2C_CR1_WUPEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable General Call. + * @note When enabled the Address 0x00 is ACKed. + * @rmtoll CR1 GCEN LL_I2C_EnableGeneralCall + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_GCEN); +} + +/** + * @brief Disable General Call. + * @note When disabled the Address 0x00 is NACKed. + * @rmtoll CR1 GCEN LL_I2C_DisableGeneralCall + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_GCEN); +} + +/** + * @brief Check if General Call is enabled or disabled. + * @rmtoll CR1 GCEN LL_I2C_IsEnabledGeneralCall + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN)) ? 1UL : 0UL); +} + +/** + * @brief Configure the Master to operate in 7-bit or 10-bit addressing mode. + * @note Changing this bit is not allowed, when the START bit is set. + * @rmtoll CR2 ADD10 LL_I2C_SetMasterAddressingMode + * @param I2Cx I2C Instance. + * @param AddressingMode This parameter can be one of the following values: + * @arg @ref LL_I2C_ADDRESSING_MODE_7BIT + * @arg @ref LL_I2C_ADDRESSING_MODE_10BIT + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetMasterAddressingMode(I2C_TypeDef *I2Cx, uint32_t AddressingMode) +{ + MODIFY_REG(I2Cx->CR2, I2C_CR2_ADD10, AddressingMode); +} + +/** + * @brief Get the Master addressing mode. + * @rmtoll CR2 ADD10 LL_I2C_GetMasterAddressingMode + * @param I2Cx I2C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2C_ADDRESSING_MODE_7BIT + * @arg @ref LL_I2C_ADDRESSING_MODE_10BIT + */ +__STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_ADD10)); +} + +/** + * @brief Set the Own Address1. + * @rmtoll OAR1 OA1 LL_I2C_SetOwnAddress1\n + * OAR1 OA1MODE LL_I2C_SetOwnAddress1 + * @param I2Cx I2C Instance. + * @param OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF. + * @param OwnAddrSize This parameter can be one of the following values: + * @arg @ref LL_I2C_OWNADDRESS1_7BIT + * @arg @ref LL_I2C_OWNADDRESS1_10BIT + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize) +{ + MODIFY_REG(I2Cx->OAR1, I2C_OAR1_OA1 | I2C_OAR1_OA1MODE, OwnAddress1 | OwnAddrSize); +} + +/** + * @brief Enable acknowledge on Own Address1 match address. + * @rmtoll OAR1 OA1EN LL_I2C_EnableOwnAddress1 + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableOwnAddress1(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN); +} + +/** + * @brief Disable acknowledge on Own Address1 match address. + * @rmtoll OAR1 OA1EN LL_I2C_DisableOwnAddress1 + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableOwnAddress1(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN); +} + +/** + * @brief Check if Own Address1 acknowledge is enabled or disabled. + * @rmtoll OAR1 OA1EN LL_I2C_IsEnabledOwnAddress1 + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN) == (I2C_OAR1_OA1EN)) ? 1UL : 0UL); +} + +/** + * @brief Set the 7bits Own Address2. + * @note This action has no effect if own address2 is enabled. + * @rmtoll OAR2 OA2 LL_I2C_SetOwnAddress2\n + * OAR2 OA2MSK LL_I2C_SetOwnAddress2 + * @param I2Cx I2C Instance. + * @param OwnAddress2 Value between Min_Data=0 and Max_Data=0x7F. + * @param OwnAddrMask This parameter can be one of the following values: + * @arg @ref LL_I2C_OWNADDRESS2_NOMASK + * @arg @ref LL_I2C_OWNADDRESS2_MASK01 + * @arg @ref LL_I2C_OWNADDRESS2_MASK02 + * @arg @ref LL_I2C_OWNADDRESS2_MASK03 + * @arg @ref LL_I2C_OWNADDRESS2_MASK04 + * @arg @ref LL_I2C_OWNADDRESS2_MASK05 + * @arg @ref LL_I2C_OWNADDRESS2_MASK06 + * @arg @ref LL_I2C_OWNADDRESS2_MASK07 + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2, uint32_t OwnAddrMask) +{ + MODIFY_REG(I2Cx->OAR2, I2C_OAR2_OA2 | I2C_OAR2_OA2MSK, OwnAddress2 | OwnAddrMask); +} + +/** + * @brief Enable acknowledge on Own Address2 match address. + * @rmtoll OAR2 OA2EN LL_I2C_EnableOwnAddress2 + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN); +} + +/** + * @brief Disable acknowledge on Own Address2 match address. + * @rmtoll OAR2 OA2EN LL_I2C_DisableOwnAddress2 + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN); +} + +/** + * @brief Check if Own Address1 acknowledge is enabled or disabled. + * @rmtoll OAR2 OA2EN LL_I2C_IsEnabledOwnAddress2 + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN) == (I2C_OAR2_OA2EN)) ? 1UL : 0UL); +} + +/** + * @brief Configure the SDA setup, hold time and the SCL high, low period. + * @note This bit can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll TIMINGR TIMINGR LL_I2C_SetTiming + * @param I2Cx I2C Instance. + * @param Timing This parameter must be a value between Min_Data=0 and Max_Data=0xFFFFFFFF. + * @note This parameter is computed with the STM32CubeMX Tool. + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetTiming(I2C_TypeDef *I2Cx, uint32_t Timing) +{ + WRITE_REG(I2Cx->TIMINGR, Timing); +} + +/** + * @brief Get the Timing Prescaler setting. + * @rmtoll TIMINGR PRESC LL_I2C_GetTimingPrescaler + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x0 and Max_Data=0xF + */ +__STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC) >> I2C_TIMINGR_PRESC_Pos); +} + +/** + * @brief Get the SCL low period setting. + * @rmtoll TIMINGR SCLL LL_I2C_GetClockLowPeriod + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL) >> I2C_TIMINGR_SCLL_Pos); +} + +/** + * @brief Get the SCL high period setting. + * @rmtoll TIMINGR SCLH LL_I2C_GetClockHighPeriod + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH) >> I2C_TIMINGR_SCLH_Pos); +} + +/** + * @brief Get the SDA hold time. + * @rmtoll TIMINGR SDADEL LL_I2C_GetDataHoldTime + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x0 and Max_Data=0xF + */ +__STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL) >> I2C_TIMINGR_SDADEL_Pos); +} + +/** + * @brief Get the SDA setup time. + * @rmtoll TIMINGR SCLDEL LL_I2C_GetDataSetupTime + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x0 and Max_Data=0xF + */ +__STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL) >> I2C_TIMINGR_SCLDEL_Pos); +} + +/** + * @brief Configure peripheral mode. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll CR1 SMBHEN LL_I2C_SetMode\n + * CR1 SMBDEN LL_I2C_SetMode + * @param I2Cx I2C Instance. + * @param PeripheralMode This parameter can be one of the following values: + * @arg @ref LL_I2C_MODE_I2C + * @arg @ref LL_I2C_MODE_SMBUS_HOST + * @arg @ref LL_I2C_MODE_SMBUS_DEVICE + * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode) +{ + MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN, PeripheralMode); +} + +/** + * @brief Get peripheral mode. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll CR1 SMBHEN LL_I2C_GetMode\n + * CR1 SMBDEN LL_I2C_GetMode + * @param I2Cx I2C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2C_MODE_I2C + * @arg @ref LL_I2C_MODE_SMBUS_HOST + * @arg @ref LL_I2C_MODE_SMBUS_DEVICE + * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP + */ +__STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN)); +} + +/** + * @brief Enable SMBus alert (Host or Device mode) + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note SMBus Device mode: + * - SMBus Alert pin is drived low and + * Alert Response Address Header acknowledge is enabled. + * SMBus Host mode: + * - SMBus Alert pin management is supported. + * @rmtoll CR1 ALERTEN LL_I2C_EnableSMBusAlert + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_ALERTEN); +} + +/** + * @brief Disable SMBus alert (Host or Device mode) + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note SMBus Device mode: + * - SMBus Alert pin is not drived (can be used as a standard GPIO) and + * Alert Response Address Header acknowledge is disabled. + * SMBus Host mode: + * - SMBus Alert pin management is not supported. + * @rmtoll CR1 ALERTEN LL_I2C_DisableSMBusAlert + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERTEN); +} + +/** + * @brief Check if SMBus alert (Host or Device mode) is enabled or disabled. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll CR1 ALERTEN LL_I2C_IsEnabledSMBusAlert + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_ALERTEN) == (I2C_CR1_ALERTEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable SMBus Packet Error Calculation (PEC). + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll CR1 PECEN LL_I2C_EnableSMBusPEC + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_PECEN); +} + +/** + * @brief Disable SMBus Packet Error Calculation (PEC). + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll CR1 PECEN LL_I2C_DisableSMBusPEC + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_PECEN); +} + +/** + * @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll CR1 PECEN LL_I2C_IsEnabledSMBusPEC + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_PECEN) == (I2C_CR1_PECEN)) ? 1UL : 0UL); +} + +/** + * @brief Configure the SMBus Clock Timeout. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB). + * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_ConfigSMBusTimeout\n + * TIMEOUTR TIDLE LL_I2C_ConfigSMBusTimeout\n + * TIMEOUTR TIMEOUTB LL_I2C_ConfigSMBusTimeout + * @param I2Cx I2C Instance. + * @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF. + * @param TimeoutAMode This parameter can be one of the following values: + * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW + * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH + * @param TimeoutB + * @retval None + */ +__STATIC_INLINE void LL_I2C_ConfigSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t TimeoutA, uint32_t TimeoutAMode, + uint32_t TimeoutB) +{ + MODIFY_REG(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA | I2C_TIMEOUTR_TIDLE | I2C_TIMEOUTR_TIMEOUTB, + TimeoutA | TimeoutAMode | (TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos)); +} + +/** + * @brief Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode). + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note These bits can only be programmed when TimeoutA is disabled. + * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_SetSMBusTimeoutA + * @param I2Cx I2C Instance. + * @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF. + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetSMBusTimeoutA(I2C_TypeDef *I2Cx, uint32_t TimeoutA) +{ + WRITE_REG(I2Cx->TIMEOUTR, TimeoutA); +} + +/** + * @brief Get the SMBus Clock TimeoutA setting. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_GetSMBusTimeoutA + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0 and Max_Data=0xFFF + */ +__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA)); +} + +/** + * @brief Set the SMBus Clock TimeoutA mode. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note This bit can only be programmed when TimeoutA is disabled. + * @rmtoll TIMEOUTR TIDLE LL_I2C_SetSMBusTimeoutAMode + * @param I2Cx I2C Instance. + * @param TimeoutAMode This parameter can be one of the following values: + * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW + * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef *I2Cx, uint32_t TimeoutAMode) +{ + WRITE_REG(I2Cx->TIMEOUTR, TimeoutAMode); +} + +/** + * @brief Get the SMBus Clock TimeoutA mode. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll TIMEOUTR TIDLE LL_I2C_GetSMBusTimeoutAMode + * @param I2Cx I2C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW + * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH + */ +__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIDLE)); +} + +/** + * @brief Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode). + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note These bits can only be programmed when TimeoutB is disabled. + * @rmtoll TIMEOUTR TIMEOUTB LL_I2C_SetSMBusTimeoutB + * @param I2Cx I2C Instance. + * @param TimeoutB This parameter must be a value between Min_Data=0 and Max_Data=0xFFF. + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t TimeoutB) +{ + WRITE_REG(I2Cx->TIMEOUTR, TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos); +} + +/** + * @brief Get the SMBus Extended Cumulative Clock TimeoutB setting. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll TIMEOUTR TIMEOUTB LL_I2C_GetSMBusTimeoutB + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0 and Max_Data=0xFFF + */ +__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB) >> I2C_TIMEOUTR_TIMEOUTB_Pos); +} + +/** + * @brief Enable the SMBus Clock Timeout. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_EnableSMBusTimeout\n + * TIMEOUTR TEXTEN LL_I2C_EnableSMBusTimeout + * @param I2Cx I2C Instance. + * @param ClockTimeout This parameter can be one of the following values: + * @arg @ref LL_I2C_SMBUS_TIMEOUTA + * @arg @ref LL_I2C_SMBUS_TIMEOUTB + * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout) +{ + SET_BIT(I2Cx->TIMEOUTR, ClockTimeout); +} + +/** + * @brief Disable the SMBus Clock Timeout. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_DisableSMBusTimeout\n + * TIMEOUTR TEXTEN LL_I2C_DisableSMBusTimeout + * @param I2Cx I2C Instance. + * @param ClockTimeout This parameter can be one of the following values: + * @arg @ref LL_I2C_SMBUS_TIMEOUTA + * @arg @ref LL_I2C_SMBUS_TIMEOUTB + * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout) +{ + CLEAR_BIT(I2Cx->TIMEOUTR, ClockTimeout); +} + +/** + * @brief Check if the SMBus Clock Timeout is enabled or disabled. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_IsEnabledSMBusTimeout\n + * TIMEOUTR TEXTEN LL_I2C_IsEnabledSMBusTimeout + * @param I2Cx I2C Instance. + * @param ClockTimeout This parameter can be one of the following values: + * @arg @ref LL_I2C_SMBUS_TIMEOUTA + * @arg @ref LL_I2C_SMBUS_TIMEOUTB + * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout) +{ + return ((READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == \ + (ClockTimeout)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup I2C_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable TXIS interrupt. + * @rmtoll CR1 TXIE LL_I2C_EnableIT_TX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_TXIE); +} + +/** + * @brief Disable TXIS interrupt. + * @rmtoll CR1 TXIE LL_I2C_DisableIT_TX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXIE); +} + +/** + * @brief Check if the TXIS Interrupt is enabled or disabled. + * @rmtoll CR1 TXIE LL_I2C_IsEnabledIT_TX + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable RXNE interrupt. + * @rmtoll CR1 RXIE LL_I2C_EnableIT_RX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_RXIE); +} + +/** + * @brief Disable RXNE interrupt. + * @rmtoll CR1 RXIE LL_I2C_DisableIT_RX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXIE); +} + +/** + * @brief Check if the RXNE Interrupt is enabled or disabled. + * @rmtoll CR1 RXIE LL_I2C_IsEnabledIT_RX + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXIE) == (I2C_CR1_RXIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable Address match interrupt (slave mode only). + * @rmtoll CR1 ADDRIE LL_I2C_EnableIT_ADDR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableIT_ADDR(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_ADDRIE); +} + +/** + * @brief Disable Address match interrupt (slave mode only). + * @rmtoll CR1 ADDRIE LL_I2C_DisableIT_ADDR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableIT_ADDR(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_ADDRIE); +} + +/** + * @brief Check if Address match interrupt is enabled or disabled. + * @rmtoll CR1 ADDRIE LL_I2C_IsEnabledIT_ADDR + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_ADDRIE) == (I2C_CR1_ADDRIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable Not acknowledge received interrupt. + * @rmtoll CR1 NACKIE LL_I2C_EnableIT_NACK + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableIT_NACK(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_NACKIE); +} + +/** + * @brief Disable Not acknowledge received interrupt. + * @rmtoll CR1 NACKIE LL_I2C_DisableIT_NACK + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableIT_NACK(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_NACKIE); +} + +/** + * @brief Check if Not acknowledge received interrupt is enabled or disabled. + * @rmtoll CR1 NACKIE LL_I2C_IsEnabledIT_NACK + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_NACKIE) == (I2C_CR1_NACKIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable STOP detection interrupt. + * @rmtoll CR1 STOPIE LL_I2C_EnableIT_STOP + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableIT_STOP(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_STOPIE); +} + +/** + * @brief Disable STOP detection interrupt. + * @rmtoll CR1 STOPIE LL_I2C_DisableIT_STOP + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableIT_STOP(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_STOPIE); +} + +/** + * @brief Check if STOP detection interrupt is enabled or disabled. + * @rmtoll CR1 STOPIE LL_I2C_IsEnabledIT_STOP + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_STOPIE) == (I2C_CR1_STOPIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable Transfer Complete interrupt. + * @note Any of these events will generate interrupt : + * Transfer Complete (TC) + * Transfer Complete Reload (TCR) + * @rmtoll CR1 TCIE LL_I2C_EnableIT_TC + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableIT_TC(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_TCIE); +} + +/** + * @brief Disable Transfer Complete interrupt. + * @note Any of these events will generate interrupt : + * Transfer Complete (TC) + * Transfer Complete Reload (TCR) + * @rmtoll CR1 TCIE LL_I2C_DisableIT_TC + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableIT_TC(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_TCIE); +} + +/** + * @brief Check if Transfer Complete interrupt is enabled or disabled. + * @rmtoll CR1 TCIE LL_I2C_IsEnabledIT_TC + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_TCIE) == (I2C_CR1_TCIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable Error interrupts. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note Any of these errors will generate interrupt : + * Arbitration Loss (ARLO) + * Bus Error detection (BERR) + * Overrun/Underrun (OVR) + * SMBus Timeout detection (TIMEOUT) + * SMBus PEC error detection (PECERR) + * SMBus Alert pin event detection (ALERT) + * @rmtoll CR1 ERRIE LL_I2C_EnableIT_ERR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_ERRIE); +} + +/** + * @brief Disable Error interrupts. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note Any of these errors will generate interrupt : + * Arbitration Loss (ARLO) + * Bus Error detection (BERR) + * Overrun/Underrun (OVR) + * SMBus Timeout detection (TIMEOUT) + * SMBus PEC error detection (PECERR) + * SMBus Alert pin event detection (ALERT) + * @rmtoll CR1 ERRIE LL_I2C_DisableIT_ERR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_ERRIE); +} + +/** + * @brief Check if Error interrupts are enabled or disabled. + * @rmtoll CR1 ERRIE LL_I2C_IsEnabledIT_ERR + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup I2C_LL_EF_FLAG_management FLAG_management + * @{ + */ + +/** + * @brief Indicate the status of Transmit data register empty flag. + * @note RESET: When next data is written in Transmit data register. + * SET: When Transmit data register is empty. + * @rmtoll ISR TXE LL_I2C_IsActiveFlag_TXE + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXE) == (I2C_ISR_TXE)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Transmit interrupt flag. + * @note RESET: When next data is written in Transmit data register. + * SET: When Transmit data register is empty. + * @rmtoll ISR TXIS LL_I2C_IsActiveFlag_TXIS + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXIS) == (I2C_ISR_TXIS)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Receive data register not empty flag. + * @note RESET: When Receive data register is read. + * SET: When the received data is copied in Receive data register. + * @rmtoll ISR RXNE LL_I2C_IsActiveFlag_RXNE + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_RXNE) == (I2C_ISR_RXNE)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Address matched flag (slave mode). + * @note RESET: Clear default value. + * SET: When the received slave address matched with one of the enabled slave address. + * @rmtoll ISR ADDR LL_I2C_IsActiveFlag_ADDR + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_ADDR) == (I2C_ISR_ADDR)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Not Acknowledge received flag. + * @note RESET: Clear default value. + * SET: When a NACK is received after a byte transmission. + * @rmtoll ISR NACKF LL_I2C_IsActiveFlag_NACK + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_NACKF) == (I2C_ISR_NACKF)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Stop detection flag. + * @note RESET: Clear default value. + * SET: When a Stop condition is detected. + * @rmtoll ISR STOPF LL_I2C_IsActiveFlag_STOP + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Transfer complete flag (master mode). + * @note RESET: Clear default value. + * SET: When RELOAD=0, AUTOEND=0 and NBYTES date have been transferred. + * @rmtoll ISR TC LL_I2C_IsActiveFlag_TC + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_TC) == (I2C_ISR_TC)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Transfer complete flag (master mode). + * @note RESET: Clear default value. + * SET: When RELOAD=1 and NBYTES date have been transferred. + * @rmtoll ISR TCR LL_I2C_IsActiveFlag_TCR + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_TCR) == (I2C_ISR_TCR)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Bus error flag. + * @note RESET: Clear default value. + * SET: When a misplaced Start or Stop condition is detected. + * @rmtoll ISR BERR LL_I2C_IsActiveFlag_BERR + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_BERR) == (I2C_ISR_BERR)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Arbitration lost flag. + * @note RESET: Clear default value. + * SET: When arbitration lost. + * @rmtoll ISR ARLO LL_I2C_IsActiveFlag_ARLO + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_ARLO) == (I2C_ISR_ARLO)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Overrun/Underrun flag (slave mode). + * @note RESET: Clear default value. + * SET: When an overrun/underrun error occurs (Clock Stretching Disabled). + * @rmtoll ISR OVR LL_I2C_IsActiveFlag_OVR + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_OVR) == (I2C_ISR_OVR)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of SMBus PEC error flag in reception. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note RESET: Clear default value. + * SET: When the received PEC does not match with the PEC register content. + * @rmtoll ISR PECERR LL_I2C_IsActiveSMBusFlag_PECERR + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_PECERR) == (I2C_ISR_PECERR)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of SMBus Timeout detection flag. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note RESET: Clear default value. + * SET: When a timeout or extended clock timeout occurs. + * @rmtoll ISR TIMEOUT LL_I2C_IsActiveSMBusFlag_TIMEOUT + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_TIMEOUT) == (I2C_ISR_TIMEOUT)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of SMBus alert flag. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note RESET: Clear default value. + * SET: When SMBus host configuration, SMBus alert enabled and + * a falling edge event occurs on SMBA pin. + * @rmtoll ISR ALERT LL_I2C_IsActiveSMBusFlag_ALERT + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_ALERT) == (I2C_ISR_ALERT)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Bus Busy flag. + * @note RESET: Clear default value. + * SET: When a Start condition is detected. + * @rmtoll ISR BUSY LL_I2C_IsActiveFlag_BUSY + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_BUSY) == (I2C_ISR_BUSY)) ? 1UL : 0UL); +} + +/** + * @brief Clear Address Matched flag. + * @rmtoll ICR ADDRCF LL_I2C_ClearFlag_ADDR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_ADDRCF); +} + +/** + * @brief Clear Not Acknowledge flag. + * @rmtoll ICR NACKCF LL_I2C_ClearFlag_NACK + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearFlag_NACK(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_NACKCF); +} + +/** + * @brief Clear Stop detection flag. + * @rmtoll ICR STOPCF LL_I2C_ClearFlag_STOP + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_STOPCF); +} + +/** + * @brief Clear Transmit data register empty flag (TXE). + * @note This bit can be clear by software in order to flush the transmit data register (TXDR). + * @rmtoll ISR TXE LL_I2C_ClearFlag_TXE + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearFlag_TXE(I2C_TypeDef *I2Cx) +{ + WRITE_REG(I2Cx->ISR, I2C_ISR_TXE); +} + +/** + * @brief Clear Bus error flag. + * @rmtoll ICR BERRCF LL_I2C_ClearFlag_BERR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_BERRCF); +} + +/** + * @brief Clear Arbitration lost flag. + * @rmtoll ICR ARLOCF LL_I2C_ClearFlag_ARLO + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_ARLOCF); +} + +/** + * @brief Clear Overrun/Underrun flag. + * @rmtoll ICR OVRCF LL_I2C_ClearFlag_OVR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_OVRCF); +} + +/** + * @brief Clear SMBus PEC error flag. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll ICR PECCF LL_I2C_ClearSMBusFlag_PECERR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_PECCF); +} + +/** + * @brief Clear SMBus Timeout detection flag. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll ICR TIMOUTCF LL_I2C_ClearSMBusFlag_TIMEOUT + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_TIMOUTCF); +} + +/** + * @brief Clear SMBus Alert flag. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll ICR ALERTCF LL_I2C_ClearSMBusFlag_ALERT + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_ALERTCF); +} + +/** + * @} + */ + +/** @defgroup I2C_LL_EF_Data_Management Data_Management + * @{ + */ + +/** + * @brief Enable automatic STOP condition generation (master mode). + * @note Automatic end mode : a STOP condition is automatically sent when NBYTES data are transferred. + * This bit has no effect in slave mode or when RELOAD bit is set. + * @rmtoll CR2 AUTOEND LL_I2C_EnableAutoEndMode + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableAutoEndMode(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR2, I2C_CR2_AUTOEND); +} + +/** + * @brief Disable automatic STOP condition generation (master mode). + * @note Software end mode : TC flag is set when NBYTES data are transferre, stretching SCL low. + * @rmtoll CR2 AUTOEND LL_I2C_DisableAutoEndMode + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableAutoEndMode(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR2, I2C_CR2_AUTOEND); +} + +/** + * @brief Check if automatic STOP condition is enabled or disabled. + * @rmtoll CR2 AUTOEND LL_I2C_IsEnabledAutoEndMode + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR2, I2C_CR2_AUTOEND) == (I2C_CR2_AUTOEND)) ? 1UL : 0UL); +} + +/** + * @brief Enable reload mode (master mode). + * @note The transfer is not completed after the NBYTES data transfer, NBYTES will be reloaded when TCR flag is set. + * @rmtoll CR2 RELOAD LL_I2C_EnableReloadMode + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableReloadMode(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR2, I2C_CR2_RELOAD); +} + +/** + * @brief Disable reload mode (master mode). + * @note The transfer is completed after the NBYTES data transfer(STOP or RESTART will follow). + * @rmtoll CR2 RELOAD LL_I2C_DisableReloadMode + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableReloadMode(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR2, I2C_CR2_RELOAD); +} + +/** + * @brief Check if reload mode is enabled or disabled. + * @rmtoll CR2 RELOAD LL_I2C_IsEnabledReloadMode + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR2, I2C_CR2_RELOAD) == (I2C_CR2_RELOAD)) ? 1UL : 0UL); +} + +/** + * @brief Configure the number of bytes for transfer. + * @note Changing these bits when START bit is set is not allowed. + * @rmtoll CR2 NBYTES LL_I2C_SetTransferSize + * @param I2Cx I2C Instance. + * @param TransferSize This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF. + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetTransferSize(I2C_TypeDef *I2Cx, uint32_t TransferSize) +{ + MODIFY_REG(I2Cx->CR2, I2C_CR2_NBYTES, TransferSize << I2C_CR2_NBYTES_Pos); +} + +/** + * @brief Get the number of bytes configured for transfer. + * @rmtoll CR2 NBYTES LL_I2C_GetTransferSize + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x0 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_I2C_GetTransferSize(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_NBYTES) >> I2C_CR2_NBYTES_Pos); +} + +/** + * @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code + or next received byte. + * @note Usage in Slave mode only. + * @rmtoll CR2 NACK LL_I2C_AcknowledgeNextData + * @param I2Cx I2C Instance. + * @param TypeAcknowledge This parameter can be one of the following values: + * @arg @ref LL_I2C_ACK + * @arg @ref LL_I2C_NACK + * @retval None + */ +__STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge) +{ + MODIFY_REG(I2Cx->CR2, I2C_CR2_NACK, TypeAcknowledge); +} + +/** + * @brief Generate a START or RESTART condition + * @note The START bit can be set even if bus is BUSY or I2C is in slave mode. + * This action has no effect when RELOAD is set. + * @rmtoll CR2 START LL_I2C_GenerateStartCondition + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR2, I2C_CR2_START); +} + +/** + * @brief Generate a STOP condition after the current byte transfer (master mode). + * @rmtoll CR2 STOP LL_I2C_GenerateStopCondition + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR2, I2C_CR2_STOP); +} + +/** + * @brief Enable automatic RESTART Read request condition for 10bit address header (master mode). + * @note The master sends the complete 10bit slave address read sequence : + * Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address + in Read direction. + * @rmtoll CR2 HEAD10R LL_I2C_EnableAuto10BitRead + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableAuto10BitRead(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR2, I2C_CR2_HEAD10R); +} + +/** + * @brief Disable automatic RESTART Read request condition for 10bit address header (master mode). + * @note The master only sends the first 7 bits of 10bit address in Read direction. + * @rmtoll CR2 HEAD10R LL_I2C_DisableAuto10BitRead + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableAuto10BitRead(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR2, I2C_CR2_HEAD10R); +} + +/** + * @brief Check if automatic RESTART Read request condition for 10bit address header is enabled or disabled. + * @rmtoll CR2 HEAD10R LL_I2C_IsEnabledAuto10BitRead + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR2, I2C_CR2_HEAD10R) != (I2C_CR2_HEAD10R)) ? 1UL : 0UL); +} + +/** + * @brief Configure the transfer direction (master mode). + * @note Changing these bits when START bit is set is not allowed. + * @rmtoll CR2 RD_WRN LL_I2C_SetTransferRequest + * @param I2Cx I2C Instance. + * @param TransferRequest This parameter can be one of the following values: + * @arg @ref LL_I2C_REQUEST_WRITE + * @arg @ref LL_I2C_REQUEST_READ + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetTransferRequest(I2C_TypeDef *I2Cx, uint32_t TransferRequest) +{ + MODIFY_REG(I2Cx->CR2, I2C_CR2_RD_WRN, TransferRequest); +} + +/** + * @brief Get the transfer direction requested (master mode). + * @rmtoll CR2 RD_WRN LL_I2C_GetTransferRequest + * @param I2Cx I2C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2C_REQUEST_WRITE + * @arg @ref LL_I2C_REQUEST_READ + */ +__STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_RD_WRN)); +} + +/** + * @brief Configure the slave address for transfer (master mode). + * @note Changing these bits when START bit is set is not allowed. + * @rmtoll CR2 SADD LL_I2C_SetSlaveAddr + * @param I2Cx I2C Instance. + * @param SlaveAddr This parameter must be a value between Min_Data=0x00 and Max_Data=0x3F. + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetSlaveAddr(I2C_TypeDef *I2Cx, uint32_t SlaveAddr) +{ + MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD, SlaveAddr); +} + +/** + * @brief Get the slave address programmed for transfer. + * @rmtoll CR2 SADD LL_I2C_GetSlaveAddr + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x0 and Max_Data=0x3F + */ +__STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_SADD)); +} + +/** + * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set). + * @rmtoll CR2 SADD LL_I2C_HandleTransfer\n + * CR2 ADD10 LL_I2C_HandleTransfer\n + * CR2 RD_WRN LL_I2C_HandleTransfer\n + * CR2 START LL_I2C_HandleTransfer\n + * CR2 STOP LL_I2C_HandleTransfer\n + * CR2 RELOAD LL_I2C_HandleTransfer\n + * CR2 NBYTES LL_I2C_HandleTransfer\n + * CR2 AUTOEND LL_I2C_HandleTransfer\n + * CR2 HEAD10R LL_I2C_HandleTransfer + * @param I2Cx I2C Instance. + * @param SlaveAddr Specifies the slave address to be programmed. + * @param SlaveAddrSize This parameter can be one of the following values: + * @arg @ref LL_I2C_ADDRSLAVE_7BIT + * @arg @ref LL_I2C_ADDRSLAVE_10BIT + * @param TransferSize Specifies the number of bytes to be programmed. + * This parameter must be a value between Min_Data=0 and Max_Data=255. + * @param EndMode This parameter can be one of the following values: + * @arg @ref LL_I2C_MODE_RELOAD + * @arg @ref LL_I2C_MODE_AUTOEND + * @arg @ref LL_I2C_MODE_SOFTEND + * @arg @ref LL_I2C_MODE_SMBUS_RELOAD + * @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC + * @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC + * @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC + * @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC + * @param Request This parameter can be one of the following values: + * @arg @ref LL_I2C_GENERATE_NOSTARTSTOP + * @arg @ref LL_I2C_GENERATE_STOP + * @arg @ref LL_I2C_GENERATE_START_READ + * @arg @ref LL_I2C_GENERATE_START_WRITE + * @arg @ref LL_I2C_GENERATE_RESTART_7BIT_READ + * @arg @ref LL_I2C_GENERATE_RESTART_7BIT_WRITE + * @arg @ref LL_I2C_GENERATE_RESTART_10BIT_READ + * @arg @ref LL_I2C_GENERATE_RESTART_10BIT_WRITE + * @retval None + */ +__STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize, + uint32_t TransferSize, uint32_t EndMode, uint32_t Request) +{ + MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 | + (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | + I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD | + I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R, + SlaveAddr | SlaveAddrSize | (TransferSize << I2C_CR2_NBYTES_Pos) | EndMode | Request); +} + +/** + * @brief Indicate the value of transfer direction (slave mode). + * @note RESET: Write transfer, Slave enters in receiver mode. + * SET: Read transfer, Slave enters in transmitter mode. + * @rmtoll ISR DIR LL_I2C_GetTransferDirection + * @param I2Cx I2C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2C_DIRECTION_WRITE + * @arg @ref LL_I2C_DIRECTION_READ + */ +__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_DIR)); +} + +/** + * @brief Return the slave matched address. + * @rmtoll ISR ADDCODE LL_I2C_GetAddressMatchCode + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x00 and Max_Data=0x3F + */ +__STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_ADDCODE) >> I2C_ISR_ADDCODE_Pos << 1); +} + +/** + * @brief Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode). + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition + or an Address Matched is received. + * This bit has no effect when RELOAD bit is set. + * This bit has no effect in device mode when SBC bit is not set. + * @rmtoll CR2 PECBYTE LL_I2C_EnableSMBusPECCompare + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR2, I2C_CR2_PECBYTE); +} + +/** + * @brief Check if the SMBus Packet Error byte internal comparison is requested or not. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll CR2 PECBYTE LL_I2C_IsEnabledSMBusPECCompare + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR2, I2C_CR2_PECBYTE) == (I2C_CR2_PECBYTE)) ? 1UL : 0UL); +} + +/** + * @brief Get the SMBus Packet Error byte calculated. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll PECR PEC LL_I2C_GetSMBusPEC + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->PECR, I2C_PECR_PEC)); +} + +/** + * @brief Read Receive Data register. + * @rmtoll RXDR RXDATA LL_I2C_ReceiveData8 + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx) +{ + return (uint8_t)(READ_BIT(I2Cx->RXDR, I2C_RXDR_RXDATA)); +} + +/** + * @brief Write in Transmit Data Register . + * @rmtoll TXDR TXDATA LL_I2C_TransmitData8 + * @param I2Cx I2C Instance. + * @param Data Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data) +{ + WRITE_REG(I2Cx->TXDR, Data); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct); +ErrorStatus LL_I2C_DeInit(I2C_TypeDef *I2Cx); +void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct); + + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* I2C1 || I2C2 || I2C3 || I2C4 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32L4xx_LL_I2C_H */ diff --git a/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_pwr.h b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_pwr.h new file mode 100644 index 0000000..4660f30 --- /dev/null +++ b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_pwr.h @@ -0,0 +1,1675 @@ +/** + ****************************************************************************** + * @file stm32l4xx_ll_pwr.h + * @author MCD Application Team + * @brief Header file of PWR LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32L4xx_LL_PWR_H +#define STM32L4xx_LL_PWR_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx.h" + +/** @addtogroup STM32L4xx_LL_Driver + * @{ + */ + +#if defined(PWR) + +/** @defgroup PWR_LL PWR + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup PWR_LL_Exported_Constants PWR Exported Constants + * @{ + */ + +/** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_PWR_WriteReg function + * @{ + */ +#define LL_PWR_SCR_CSBF PWR_SCR_CSBF +#define LL_PWR_SCR_CWUF PWR_SCR_CWUF +#define LL_PWR_SCR_CWUF5 PWR_SCR_CWUF5 +#define LL_PWR_SCR_CWUF4 PWR_SCR_CWUF4 +#define LL_PWR_SCR_CWUF3 PWR_SCR_CWUF3 +#define LL_PWR_SCR_CWUF2 PWR_SCR_CWUF2 +#define LL_PWR_SCR_CWUF1 PWR_SCR_CWUF1 +/** + * @} + */ + +/** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_PWR_ReadReg function + * @{ + */ +#define LL_PWR_SR1_WUFI PWR_SR1_WUFI +#if defined(PWR_SR1_EXT_SMPS_RDY) +#define LL_PWR_SR1_EXT_SMPS_RDY PWR_SR1_EXT_SMPS_RDY +#endif /* PWR_SR1_EXT_SMPS_RDY */ +#define LL_PWR_SR1_SBF PWR_SR1_SBF +#define LL_PWR_SR1_WUF5 PWR_SR1_WUF5 +#define LL_PWR_SR1_WUF4 PWR_SR1_WUF4 +#define LL_PWR_SR1_WUF3 PWR_SR1_WUF3 +#define LL_PWR_SR1_WUF2 PWR_SR1_WUF2 +#define LL_PWR_SR1_WUF1 PWR_SR1_WUF1 +#if defined(PWR_SR2_PVMO4) +#define LL_PWR_SR2_PVMO4 PWR_SR2_PVMO4 +#endif /* PWR_SR2_PVMO4 */ +#if defined(PWR_SR2_PVMO3) +#define LL_PWR_SR2_PVMO3 PWR_SR2_PVMO3 +#endif /* PWR_SR2_PVMO3 */ +#if defined(PWR_SR2_PVMO2) +#define LL_PWR_SR2_PVMO2 PWR_SR2_PVMO2 +#endif /* PWR_SR2_PVMO2 */ +#if defined(PWR_SR2_PVMO1) +#define LL_PWR_SR2_PVMO1 PWR_SR2_PVMO1 +#endif /* PWR_SR2_PVMO1 */ +#define LL_PWR_SR2_PVDO PWR_SR2_PVDO +#define LL_PWR_SR2_VOSF PWR_SR2_VOSF +#define LL_PWR_SR2_REGLPF PWR_SR2_REGLPF +#define LL_PWR_SR2_REGLPS PWR_SR2_REGLPS +/** + * @} + */ + +/** @defgroup PWR_LL_EC_REGU_VOLTAGE REGU VOLTAGE + * @{ + */ +#define LL_PWR_REGU_VOLTAGE_SCALE1 (PWR_CR1_VOS_0) +#define LL_PWR_REGU_VOLTAGE_SCALE2 (PWR_CR1_VOS_1) +/** + * @} + */ + +/** @defgroup PWR_LL_EC_MODE_PWR MODE PWR + * @{ + */ +#define LL_PWR_MODE_STOP0 (PWR_CR1_LPMS_STOP0) +#define LL_PWR_MODE_STOP1 (PWR_CR1_LPMS_STOP1) +#define LL_PWR_MODE_STOP2 (PWR_CR1_LPMS_STOP2) +#define LL_PWR_MODE_STANDBY (PWR_CR1_LPMS_STANDBY) +#define LL_PWR_MODE_SHUTDOWN (PWR_CR1_LPMS_SHUTDOWN) +/** + * @} + */ + +/** @defgroup PWR_LL_EC_PVM_VDDUSB_1 Peripheral voltage monitoring + * @{ + */ +#if defined(PWR_CR2_PVME1) +#define LL_PWR_PVM_VDDUSB_1_2V (PWR_CR2_PVME1) /* Monitoring VDDUSB vs. 1.2V */ +#endif +#if defined(PWR_CR2_PVME2) +#define LL_PWR_PVM_VDDIO2_0_9V (PWR_CR2_PVME2) /* Monitoring VDDIO2 vs. 0.9V */ +#endif +#if defined(PWR_CR2_PVME3) +#define LL_PWR_PVM_VDDA_1_62V (PWR_CR2_PVME3) /* Monitoring VDDA vs. 1.62V */ +#endif +#if defined(PWR_CR2_PVME4) +#define LL_PWR_PVM_VDDA_2_2V (PWR_CR2_PVME4) /* Monitoring VDDA vs. 2.2V */ +#endif +/** + * @} + */ + +/** @defgroup PWR_LL_EC_PVDLEVEL PVDLEVEL + * @{ + */ +#define LL_PWR_PVDLEVEL_0 (PWR_CR2_PLS_LEV0) /* VPVD0 around 2.0 V */ +#define LL_PWR_PVDLEVEL_1 (PWR_CR2_PLS_LEV1) /* VPVD1 around 2.2 V */ +#define LL_PWR_PVDLEVEL_2 (PWR_CR2_PLS_LEV2) /* VPVD2 around 2.4 V */ +#define LL_PWR_PVDLEVEL_3 (PWR_CR2_PLS_LEV3) /* VPVD3 around 2.5 V */ +#define LL_PWR_PVDLEVEL_4 (PWR_CR2_PLS_LEV4) /* VPVD4 around 2.6 V */ +#define LL_PWR_PVDLEVEL_5 (PWR_CR2_PLS_LEV5) /* VPVD5 around 2.8 V */ +#define LL_PWR_PVDLEVEL_6 (PWR_CR2_PLS_LEV6) /* VPVD6 around 2.9 V */ +#define LL_PWR_PVDLEVEL_7 (PWR_CR2_PLS_LEV7) /* External input analog voltage (Compare internally to VREFINT) */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_WAKEUP WAKEUP + * @{ + */ +#define LL_PWR_WAKEUP_PIN1 (PWR_CR3_EWUP1) +#define LL_PWR_WAKEUP_PIN2 (PWR_CR3_EWUP2) +#define LL_PWR_WAKEUP_PIN3 (PWR_CR3_EWUP3) +#define LL_PWR_WAKEUP_PIN4 (PWR_CR3_EWUP4) +#define LL_PWR_WAKEUP_PIN5 (PWR_CR3_EWUP5) +/** + * @} + */ + +/** @defgroup PWR_LL_EC_BATT_CHARG_RESISTOR BATT CHARG RESISTOR + * @{ + */ +#define LL_PWR_BATT_CHARG_RESISTOR_5K (0x00000000U) +#define LL_PWR_BATT_CHARGRESISTOR_1_5K (PWR_CR4_VBRS) +/** + * @} + */ + +/** @defgroup PWR_LL_EC_SRAM2_CONTENT_RETENTION SRAM2 CONTENT RETENTION + * @{ + */ +#define LL_PWR_NO_SRAM2_RETENTION (0x00000000U) +#if defined(PWR_CR3_RRS_1) +#define LL_PWR_FULL_SRAM2_RETENTION PWR_CR3_RRS_0 +#define LL_PWR_4KBYTES_SRAM2_RETENTION PWR_CR3_RRS_1 +#else +#define LL_PWR_FULL_SRAM2_RETENTION PWR_CR3_RRS +#endif /* PWR_CR3_RRS_1 */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_GPIO GPIO + * @{ + */ +#define LL_PWR_GPIO_A ((uint32_t)(&(PWR->PUCRA))) +#define LL_PWR_GPIO_B ((uint32_t)(&(PWR->PUCRB))) +#define LL_PWR_GPIO_C ((uint32_t)(&(PWR->PUCRC))) +#define LL_PWR_GPIO_D ((uint32_t)(&(PWR->PUCRD))) +#define LL_PWR_GPIO_E ((uint32_t)(&(PWR->PUCRE))) +#if defined(GPIOF) +#define LL_PWR_GPIO_F ((uint32_t)(&(PWR->PUCRF))) +#endif +#if defined(GPIOG) +#define LL_PWR_GPIO_G ((uint32_t)(&(PWR->PUCRG))) +#endif +#if defined(GPIOH) +#define LL_PWR_GPIO_H ((uint32_t)(&(PWR->PUCRH))) +#endif +#if defined(GPIOI) +#define LL_PWR_GPIO_I ((uint32_t)(&(PWR->PUCRI))) +#endif +/** + * @} + */ + +/** @defgroup PWR_LL_EC_GPIO_BIT GPIO BIT + * @{ + */ +#define LL_PWR_GPIO_BIT_0 (0x00000001U) +#define LL_PWR_GPIO_BIT_1 (0x00000002U) +#define LL_PWR_GPIO_BIT_2 (0x00000004U) +#define LL_PWR_GPIO_BIT_3 (0x00000008U) +#define LL_PWR_GPIO_BIT_4 (0x00000010U) +#define LL_PWR_GPIO_BIT_5 (0x00000020U) +#define LL_PWR_GPIO_BIT_6 (0x00000040U) +#define LL_PWR_GPIO_BIT_7 (0x00000080U) +#define LL_PWR_GPIO_BIT_8 (0x00000100U) +#define LL_PWR_GPIO_BIT_9 (0x00000200U) +#define LL_PWR_GPIO_BIT_10 (0x00000400U) +#define LL_PWR_GPIO_BIT_11 (0x00000800U) +#define LL_PWR_GPIO_BIT_12 (0x00001000U) +#define LL_PWR_GPIO_BIT_13 (0x00002000U) +#define LL_PWR_GPIO_BIT_14 (0x00004000U) +#define LL_PWR_GPIO_BIT_15 (0x00008000U) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup PWR_LL_Exported_Macros PWR Exported Macros + * @{ + */ + +/** @defgroup PWR_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in PWR register + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__)) + +/** + * @brief Read a value in PWR register + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__) +/** + * @} + */ + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup PWR_LL_Exported_Functions PWR Exported Functions + * @{ + */ + +/** @defgroup PWR_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Switch the regulator from main mode to low-power mode + * @rmtoll CR1 LPR LL_PWR_EnableLowPowerRunMode + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableLowPowerRunMode(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_LPR); +} + +/** + * @brief Switch the regulator from low-power mode to main mode + * @rmtoll CR1 LPR LL_PWR_DisableLowPowerRunMode + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableLowPowerRunMode(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_LPR); +} + +/** + * @brief Switch from run main mode to run low-power mode. + * @rmtoll CR1 LPR LL_PWR_EnterLowPowerRunMode + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnterLowPowerRunMode(void) +{ + LL_PWR_EnableLowPowerRunMode(); +} + +/** + * @brief Switch from run main mode to low-power mode. + * @rmtoll CR1 LPR LL_PWR_ExitLowPowerRunMode + * @retval None + */ +__STATIC_INLINE void LL_PWR_ExitLowPowerRunMode(void) +{ + LL_PWR_DisableLowPowerRunMode(); +} + +/** + * @brief Check if the regulator is in low-power mode + * @rmtoll CR1 LPR LL_PWR_IsEnabledLowPowerRunMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRunMode(void) +{ + return ((READ_BIT(PWR->CR1, PWR_CR1_LPR) == (PWR_CR1_LPR)) ? 1UL : 0UL); +} + +/** + * @brief Set the main internal regulator output voltage + * @note This configuration may be completed with LL_PWR_EnableRange1BoostMode() on STM32L4Rx/STM32L4Sx devices. + * @rmtoll CR1 VOS LL_PWR_SetRegulVoltageScaling + * @param VoltageScaling This parameter can be one of the following values: + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2 + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling) +{ + MODIFY_REG(PWR->CR1, PWR_CR1_VOS, VoltageScaling); +} + +/** + * @brief Get the main internal regulator output voltage + * @rmtoll CR1 VOS LL_PWR_GetRegulVoltageScaling + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2 + */ +__STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void) +{ + return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_VOS)); +} + +#if defined(PWR_CR5_R1MODE) +/** + * @brief Enable main regulator voltage range 1 boost mode + * @rmtoll CR5 R1MODE LL_PWR_EnableRange1BoostMode + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableRange1BoostMode(void) +{ + CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE); +} + +/** + * @brief Disable main regulator voltage range 1 boost mode + * @rmtoll CR5 R1MODE LL_PWR_DisableRange1BoostMode + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableRange1BoostMode(void) +{ + SET_BIT(PWR->CR5, PWR_CR5_R1MODE); +} + +/** + * @brief Check if the main regulator voltage range 1 boost mode is enabled + * @rmtoll CR5 R1MODE LL_PWR_IsEnabledRange1BoostMode + * @retval Inverted state of bit (0 or 1). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledRange1BoostMode(void) +{ + return ((READ_BIT(PWR->CR5, PWR_CR5_R1MODE) == 0x0U) ? 1UL : 0UL); +} +#endif /* PWR_CR5_R1MODE */ + +/** + * @brief Enable access to the backup domain + * @rmtoll CR1 DBP LL_PWR_EnableBkUpAccess + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_DBP); +} + +/** + * @brief Disable access to the backup domain + * @rmtoll CR1 DBP LL_PWR_DisableBkUpAccess + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_DBP); +} + +/** + * @brief Check if the backup domain is enabled + * @rmtoll CR1 DBP LL_PWR_IsEnabledBkUpAccess + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void) +{ + return ((READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP)) ? 1UL : 0UL); +} + +/** + * @brief Set Low-Power mode + * @rmtoll CR1 LPMS LL_PWR_SetPowerMode + * @param LowPowerMode This parameter can be one of the following values: + * @arg @ref LL_PWR_MODE_STOP0 + * @arg @ref LL_PWR_MODE_STOP1 + * @arg @ref LL_PWR_MODE_STOP2 + * @arg @ref LL_PWR_MODE_STANDBY + * @arg @ref LL_PWR_MODE_SHUTDOWN + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t LowPowerMode) +{ + MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, LowPowerMode); +} + +/** + * @brief Get Low-Power mode + * @rmtoll CR1 LPMS LL_PWR_GetPowerMode + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_MODE_STOP0 + * @arg @ref LL_PWR_MODE_STOP1 + * @arg @ref LL_PWR_MODE_STOP2 + * @arg @ref LL_PWR_MODE_STANDBY + * @arg @ref LL_PWR_MODE_SHUTDOWN + */ +__STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void) +{ + return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_LPMS)); +} + +#if defined(PWR_CR1_RRSTP) +/** + * @brief Enable SRAM3 content retention in Stop mode + * @rmtoll CR1 RRSTP LL_PWR_EnableSRAM3Retention + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableSRAM3Retention(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_RRSTP); +} + +/** + * @brief Disable SRAM3 content retention in Stop mode + * @rmtoll CR1 RRSTP LL_PWR_DisableSRAM3Retention + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableSRAM3Retention(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_RRSTP); +} + +/** + * @brief Check if SRAM3 content retention in Stop mode is enabled + * @rmtoll CR1 RRSTP LL_PWR_IsEnabledSRAM3Retention + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledSRAM3Retention(void) +{ + return ((READ_BIT(PWR->CR1, PWR_CR1_RRSTP) == (PWR_CR1_RRSTP)) ? 1UL : 0UL); +} +#endif /* PWR_CR1_RRSTP */ + +#if defined(PWR_CR3_DSIPDEN) +/** + * @brief Enable pull-down activation on DSI pins + * @rmtoll CR3 DSIPDEN LL_PWR_EnableDSIPinsPDActivation + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableDSIPinsPDActivation(void) +{ + SET_BIT(PWR->CR3, PWR_CR3_DSIPDEN); +} + +/** + * @brief Disable pull-down activation on DSI pins + * @rmtoll CR3 DSIPDEN LL_PWR_DisableDSIPinsPDActivation + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableDSIPinsPDActivation(void) +{ + CLEAR_BIT(PWR->CR3, PWR_CR3_DSIPDEN); +} + +/** + * @brief Check if pull-down activation on DSI pins is enabled + * @rmtoll CR3 DSIPDEN LL_PWR_IsEnabledDSIPinsPDActivation + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledDSIPinsPDActivation(void) +{ + return ((READ_BIT(PWR->CR3, PWR_CR3_DSIPDEN) == (PWR_CR3_DSIPDEN)) ? 1UL : 0UL); +} +#endif /* PWR_CR3_DSIPDEN */ + +#if defined(PWR_CR2_USV) +/** + * @brief Enable VDDUSB supply + * @rmtoll CR2 USV LL_PWR_EnableVddUSB + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableVddUSB(void) +{ + SET_BIT(PWR->CR2, PWR_CR2_USV); +} + +/** + * @brief Disable VDDUSB supply + * @rmtoll CR2 USV LL_PWR_DisableVddUSB + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableVddUSB(void) +{ + CLEAR_BIT(PWR->CR2, PWR_CR2_USV); +} + +/** + * @brief Check if VDDUSB supply is enabled + * @rmtoll CR2 USV LL_PWR_IsEnabledVddUSB + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledVddUSB(void) +{ + return ((READ_BIT(PWR->CR2, PWR_CR2_USV) == (PWR_CR2_USV)) ? 1UL : 0UL); +} +#endif + +#if defined(PWR_CR2_IOSV) +/** + * @brief Enable VDDIO2 supply + * @rmtoll CR2 IOSV LL_PWR_EnableVddIO2 + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableVddIO2(void) +{ + SET_BIT(PWR->CR2, PWR_CR2_IOSV); +} + +/** + * @brief Disable VDDIO2 supply + * @rmtoll CR2 IOSV LL_PWR_DisableVddIO2 + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableVddIO2(void) +{ + CLEAR_BIT(PWR->CR2, PWR_CR2_IOSV); +} + +/** + * @brief Check if VDDIO2 supply is enabled + * @rmtoll CR2 IOSV LL_PWR_IsEnabledVddIO2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledVddIO2(void) +{ + return ((READ_BIT(PWR->CR2, PWR_CR2_IOSV) == (PWR_CR2_IOSV)) ? 1UL : 0UL); +} +#endif + +/** + * @brief Enable the Power Voltage Monitoring on a peripheral + * @rmtoll CR2 PVME1 LL_PWR_EnablePVM\n + * CR2 PVME2 LL_PWR_EnablePVM\n + * CR2 PVME3 LL_PWR_EnablePVM\n + * CR2 PVME4 LL_PWR_EnablePVM + * @param PeriphVoltage This parameter can be one of the following values: + * @arg @ref LL_PWR_PVM_VDDUSB_1_2V (*) + * @arg @ref LL_PWR_PVM_VDDIO2_0_9V (*) + * @arg @ref LL_PWR_PVM_VDDA_1_62V + * @arg @ref LL_PWR_PVM_VDDA_2_2V + * + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnablePVM(uint32_t PeriphVoltage) +{ + SET_BIT(PWR->CR2, PeriphVoltage); +} + +/** + * @brief Disable the Power Voltage Monitoring on a peripheral + * @rmtoll CR2 PVME1 LL_PWR_DisablePVM\n + * CR2 PVME2 LL_PWR_DisablePVM\n + * CR2 PVME3 LL_PWR_DisablePVM\n + * CR2 PVME4 LL_PWR_DisablePVM + * @param PeriphVoltage This parameter can be one of the following values: + * @arg @ref LL_PWR_PVM_VDDUSB_1_2V (*) + * @arg @ref LL_PWR_PVM_VDDIO2_0_9V (*) + * @arg @ref LL_PWR_PVM_VDDA_1_62V + * @arg @ref LL_PWR_PVM_VDDA_2_2V + * + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisablePVM(uint32_t PeriphVoltage) +{ + CLEAR_BIT(PWR->CR2, PeriphVoltage); +} + +/** + * @brief Check if Power Voltage Monitoring is enabled on a peripheral + * @rmtoll CR2 PVME1 LL_PWR_IsEnabledPVM\n + * CR2 PVME2 LL_PWR_IsEnabledPVM\n + * CR2 PVME3 LL_PWR_IsEnabledPVM\n + * CR2 PVME4 LL_PWR_IsEnabledPVM + * @param PeriphVoltage This parameter can be one of the following values: + * @arg @ref LL_PWR_PVM_VDDUSB_1_2V (*) + * @arg @ref LL_PWR_PVM_VDDIO2_0_9V (*) + * @arg @ref LL_PWR_PVM_VDDA_1_62V + * @arg @ref LL_PWR_PVM_VDDA_2_2V + * + * (*) value not defined in all devices + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVM(uint32_t PeriphVoltage) +{ + return ((READ_BIT(PWR->CR2, PeriphVoltage) == (PeriphVoltage)) ? 1UL : 0UL); +} + +/** + * @brief Configure the voltage threshold detected by the Power Voltage Detector + * @rmtoll CR2 PLS LL_PWR_SetPVDLevel + * @param PVDLevel This parameter can be one of the following values: + * @arg @ref LL_PWR_PVDLEVEL_0 + * @arg @ref LL_PWR_PVDLEVEL_1 + * @arg @ref LL_PWR_PVDLEVEL_2 + * @arg @ref LL_PWR_PVDLEVEL_3 + * @arg @ref LL_PWR_PVDLEVEL_4 + * @arg @ref LL_PWR_PVDLEVEL_5 + * @arg @ref LL_PWR_PVDLEVEL_6 + * @arg @ref LL_PWR_PVDLEVEL_7 + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel) +{ + MODIFY_REG(PWR->CR2, PWR_CR2_PLS, PVDLevel); +} + +/** + * @brief Get the voltage threshold detection + * @rmtoll CR2 PLS LL_PWR_GetPVDLevel + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_PVDLEVEL_0 + * @arg @ref LL_PWR_PVDLEVEL_1 + * @arg @ref LL_PWR_PVDLEVEL_2 + * @arg @ref LL_PWR_PVDLEVEL_3 + * @arg @ref LL_PWR_PVDLEVEL_4 + * @arg @ref LL_PWR_PVDLEVEL_5 + * @arg @ref LL_PWR_PVDLEVEL_6 + * @arg @ref LL_PWR_PVDLEVEL_7 + */ +__STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void) +{ + return (uint32_t)(READ_BIT(PWR->CR2, PWR_CR2_PLS)); +} + +/** + * @brief Enable Power Voltage Detector + * @rmtoll CR2 PVDE LL_PWR_EnablePVD + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnablePVD(void) +{ + SET_BIT(PWR->CR2, PWR_CR2_PVDE); +} + +/** + * @brief Disable Power Voltage Detector + * @rmtoll CR2 PVDE LL_PWR_DisablePVD + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisablePVD(void) +{ + CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE); +} + +/** + * @brief Check if Power Voltage Detector is enabled + * @rmtoll CR2 PVDE LL_PWR_IsEnabledPVD + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void) +{ + return ((READ_BIT(PWR->CR2, PWR_CR2_PVDE) == (PWR_CR2_PVDE)) ? 1UL : 0UL); +} + +/** + * @brief Enable Internal Wake-up line + * @rmtoll CR3 EIWF LL_PWR_EnableInternWU + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableInternWU(void) +{ + SET_BIT(PWR->CR3, PWR_CR3_EIWF); +} + +/** + * @brief Disable Internal Wake-up line + * @rmtoll CR3 EIWF LL_PWR_DisableInternWU + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableInternWU(void) +{ + CLEAR_BIT(PWR->CR3, PWR_CR3_EIWF); +} + +/** + * @brief Check if Internal Wake-up line is enabled + * @rmtoll CR3 EIWF LL_PWR_IsEnabledInternWU + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledInternWU(void) +{ + return ((READ_BIT(PWR->CR3, PWR_CR3_EIWF) == (PWR_CR3_EIWF)) ? 1UL : 0UL); +} + +/** + * @brief Enable pull-up and pull-down configuration + * @rmtoll CR3 APC LL_PWR_EnablePUPDCfg + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnablePUPDCfg(void) +{ + SET_BIT(PWR->CR3, PWR_CR3_APC); +} + +/** + * @brief Disable pull-up and pull-down configuration + * @rmtoll CR3 APC LL_PWR_DisablePUPDCfg + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisablePUPDCfg(void) +{ + CLEAR_BIT(PWR->CR3, PWR_CR3_APC); +} + +/** + * @brief Check if pull-up and pull-down configuration is enabled + * @rmtoll CR3 APC LL_PWR_IsEnabledPUPDCfg + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledPUPDCfg(void) +{ + return ((READ_BIT(PWR->CR3, PWR_CR3_APC) == (PWR_CR3_APC)) ? 1UL : 0UL); +} + +#if defined(PWR_CR3_DSIPDEN) +/** + * @brief Enable pull-down activation on DSI pins + * @rmtoll CR3 DSIPDEN LL_PWR_EnableDSIPullDown + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableDSIPullDown(void) +{ + SET_BIT(PWR->CR3, PWR_CR3_DSIPDEN); +} + +/** + * @brief Disable pull-down activation on DSI pins + * @rmtoll CR3 DSIPDEN LL_PWR_DisableDSIPullDown + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableDSIPullDown(void) +{ + CLEAR_BIT(PWR->CR3, PWR_CR3_DSIPDEN); +} + +/** + * @brief Check if pull-down activation on DSI pins is enabled + * @rmtoll CR3 DSIPDEN LL_PWR_IsEnabledDSIPullDown + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledDSIPullDown(void) +{ + return ((READ_BIT(PWR->CR3, PWR_CR3_DSIPDEN) == (PWR_CR3_DSIPDEN)) ? 1UL : 0UL); +} +#endif /* PWR_CR3_DSIPDEN */ + +#if defined(PWR_CR3_ENULP) +/** + * @brief Enable Ultra Low Power BORL, BORH and PVD for STOP2 and Standby modes + * @rmtoll CR3 ENULP LL_PWR_EnableBORPVD_ULP + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableBORPVD_ULP(void) +{ + SET_BIT(PWR->CR3, PWR_CR3_ENULP); +} + +/** + * @brief Disable Ultra Low Power BORL, BORH and PVD for STOP2 and Standby modes + * @rmtoll CR3 ENULP LL_PWR_DisableBORPVD_ULP + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableBORPVD_ULP(void) +{ + CLEAR_BIT(PWR->CR3, PWR_CR3_ENULP); +} + +/** + * @brief Check if Ultra Low Power BORL, BORH and PVD for STOP2 and Standby modes is enabled + * @rmtoll CR3 ENULP LL_PWR_IsEnabledBORPVD_ULP + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledBORPVD_ULP(void) +{ + return ((READ_BIT(PWR->CR3, PWR_CR3_ENULP) == (PWR_CR3_ENULP)) ? 1UL : 0UL); +} +#endif /* PWR_CR3_ENULP */ + +/** + * @brief Enable SRAM2 full content retention in Standby mode + * @rmtoll CR3 RRS LL_PWR_EnableSRAM2Retention + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableSRAM2Retention(void) +{ + MODIFY_REG(PWR->CR3, PWR_CR3_RRS, LL_PWR_FULL_SRAM2_RETENTION); +} + +/** + * @brief Disable SRAM2 content retention in Standby mode + * @rmtoll CR3 RRS LL_PWR_DisableSRAM2Retention + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableSRAM2Retention(void) +{ + CLEAR_BIT(PWR->CR3, PWR_CR3_RRS); +} + +/** + * @brief Check if SRAM2 full content retention in Standby mode is enabled + * @rmtoll CR3 RRS LL_PWR_IsEnabledSRAM2Retention + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledSRAM2Retention(void) +{ + return ((READ_BIT(PWR->CR3, PWR_CR3_RRS) == (LL_PWR_FULL_SRAM2_RETENTION)) ? 1UL : 0UL); +} + +/** + * @brief Set SRAM2 content retention in Standby mode + * @rmtoll CR3 RRS LL_PWR_SetSRAM2ContentRetention + * @param SRAM2Size This parameter can be one of the following values: + * @arg @ref LL_PWR_NO_SRAM2_RETENTION + * @arg @ref LL_PWR_FULL_SRAM2_RETENTION + * @arg @ref LL_PWR_4KBYTES_SRAM2_RETENTION + * @note LL_PWR_4KBYTES_SRAM2_RETENTION parameter is not available on all devices + * @note Setting LL_PWR_NO_SRAM2_RETENTION is same as calling LL_PWR_DisableSRAM2Retention() + * @note Setting LL_PWR_FULL_SRAM2_RETENTION is same as calling LL_PWR_EnableSRAM2Retention() + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetSRAM2ContentRetention(uint32_t SRAM2Size) +{ + MODIFY_REG(PWR->CR3, PWR_CR3_RRS, SRAM2Size); +} + +/** + * @brief Get SRAM2 content retention in Standby mode + * @rmtoll CR3 RRS LL_PWR_GetSRAM2ContentRetention + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_NO_SRAM2_RETENTION + * @arg @ref LL_PWR_FULL_SRAM2_RETENTION + * @arg @ref LL_PWR_4KBYTES_SRAM2_RETENTION + * @note LL_PWR_4KBYTES_SRAM2_RETENTION parameter is not available on all devices + */ +__STATIC_INLINE uint32_t LL_PWR_GetSRAM2ContentRetention(void) +{ + return (uint32_t)(READ_BIT(PWR->CR3, PWR_CR3_RRS)); +} + +/** + * @brief Enable the WakeUp PINx functionality + * @rmtoll CR3 EWUP1 LL_PWR_EnableWakeUpPin\n + * CR3 EWUP2 LL_PWR_EnableWakeUpPin\n + * CR3 EWUP3 LL_PWR_EnableWakeUpPin\n + * CR3 EWUP4 LL_PWR_EnableWakeUpPin\n + * CR3 EWUP5 LL_PWR_EnableWakeUpPin\n + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin) +{ + SET_BIT(PWR->CR3, WakeUpPin); +} + +/** + * @brief Disable the WakeUp PINx functionality + * @rmtoll CR3 EWUP1 LL_PWR_DisableWakeUpPin\n + * CR3 EWUP2 LL_PWR_DisableWakeUpPin\n + * CR3 EWUP3 LL_PWR_DisableWakeUpPin\n + * CR3 EWUP4 LL_PWR_DisableWakeUpPin\n + * CR3 EWUP5 LL_PWR_DisableWakeUpPin\n + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin) +{ + CLEAR_BIT(PWR->CR3, WakeUpPin); +} + +/** + * @brief Check if the WakeUp PINx functionality is enabled + * @rmtoll CR3 EWUP1 LL_PWR_IsEnabledWakeUpPin\n + * CR3 EWUP2 LL_PWR_IsEnabledWakeUpPin\n + * CR3 EWUP3 LL_PWR_IsEnabledWakeUpPin\n + * CR3 EWUP4 LL_PWR_IsEnabledWakeUpPin\n + * CR3 EWUP5 LL_PWR_IsEnabledWakeUpPin\n + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin) +{ + return ((READ_BIT(PWR->CR3, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL); +} + +#if defined(PWR_CR4_EXT_SMPS_ON) +/** + * @brief Enable the CFLDO working @ 0.95V + * @note When external SMPS is used & CFLDO operating in Range 2, the regulated voltage of the + * internal CFLDO can be reduced to 0.95V. + * @rmtoll CR4 EXT_SMPS_ON LL_PWR_EnableExtSMPS_0V95 + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableExtSMPS_0V95(void) +{ + SET_BIT(PWR->CR4, PWR_CR4_EXT_SMPS_ON); +} + +/** + * @brief Disable the CFLDO working @ 0.95V + * @note When external SMPS is used & CFLDO operating in Range 2, the regulated voltage of the + * internal CFLDO can be reduced to 0.95V. + * @rmtoll CR4 EXT_SMPS_ON LL_PWR_DisableExtSMPS_0V95 + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableExtSMPS_0V95(void) +{ + CLEAR_BIT(PWR->CR4, PWR_CR4_EXT_SMPS_ON); +} + +/** + * @brief Check if CFLDO is working @ 0.95V + * @note When external SMPS is used & CFLDO operating in Range 2, the regulated voltage of the + * internal CFLDO can be reduced to 0.95V. + * @rmtoll CR4 EXT_SMPS_ON LL_PWR_IsEnabledExtSMPS_0V95 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledExtSMPS_0V95(void) +{ + return ((READ_BIT(PWR->CR4, PWR_CR4_EXT_SMPS_ON) == (PWR_CR4_EXT_SMPS_ON)) ? 1UL : 0UL); +} +#endif /* PWR_CR4_EXT_SMPS_ON */ + +/** + * @brief Set the resistor impedance + * @rmtoll CR4 VBRS LL_PWR_SetBattChargResistor + * @param Resistor This parameter can be one of the following values: + * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K + * @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetBattChargResistor(uint32_t Resistor) +{ + MODIFY_REG(PWR->CR4, PWR_CR4_VBRS, Resistor); +} + +/** + * @brief Get the resistor impedance + * @rmtoll CR4 VBRS LL_PWR_GetBattChargResistor + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K + * @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K + */ +__STATIC_INLINE uint32_t LL_PWR_GetBattChargResistor(void) +{ + return (uint32_t)(READ_BIT(PWR->CR4, PWR_CR4_VBRS)); +} + +/** + * @brief Enable battery charging + * @rmtoll CR4 VBE LL_PWR_EnableBatteryCharging + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableBatteryCharging(void) +{ + SET_BIT(PWR->CR4, PWR_CR4_VBE); +} + +/** + * @brief Disable battery charging + * @rmtoll CR4 VBE LL_PWR_DisableBatteryCharging + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableBatteryCharging(void) +{ + CLEAR_BIT(PWR->CR4, PWR_CR4_VBE); +} + +/** + * @brief Check if battery charging is enabled + * @rmtoll CR4 VBE LL_PWR_IsEnabledBatteryCharging + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledBatteryCharging(void) +{ + return ((READ_BIT(PWR->CR4, PWR_CR4_VBE) == (PWR_CR4_VBE)) ? 1UL : 0UL); +} + +/** + * @brief Set the Wake-Up pin polarity low for the event detection + * @rmtoll CR4 WP1 LL_PWR_SetWakeUpPinPolarityLow\n + * CR4 WP2 LL_PWR_SetWakeUpPinPolarityLow\n + * CR4 WP3 LL_PWR_SetWakeUpPinPolarityLow\n + * CR4 WP4 LL_PWR_SetWakeUpPinPolarityLow\n + * CR4 WP5 LL_PWR_SetWakeUpPinPolarityLow + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin) +{ + SET_BIT(PWR->CR4, WakeUpPin); +} + +/** + * @brief Set the Wake-Up pin polarity high for the event detection + * @rmtoll CR4 WP1 LL_PWR_SetWakeUpPinPolarityHigh\n + * CR4 WP2 LL_PWR_SetWakeUpPinPolarityHigh\n + * CR4 WP3 LL_PWR_SetWakeUpPinPolarityHigh\n + * CR4 WP4 LL_PWR_SetWakeUpPinPolarityHigh\n + * CR4 WP5 LL_PWR_SetWakeUpPinPolarityHigh + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin) +{ + CLEAR_BIT(PWR->CR4, WakeUpPin); +} + +/** + * @brief Get the Wake-Up pin polarity for the event detection + * @rmtoll CR4 WP1 LL_PWR_IsWakeUpPinPolarityLow\n + * CR4 WP2 LL_PWR_IsWakeUpPinPolarityLow\n + * CR4 WP3 LL_PWR_IsWakeUpPinPolarityLow\n + * CR4 WP4 LL_PWR_IsWakeUpPinPolarityLow\n + * CR4 WP5 LL_PWR_IsWakeUpPinPolarityLow + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin) +{ + return ((READ_BIT(PWR->CR4, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL); +} + +/** + * @brief Enable GPIO pull-up state in Standby and Shutdown modes + * @rmtoll PUCRA PU0-15 LL_PWR_EnableGPIOPullUp\n + * PUCRB PU0-15 LL_PWR_EnableGPIOPullUp\n + * PUCRC PU0-15 LL_PWR_EnableGPIOPullUp\n + * PUCRD PU0-15 LL_PWR_EnableGPIOPullUp\n + * PUCRE PU0-15 LL_PWR_EnableGPIOPullUp\n + * PUCRF PU0-15 LL_PWR_EnableGPIOPullUp\n + * PUCRG PU0-15 LL_PWR_EnableGPIOPullUp\n + * PUCRH PU0-15 LL_PWR_EnableGPIOPullUp\n + * PUCRI PU0-11 LL_PWR_EnableGPIOPullUp + * @param GPIO This parameter can be one of the following values: + * @arg @ref LL_PWR_GPIO_A + * @arg @ref LL_PWR_GPIO_B + * @arg @ref LL_PWR_GPIO_C + * @arg @ref LL_PWR_GPIO_D + * @arg @ref LL_PWR_GPIO_E + * @arg @ref LL_PWR_GPIO_F (*) + * @arg @ref LL_PWR_GPIO_G (*) + * @arg @ref LL_PWR_GPIO_H + * @arg @ref LL_PWR_GPIO_I (*) + * + * (*) value not defined in all devices + * @param GPIONumber This parameter can be one of the following values: + * @arg @ref LL_PWR_GPIO_BIT_0 + * @arg @ref LL_PWR_GPIO_BIT_1 + * @arg @ref LL_PWR_GPIO_BIT_2 + * @arg @ref LL_PWR_GPIO_BIT_3 + * @arg @ref LL_PWR_GPIO_BIT_4 + * @arg @ref LL_PWR_GPIO_BIT_5 + * @arg @ref LL_PWR_GPIO_BIT_6 + * @arg @ref LL_PWR_GPIO_BIT_7 + * @arg @ref LL_PWR_GPIO_BIT_8 + * @arg @ref LL_PWR_GPIO_BIT_9 + * @arg @ref LL_PWR_GPIO_BIT_10 + * @arg @ref LL_PWR_GPIO_BIT_11 + * @arg @ref LL_PWR_GPIO_BIT_12 + * @arg @ref LL_PWR_GPIO_BIT_13 + * @arg @ref LL_PWR_GPIO_BIT_14 + * @arg @ref LL_PWR_GPIO_BIT_15 + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) +{ + SET_BIT(*((__IO uint32_t *)GPIO), GPIONumber); +} + +/** + * @brief Disable GPIO pull-up state in Standby and Shutdown modes + * @rmtoll PUCRA PU0-15 LL_PWR_DisableGPIOPullUp\n + * PUCRB PU0-15 LL_PWR_DisableGPIOPullUp\n + * PUCRC PU0-15 LL_PWR_DisableGPIOPullUp\n + * PUCRD PU0-15 LL_PWR_DisableGPIOPullUp\n + * PUCRE PU0-15 LL_PWR_DisableGPIOPullUp\n + * PUCRF PU0-15 LL_PWR_DisableGPIOPullUp\n + * PUCRG PU0-15 LL_PWR_DisableGPIOPullUp\n + * PUCRH PU0-15 LL_PWR_DisableGPIOPullUp\n + * PUCRI PU0-11 LL_PWR_DisableGPIOPullUp + * @param GPIO This parameter can be one of the following values: + * @arg @ref LL_PWR_GPIO_A + * @arg @ref LL_PWR_GPIO_B + * @arg @ref LL_PWR_GPIO_C + * @arg @ref LL_PWR_GPIO_D + * @arg @ref LL_PWR_GPIO_E + * @arg @ref LL_PWR_GPIO_F (*) + * @arg @ref LL_PWR_GPIO_G (*) + * @arg @ref LL_PWR_GPIO_H + * @arg @ref LL_PWR_GPIO_I (*) + * + * (*) value not defined in all devices + * @param GPIONumber This parameter can be one of the following values: + * @arg @ref LL_PWR_GPIO_BIT_0 + * @arg @ref LL_PWR_GPIO_BIT_1 + * @arg @ref LL_PWR_GPIO_BIT_2 + * @arg @ref LL_PWR_GPIO_BIT_3 + * @arg @ref LL_PWR_GPIO_BIT_4 + * @arg @ref LL_PWR_GPIO_BIT_5 + * @arg @ref LL_PWR_GPIO_BIT_6 + * @arg @ref LL_PWR_GPIO_BIT_7 + * @arg @ref LL_PWR_GPIO_BIT_8 + * @arg @ref LL_PWR_GPIO_BIT_9 + * @arg @ref LL_PWR_GPIO_BIT_10 + * @arg @ref LL_PWR_GPIO_BIT_11 + * @arg @ref LL_PWR_GPIO_BIT_12 + * @arg @ref LL_PWR_GPIO_BIT_13 + * @arg @ref LL_PWR_GPIO_BIT_14 + * @arg @ref LL_PWR_GPIO_BIT_15 + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) +{ + CLEAR_BIT(*((__IO uint32_t *)GPIO), GPIONumber); +} + +/** + * @brief Check if GPIO pull-up state is enabled + * @rmtoll PUCRA PU0-15 LL_PWR_IsEnabledGPIOPullUp\n + * PUCRB PU0-15 LL_PWR_IsEnabledGPIOPullUp\n + * PUCRC PU0-15 LL_PWR_IsEnabledGPIOPullUp\n + * PUCRD PU0-15 LL_PWR_IsEnabledGPIOPullUp\n + * PUCRE PU0-15 LL_PWR_IsEnabledGPIOPullUp\n + * PUCRF PU0-15 LL_PWR_IsEnabledGPIOPullUp\n + * PUCRG PU0-15 LL_PWR_IsEnabledGPIOPullUp\n + * PUCRH PU0-15 LL_PWR_IsEnabledGPIOPullUp\n + * PUCRI PU0-11 LL_PWR_IsEnabledGPIOPullUp + * @param GPIO This parameter can be one of the following values: + * @arg @ref LL_PWR_GPIO_A + * @arg @ref LL_PWR_GPIO_B + * @arg @ref LL_PWR_GPIO_C + * @arg @ref LL_PWR_GPIO_D + * @arg @ref LL_PWR_GPIO_E + * @arg @ref LL_PWR_GPIO_F (*) + * @arg @ref LL_PWR_GPIO_G (*) + * @arg @ref LL_PWR_GPIO_H + * @arg @ref LL_PWR_GPIO_I (*) + * + * (*) value not defined in all devices + * @param GPIONumber This parameter can be one of the following values: + * @arg @ref LL_PWR_GPIO_BIT_0 + * @arg @ref LL_PWR_GPIO_BIT_1 + * @arg @ref LL_PWR_GPIO_BIT_2 + * @arg @ref LL_PWR_GPIO_BIT_3 + * @arg @ref LL_PWR_GPIO_BIT_4 + * @arg @ref LL_PWR_GPIO_BIT_5 + * @arg @ref LL_PWR_GPIO_BIT_6 + * @arg @ref LL_PWR_GPIO_BIT_7 + * @arg @ref LL_PWR_GPIO_BIT_8 + * @arg @ref LL_PWR_GPIO_BIT_9 + * @arg @ref LL_PWR_GPIO_BIT_10 + * @arg @ref LL_PWR_GPIO_BIT_11 + * @arg @ref LL_PWR_GPIO_BIT_12 + * @arg @ref LL_PWR_GPIO_BIT_13 + * @arg @ref LL_PWR_GPIO_BIT_14 + * @arg @ref LL_PWR_GPIO_BIT_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) +{ + return ((READ_BIT(*((__IO uint32_t *)GPIO), GPIONumber) == (GPIONumber)) ? 1UL : 0UL); +} + +/** + * @brief Enable GPIO pull-down state in Standby and Shutdown modes + * @rmtoll PDCRA PD0-15 LL_PWR_EnableGPIOPullDown\n + * PDCRB PD0-15 LL_PWR_EnableGPIOPullDown\n + * PDCRC PD0-15 LL_PWR_EnableGPIOPullDown\n + * PDCRD PD0-15 LL_PWR_EnableGPIOPullDown\n + * PDCRE PD0-15 LL_PWR_EnableGPIOPullDown\n + * PDCRF PD0-15 LL_PWR_EnableGPIOPullDown\n + * PDCRG PD0-15 LL_PWR_EnableGPIOPullDown\n + * PDCRH PD0-15 LL_PWR_EnableGPIOPullDown\n + * PDCRI PD0-11 LL_PWR_EnableGPIOPullDown + * @param GPIO This parameter can be one of the following values: + * @arg @ref LL_PWR_GPIO_A + * @arg @ref LL_PWR_GPIO_B + * @arg @ref LL_PWR_GPIO_C + * @arg @ref LL_PWR_GPIO_D + * @arg @ref LL_PWR_GPIO_E + * @arg @ref LL_PWR_GPIO_F (*) + * @arg @ref LL_PWR_GPIO_G (*) + * @arg @ref LL_PWR_GPIO_H + * @arg @ref LL_PWR_GPIO_I (*) + * + * (*) value not defined in all devices + * @param GPIONumber This parameter can be one of the following values: + * @arg @ref LL_PWR_GPIO_BIT_0 + * @arg @ref LL_PWR_GPIO_BIT_1 + * @arg @ref LL_PWR_GPIO_BIT_2 + * @arg @ref LL_PWR_GPIO_BIT_3 + * @arg @ref LL_PWR_GPIO_BIT_4 + * @arg @ref LL_PWR_GPIO_BIT_5 + * @arg @ref LL_PWR_GPIO_BIT_6 + * @arg @ref LL_PWR_GPIO_BIT_7 + * @arg @ref LL_PWR_GPIO_BIT_8 + * @arg @ref LL_PWR_GPIO_BIT_9 + * @arg @ref LL_PWR_GPIO_BIT_10 + * @arg @ref LL_PWR_GPIO_BIT_11 + * @arg @ref LL_PWR_GPIO_BIT_12 + * @arg @ref LL_PWR_GPIO_BIT_13 + * @arg @ref LL_PWR_GPIO_BIT_14 + * @arg @ref LL_PWR_GPIO_BIT_15 + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber) +{ + SET_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber); +} + +/** + * @brief Disable GPIO pull-down state in Standby and Shutdown modes + * @rmtoll PDCRA PD0-15 LL_PWR_DisableGPIOPullDown\n + * PDCRB PD0-15 LL_PWR_DisableGPIOPullDown\n + * PDCRC PD0-15 LL_PWR_DisableGPIOPullDown\n + * PDCRD PD0-15 LL_PWR_DisableGPIOPullDown\n + * PDCRE PD0-15 LL_PWR_DisableGPIOPullDown\n + * PDCRF PD0-15 LL_PWR_DisableGPIOPullDown\n + * PDCRG PD0-15 LL_PWR_DisableGPIOPullDown\n + * PDCRH PD0-15 LL_PWR_DisableGPIOPullDown\n + * PDCRI PD0-11 LL_PWR_DisableGPIOPullDown + * @param GPIO This parameter can be one of the following values: + * @arg @ref LL_PWR_GPIO_A + * @arg @ref LL_PWR_GPIO_B + * @arg @ref LL_PWR_GPIO_C + * @arg @ref LL_PWR_GPIO_D + * @arg @ref LL_PWR_GPIO_E + * @arg @ref LL_PWR_GPIO_F (*) + * @arg @ref LL_PWR_GPIO_G (*) + * @arg @ref LL_PWR_GPIO_H + * @arg @ref LL_PWR_GPIO_I (*) + * + * (*) value not defined in all devices + * @param GPIONumber This parameter can be one of the following values: + * @arg @ref LL_PWR_GPIO_BIT_0 + * @arg @ref LL_PWR_GPIO_BIT_1 + * @arg @ref LL_PWR_GPIO_BIT_2 + * @arg @ref LL_PWR_GPIO_BIT_3 + * @arg @ref LL_PWR_GPIO_BIT_4 + * @arg @ref LL_PWR_GPIO_BIT_5 + * @arg @ref LL_PWR_GPIO_BIT_6 + * @arg @ref LL_PWR_GPIO_BIT_7 + * @arg @ref LL_PWR_GPIO_BIT_8 + * @arg @ref LL_PWR_GPIO_BIT_9 + * @arg @ref LL_PWR_GPIO_BIT_10 + * @arg @ref LL_PWR_GPIO_BIT_11 + * @arg @ref LL_PWR_GPIO_BIT_12 + * @arg @ref LL_PWR_GPIO_BIT_13 + * @arg @ref LL_PWR_GPIO_BIT_14 + * @arg @ref LL_PWR_GPIO_BIT_15 + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber) +{ + CLEAR_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber); +} + +/** + * @brief Check if GPIO pull-down state is enabled + * @rmtoll PDCRA PD0-15 LL_PWR_IsEnabledGPIOPullDown\n + * PDCRB PD0-15 LL_PWR_IsEnabledGPIOPullDown\n + * PDCRC PD0-15 LL_PWR_IsEnabledGPIOPullDown\n + * PDCRD PD0-15 LL_PWR_IsEnabledGPIOPullDown\n + * PDCRE PD0-15 LL_PWR_IsEnabledGPIOPullDown\n + * PDCRF PD0-15 LL_PWR_IsEnabledGPIOPullDown\n + * PDCRG PD0-15 LL_PWR_IsEnabledGPIOPullDown\n + * PDCRH PD0-15 LL_PWR_IsEnabledGPIOPullDown\n + * PDCRI PD0-11 LL_PWR_IsEnabledGPIOPullDown + * @param GPIO This parameter can be one of the following values: + * @arg @ref LL_PWR_GPIO_A + * @arg @ref LL_PWR_GPIO_B + * @arg @ref LL_PWR_GPIO_C + * @arg @ref LL_PWR_GPIO_D + * @arg @ref LL_PWR_GPIO_E + * @arg @ref LL_PWR_GPIO_F (*) + * @arg @ref LL_PWR_GPIO_G (*) + * @arg @ref LL_PWR_GPIO_H + * @arg @ref LL_PWR_GPIO_I (*) + * + * (*) value not defined in all devices + * @param GPIONumber This parameter can be one of the following values: + * @arg @ref LL_PWR_GPIO_BIT_0 + * @arg @ref LL_PWR_GPIO_BIT_1 + * @arg @ref LL_PWR_GPIO_BIT_2 + * @arg @ref LL_PWR_GPIO_BIT_3 + * @arg @ref LL_PWR_GPIO_BIT_4 + * @arg @ref LL_PWR_GPIO_BIT_5 + * @arg @ref LL_PWR_GPIO_BIT_6 + * @arg @ref LL_PWR_GPIO_BIT_7 + * @arg @ref LL_PWR_GPIO_BIT_8 + * @arg @ref LL_PWR_GPIO_BIT_9 + * @arg @ref LL_PWR_GPIO_BIT_10 + * @arg @ref LL_PWR_GPIO_BIT_11 + * @arg @ref LL_PWR_GPIO_BIT_12 + * @arg @ref LL_PWR_GPIO_BIT_13 + * @arg @ref LL_PWR_GPIO_BIT_14 + * @arg @ref LL_PWR_GPIO_BIT_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber) +{ + return ((READ_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber) == (GPIONumber)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Get Internal Wake-up line Flag + * @rmtoll SR1 WUFI LL_PWR_IsActiveFlag_InternWU + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_InternWU(void) +{ + return ((READ_BIT(PWR->SR1, PWR_SR1_WUFI) == (PWR_SR1_WUFI)) ? 1UL : 0UL); +} + +#if defined(PWR_SR1_EXT_SMPS_RDY) +/** + * @brief Get Ready Flag for switching to external SMPS + * @rmtoll SR1 EXT_SMPS_RDY LL_PWR_IsActiveFlag_ExtSMPSReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_ExtSMPSReady(void) +{ + return ((READ_BIT(PWR->SR1, PWR_SR1_EXT_SMPS_RDY) == (PWR_SR1_EXT_SMPS_RDY)) ? 1UL : 0UL); +} +#endif /* PWR_SR1_EXT_SMPS_RDY */ + +/** + * @brief Get Stand-By Flag + * @rmtoll SR1 SBF LL_PWR_IsActiveFlag_SB + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void) +{ + return ((READ_BIT(PWR->SR1, PWR_SR1_SBF) == (PWR_SR1_SBF)) ? 1UL : 0UL); +} + +/** + * @brief Get Wake-up Flag 5 + * @rmtoll SR1 WUF5 LL_PWR_IsActiveFlag_WU5 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void) +{ + return ((READ_BIT(PWR->SR1, PWR_SR1_WUF5) == (PWR_SR1_WUF5)) ? 1UL : 0UL); +} + +/** + * @brief Get Wake-up Flag 4 + * @rmtoll SR1 WUF4 LL_PWR_IsActiveFlag_WU4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void) +{ + return ((READ_BIT(PWR->SR1, PWR_SR1_WUF4) == (PWR_SR1_WUF4)) ? 1UL : 0UL); +} + +/** + * @brief Get Wake-up Flag 3 + * @rmtoll SR1 WUF3 LL_PWR_IsActiveFlag_WU3 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void) +{ + return ((READ_BIT(PWR->SR1, PWR_SR1_WUF3) == (PWR_SR1_WUF3)) ? 1UL : 0UL); +} + +/** + * @brief Get Wake-up Flag 2 + * @rmtoll SR1 WUF2 LL_PWR_IsActiveFlag_WU2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void) +{ + return ((READ_BIT(PWR->SR1, PWR_SR1_WUF2) == (PWR_SR1_WUF2)) ? 1UL : 0UL); +} + +/** + * @brief Get Wake-up Flag 1 + * @rmtoll SR1 WUF1 LL_PWR_IsActiveFlag_WU1 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void) +{ + return ((READ_BIT(PWR->SR1, PWR_SR1_WUF1) == (PWR_SR1_WUF1)) ? 1UL : 0UL); +} + +/** + * @brief Clear Stand-By Flag + * @rmtoll SCR CSBF LL_PWR_ClearFlag_SB + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_SB(void) +{ + WRITE_REG(PWR->SCR, PWR_SCR_CSBF); +} + +/** + * @brief Clear Wake-up Flags + * @rmtoll SCR CWUF LL_PWR_ClearFlag_WU + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU(void) +{ + WRITE_REG(PWR->SCR, PWR_SCR_CWUF); +} + +/** + * @brief Clear Wake-up Flag 5 + * @rmtoll SCR CWUF5 LL_PWR_ClearFlag_WU5 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU5(void) +{ + WRITE_REG(PWR->SCR, PWR_SCR_CWUF5); +} + +/** + * @brief Clear Wake-up Flag 4 + * @rmtoll SCR CWUF4 LL_PWR_ClearFlag_WU4 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU4(void) +{ + WRITE_REG(PWR->SCR, PWR_SCR_CWUF4); +} + +/** + * @brief Clear Wake-up Flag 3 + * @rmtoll SCR CWUF3 LL_PWR_ClearFlag_WU3 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU3(void) +{ + WRITE_REG(PWR->SCR, PWR_SCR_CWUF3); +} + +/** + * @brief Clear Wake-up Flag 2 + * @rmtoll SCR CWUF2 LL_PWR_ClearFlag_WU2 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU2(void) +{ + WRITE_REG(PWR->SCR, PWR_SCR_CWUF2); +} + +/** + * @brief Clear Wake-up Flag 1 + * @rmtoll SCR CWUF1 LL_PWR_ClearFlag_WU1 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU1(void) +{ + WRITE_REG(PWR->SCR, PWR_SCR_CWUF1); +} + +/** + * @brief Indicate whether VDDA voltage is below or above PVM4 threshold + * @rmtoll SR2 PVMO4 LL_PWR_IsActiveFlag_PVMO4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO4(void) +{ + return ((READ_BIT(PWR->SR2, PWR_SR2_PVMO4) == (PWR_SR2_PVMO4)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether VDDA voltage is below or above PVM3 threshold + * @rmtoll SR2 PVMO3 LL_PWR_IsActiveFlag_PVMO3 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO3(void) +{ + return ((READ_BIT(PWR->SR2, PWR_SR2_PVMO3) == (PWR_SR2_PVMO3)) ? 1UL : 0UL); +} + +#if defined(PWR_SR2_PVMO2) +/** + * @brief Indicate whether VDDIO2 voltage is below or above PVM2 threshold + * @rmtoll SR2 PVMO2 LL_PWR_IsActiveFlag_PVMO2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO2(void) +{ + return ((READ_BIT(PWR->SR2, PWR_SR2_PVMO2) == (PWR_SR2_PVMO2)) ? 1UL : 0UL); +} +#endif /* PWR_SR2_PVMO2 */ + +#if defined(PWR_SR2_PVMO1) +/** + * @brief Indicate whether VDDUSB voltage is below or above PVM1 threshold + * @rmtoll SR2 PVMO1 LL_PWR_IsActiveFlag_PVMO1 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO1(void) +{ + return ((READ_BIT(PWR->SR2, PWR_SR2_PVMO1) == (PWR_SR2_PVMO1)) ? 1UL : 0UL); +} +#endif /* PWR_SR2_PVMO1 */ + +/** + * @brief Indicate whether VDD voltage is below or above the selected PVD threshold + * @rmtoll SR2 PVDO LL_PWR_IsActiveFlag_PVDO + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void) +{ + return ((READ_BIT(PWR->SR2, PWR_SR2_PVDO) == (PWR_SR2_PVDO)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether the regulator is ready in the selected voltage range or if its output voltage is still changing to the required voltage level + * @rmtoll SR2 VOSF LL_PWR_IsActiveFlag_VOS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void) +{ + return ((READ_BIT(PWR->SR2, PWR_SR2_VOSF) == (PWR_SR2_VOSF)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether the regulator is ready in main mode or is in low-power mode + * @note Take care, return value "0" means the regulator is ready. Return value "1" means the output voltage range is still changing. + * @rmtoll SR2 REGLPF LL_PWR_IsActiveFlag_REGLPF + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPF(void) +{ + return ((READ_BIT(PWR->SR2, PWR_SR2_REGLPF) == (PWR_SR2_REGLPF)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether or not the low-power regulator is ready + * @rmtoll SR2 REGLPS LL_PWR_IsActiveFlag_REGLPS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPS(void) +{ + return ((READ_BIT(PWR->SR2, PWR_SR2_REGLPS) == (PWR_SR2_REGLPS)) ? 1UL : 0UL); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup PWR_LL_EF_Init De-initialization function + * @{ + */ +ErrorStatus LL_PWR_DeInit(void); +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** @defgroup PWR_LL_EF_Legacy_Functions Legacy functions name + * @{ + */ +/* Old functions name kept for legacy purpose, to be replaced by the */ +/* current functions name. */ +#define LL_PWR_IsActiveFlag_VOSF LL_PWR_IsActiveFlag_VOS +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(PWR) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32L4xx_LL_PWR_H */ diff --git a/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_rcc.h b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_rcc.h new file mode 100644 index 0000000..cc05c56 --- /dev/null +++ b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_rcc.h @@ -0,0 +1,6233 @@ +/** + ****************************************************************************** + * @file stm32l4xx_ll_rcc.h + * @author MCD Application Team + * @brief Header file of RCC LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32L4xx_LL_RCC_H +#define STM32L4xx_LL_RCC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx.h" + +/** @addtogroup STM32L4xx_LL_Driver + * @{ + */ + +#if defined(RCC) + +/** @defgroup RCC_LL RCC + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup RCC_LL_Private_Constants RCC Private Constants + * @{ + */ +/* Defines used to perform offsets*/ +/* Offset used to access to RCC_CCIPR and RCC_CCIPR2 registers */ +#define RCC_OFFSET_CCIPR 0U +#define RCC_OFFSET_CCIPR2 0x14U + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_Private_Macros RCC Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_Exported_Types RCC Exported Types + * @{ + */ + +/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure + * @{ + */ + +/** + * @brief RCC Clocks Frequency Structure + */ +typedef struct +{ + uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */ + uint32_t HCLK_Frequency; /*!< HCLK clock frequency */ + uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */ + uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */ +} LL_RCC_ClocksTypeDef; + +/** + * @} + */ + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants + * @{ + */ + +/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation + * @brief Defines used to adapt values of different oscillators + * @note These values could be modified in the user environment according to + * HW set-up. + * @{ + */ +#if !defined (HSE_VALUE) +#define HSE_VALUE 8000000U /*!< Value of the HSE oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) +#define HSI_VALUE 16000000U /*!< Value of the HSI oscillator in Hz */ +#endif /* HSI_VALUE */ + +#if !defined (LSE_VALUE) +#define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */ +#endif /* LSE_VALUE */ + +#if !defined (LSI_VALUE) +#define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */ +#endif /* LSI_VALUE */ +#if defined(RCC_HSI48_SUPPORT) + +#if !defined (HSI48_VALUE) +#define HSI48_VALUE 48000000U /*!< Value of the HSI48 oscillator in Hz */ +#endif /* HSI48_VALUE */ +#endif /* RCC_HSI48_SUPPORT */ + +#if !defined (EXTERNAL_SAI1_CLOCK_VALUE) +#define EXTERNAL_SAI1_CLOCK_VALUE 48000U /*!< Value of the SAI1_EXTCLK external oscillator in Hz */ +#endif /* EXTERNAL_SAI1_CLOCK_VALUE */ + +#if !defined (EXTERNAL_SAI2_CLOCK_VALUE) +#define EXTERNAL_SAI2_CLOCK_VALUE 48000U /*!< Value of the SAI2_EXTCLK external oscillator in Hz */ +#endif /* EXTERNAL_SAI2_CLOCK_VALUE */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_RCC_WriteReg function + * @{ + */ +#define LL_RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC /*!< LSI Ready Interrupt Clear */ +#define LL_RCC_CICR_LSERDYC RCC_CICR_LSERDYC /*!< LSE Ready Interrupt Clear */ +#define LL_RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC /*!< MSI Ready Interrupt Clear */ +#define LL_RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC /*!< HSI Ready Interrupt Clear */ +#define LL_RCC_CICR_HSERDYC RCC_CICR_HSERDYC /*!< HSE Ready Interrupt Clear */ +#define LL_RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC /*!< PLL Ready Interrupt Clear */ +#if defined(RCC_HSI48_SUPPORT) +#define LL_RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC /*!< HSI48 Ready Interrupt Clear */ +#endif /* RCC_HSI48_SUPPORT */ +#if defined(RCC_PLLSAI1_SUPPORT) +#define LL_RCC_CICR_PLLSAI1RDYC RCC_CICR_PLLSAI1RDYC /*!< PLLSAI1 Ready Interrupt Clear */ +#endif /* RCC_PLLSAI1_SUPPORT */ +#if defined(RCC_PLLSAI2_SUPPORT) +#define LL_RCC_CICR_PLLSAI2RDYC RCC_CICR_PLLSAI2RDYC /*!< PLLSAI2 Ready Interrupt Clear */ +#endif /* RCC_PLLSAI2_SUPPORT */ +#define LL_RCC_CICR_LSECSSC RCC_CICR_LSECSSC /*!< LSE Clock Security System Interrupt Clear */ +#define LL_RCC_CICR_CSSC RCC_CICR_CSSC /*!< Clock Security System Interrupt Clear */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_RCC_ReadReg function + * @{ + */ +#define LL_RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */ +#define LL_RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */ +#define LL_RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF /*!< MSI Ready Interrupt flag */ +#define LL_RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF /*!< HSI Ready Interrupt flag */ +#define LL_RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */ +#define LL_RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF /*!< PLL Ready Interrupt flag */ +#if defined(RCC_HSI48_SUPPORT) +#define LL_RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */ +#endif /* RCC_HSI48_SUPPORT */ +#if defined(RCC_PLLSAI1_SUPPORT) +#define LL_RCC_CIFR_PLLSAI1RDYF RCC_CIFR_PLLSAI1RDYF /*!< PLLSAI1 Ready Interrupt flag */ +#endif /* RCC_PLLSAI1_SUPPORT */ +#if defined(RCC_PLLSAI2_SUPPORT) +#define LL_RCC_CIFR_PLLSAI2RDYF RCC_CIFR_PLLSAI2RDYF /*!< PLLSAI2 Ready Interrupt flag */ +#endif /* RCC_PLLSAI2_SUPPORT */ +#define LL_RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF /*!< LSE Clock Security System Interrupt flag */ +#define LL_RCC_CIFR_CSSF RCC_CIFR_CSSF /*!< Clock Security System Interrupt flag */ +#define LL_RCC_CSR_FWRSTF RCC_CSR_FWRSTF /*!< Firewall reset flag */ +#define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */ +#define LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF /*!< OBL reset flag */ +#define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */ +#define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */ +#define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */ +#define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */ +#define LL_RCC_CSR_BORRSTF RCC_CSR_BORRSTF /*!< BOR reset flag */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions + * @{ + */ +#define LL_RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE /*!< LSI Ready Interrupt Enable */ +#define LL_RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE /*!< LSE Ready Interrupt Enable */ +#define LL_RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE /*!< MSI Ready Interrupt Enable */ +#define LL_RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE /*!< HSI Ready Interrupt Enable */ +#define LL_RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE /*!< HSE Ready Interrupt Enable */ +#define LL_RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE /*!< PLL Ready Interrupt Enable */ +#if defined(RCC_HSI48_SUPPORT) +#define LL_RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE /*!< HSI48 Ready Interrupt Enable */ +#endif /* RCC_HSI48_SUPPORT */ +#if defined(RCC_PLLSAI1_SUPPORT) +#define LL_RCC_CIER_PLLSAI1RDYIE RCC_CIER_PLLSAI1RDYIE /*!< PLLSAI1 Ready Interrupt Enable */ +#endif /* RCC_PLLSAI1_SUPPORT */ +#if defined(RCC_PLLSAI2_SUPPORT) +#define LL_RCC_CIER_PLLSAI2RDYIE RCC_CIER_PLLSAI2RDYIE /*!< PLLSAI2 Ready Interrupt Enable */ +#endif /* RCC_PLLSAI2_SUPPORT */ +#define LL_RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE /*!< LSE CSS Interrupt Enable */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability + * @{ + */ +#define LL_RCC_LSEDRIVE_LOW 0x00000000U /*!< Xtal mode lower driving capability */ +#define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium low driving capability */ +#define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium high driving capability */ +#define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capability */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_MSIRANGE MSI clock ranges + * @{ + */ +#define LL_RCC_MSIRANGE_0 RCC_CR_MSIRANGE_0 /*!< MSI = 100 KHz */ +#define LL_RCC_MSIRANGE_1 RCC_CR_MSIRANGE_1 /*!< MSI = 200 KHz */ +#define LL_RCC_MSIRANGE_2 RCC_CR_MSIRANGE_2 /*!< MSI = 400 KHz */ +#define LL_RCC_MSIRANGE_3 RCC_CR_MSIRANGE_3 /*!< MSI = 800 KHz */ +#define LL_RCC_MSIRANGE_4 RCC_CR_MSIRANGE_4 /*!< MSI = 1 MHz */ +#define LL_RCC_MSIRANGE_5 RCC_CR_MSIRANGE_5 /*!< MSI = 2 MHz */ +#define LL_RCC_MSIRANGE_6 RCC_CR_MSIRANGE_6 /*!< MSI = 4 MHz */ +#define LL_RCC_MSIRANGE_7 RCC_CR_MSIRANGE_7 /*!< MSI = 8 MHz */ +#define LL_RCC_MSIRANGE_8 RCC_CR_MSIRANGE_8 /*!< MSI = 16 MHz */ +#define LL_RCC_MSIRANGE_9 RCC_CR_MSIRANGE_9 /*!< MSI = 24 MHz */ +#define LL_RCC_MSIRANGE_10 RCC_CR_MSIRANGE_10 /*!< MSI = 32 MHz */ +#define LL_RCC_MSIRANGE_11 RCC_CR_MSIRANGE_11 /*!< MSI = 48 MHz */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_MSISRANGE MSI range after Standby mode + * @{ + */ +#define LL_RCC_MSISRANGE_4 RCC_CSR_MSISRANGE_1 /*!< MSI = 1 MHz */ +#define LL_RCC_MSISRANGE_5 RCC_CSR_MSISRANGE_2 /*!< MSI = 2 MHz */ +#define LL_RCC_MSISRANGE_6 RCC_CSR_MSISRANGE_4 /*!< MSI = 4 MHz */ +#define LL_RCC_MSISRANGE_7 RCC_CSR_MSISRANGE_8 /*!< MSI = 8 MHz */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_LSCO_CLKSOURCE LSCO Selection + * @{ + */ +#define LL_RCC_LSCO_CLKSOURCE_LSI 0x00000000U /*!< LSI selection for low speed clock */ +#define LL_RCC_LSCO_CLKSOURCE_LSE RCC_BDCR_LSCOSEL /*!< LSE selection for low speed clock */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch + * @{ + */ +#define LL_RCC_SYS_CLKSOURCE_MSI RCC_CFGR_SW_MSI /*!< MSI selection as system clock */ +#define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */ +#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */ +#define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /*!< PLL selection as system clock */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status + * @{ + */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_MSI RCC_CFGR_SWS_MSI /*!< MSI used as system clock */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler + * @{ + */ +#define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */ +#define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ +#define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */ +#define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */ +#define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */ +#define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */ +#define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */ +#define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */ +#define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1) + * @{ + */ +#define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */ +#define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */ +#define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */ +#define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */ +#define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2) + * @{ + */ +#define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /*!< HCLK not divided */ +#define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /*!< HCLK divided by 2 */ +#define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /*!< HCLK divided by 4 */ +#define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /*!< HCLK divided by 8 */ +#define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_STOP_WAKEUPCLOCK Wakeup from Stop and CSS backup clock selection + * @{ + */ +#define LL_RCC_STOP_WAKEUPCLOCK_MSI 0x00000000U /*!< MSI selection after wake-up from STOP */ +#define LL_RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK /*!< HSI selection after wake-up from STOP */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection + * @{ + */ +#define LL_RCC_MCO1SOURCE_NOCLOCK 0x00000000U /*!< MCO output disabled, no clock on MCO */ +#define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */ +#define LL_RCC_MCO1SOURCE_MSI RCC_CFGR_MCOSEL_1 /*!< MSI selection as MCO1 source */ +#define LL_RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI16 selection as MCO1 source */ +#define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2 /*!< HSE selection as MCO1 source */ +#define LL_RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2) /*!< Main PLL selection as MCO1 source */ +#define LL_RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSI selection as MCO1 source */ +#define LL_RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSE selection as MCO1 source */ +#if defined(RCC_HSI48_SUPPORT) +#define LL_RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_3 /*!< HSI48 selection as MCO1 source */ +#endif /* RCC_HSI48_SUPPORT */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler + * @{ + */ +#define LL_RCC_MCO1_DIV_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO not divided */ +#define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO divided by 2 */ +#define LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO divided by 4 */ +#define LL_RCC_MCO1_DIV_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO divided by 8 */ +#define LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO divided by 16 */ +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency + * @{ + */ +#define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */ +#define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** @defgroup RCC_LL_EC_USART1_CLKSOURCE Peripheral USART clock source selection + * @{ + */ +#define LL_RCC_USART1_CLKSOURCE_PCLK2 (RCC_CCIPR_USART1SEL << 16U) /*!< PCLK2 clock used as USART1 clock source */ +#define LL_RCC_USART1_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL_0) /*!< SYSCLK clock used as USART1 clock source */ +#define LL_RCC_USART1_CLKSOURCE_HSI ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL_1) /*!< HSI clock used as USART1 clock source */ +#define LL_RCC_USART1_CLKSOURCE_LSE ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL) /*!< LSE clock used as USART1 clock source */ +#define LL_RCC_USART2_CLKSOURCE_PCLK1 (RCC_CCIPR_USART2SEL << 16U) /*!< PCLK1 clock used as USART2 clock source */ +#define LL_RCC_USART2_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL_0) /*!< SYSCLK clock used as USART2 clock source */ +#define LL_RCC_USART2_CLKSOURCE_HSI ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL_1) /*!< HSI clock used as USART2 clock source */ +#define LL_RCC_USART2_CLKSOURCE_LSE ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL) /*!< LSE clock used as USART2 clock source */ +#if defined(RCC_CCIPR_USART3SEL) +#define LL_RCC_USART3_CLKSOURCE_PCLK1 (RCC_CCIPR_USART3SEL << 16U) /*!< PCLK1 clock used as USART3 clock source */ +#define LL_RCC_USART3_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL_0) /*!< SYSCLK clock used as USART3 clock source */ +#define LL_RCC_USART3_CLKSOURCE_HSI ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL_1) /*!< HSI clock used as USART3 clock source */ +#define LL_RCC_USART3_CLKSOURCE_LSE ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL) /*!< LSE clock used as USART3 clock source */ +#endif /* RCC_CCIPR_USART3SEL */ +/** + * @} + */ + +#if defined(RCC_CCIPR_UART4SEL) || defined(RCC_CCIPR_UART5SEL) +/** @defgroup RCC_LL_EC_UART4_CLKSOURCE Peripheral UART clock source selection + * @{ + */ +#if defined(RCC_CCIPR_UART4SEL) +#define LL_RCC_UART4_CLKSOURCE_PCLK1 (RCC_CCIPR_UART4SEL << 16U) /*!< PCLK1 clock used as UART4 clock source */ +#define LL_RCC_UART4_CLKSOURCE_SYSCLK ((RCC_CCIPR_UART4SEL << 16U) | RCC_CCIPR_UART4SEL_0) /*!< SYSCLK clock used as UART4 clock source */ +#define LL_RCC_UART4_CLKSOURCE_HSI ((RCC_CCIPR_UART4SEL << 16U) | RCC_CCIPR_UART4SEL_1) /*!< HSI clock used as UART4 clock source */ +#define LL_RCC_UART4_CLKSOURCE_LSE ((RCC_CCIPR_UART4SEL << 16U) | RCC_CCIPR_UART4SEL) /*!< LSE clock used as UART4 clock source */ +#endif /* RCC_CCIPR_UART4SEL */ +#if defined(RCC_CCIPR_UART5SEL) +#define LL_RCC_UART5_CLKSOURCE_PCLK1 (RCC_CCIPR_UART5SEL << 16U) /*!< PCLK1 clock used as UART5 clock source */ +#define LL_RCC_UART5_CLKSOURCE_SYSCLK ((RCC_CCIPR_UART5SEL << 16U) | RCC_CCIPR_UART5SEL_0) /*!< SYSCLK clock used as UART5 clock source */ +#define LL_RCC_UART5_CLKSOURCE_HSI ((RCC_CCIPR_UART5SEL << 16U) | RCC_CCIPR_UART5SEL_1) /*!< HSI clock used as UART5 clock source */ +#define LL_RCC_UART5_CLKSOURCE_LSE ((RCC_CCIPR_UART5SEL << 16U) | RCC_CCIPR_UART5SEL) /*!< LSE clock used as UART5 clock source */ +#endif /* RCC_CCIPR_UART5SEL */ +/** + * @} + */ +#endif /* RCC_CCIPR_UART4SEL || RCC_CCIPR_UART5SEL */ + +/** @defgroup RCC_LL_EC_LPUART1_CLKSOURCE Peripheral LPUART clock source selection + * @{ + */ +#define LL_RCC_LPUART1_CLKSOURCE_PCLK1 0x00000000U /*!< PCLK1 clock used as LPUART1 clock source */ +#define LL_RCC_LPUART1_CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0 /*!< SYSCLK clock used as LPUART1 clock source */ +#define LL_RCC_LPUART1_CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1 /*!< HSI clock used as LPUART1 clock source */ +#define LL_RCC_LPUART1_CLKSOURCE_LSE RCC_CCIPR_LPUART1SEL /*!< LSE clock used as LPUART1 clock source */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_I2C1_CLKSOURCE Peripheral I2C clock source selection + * @{ + */ +#define LL_RCC_I2C1_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C1SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C1 clock source */ +#define LL_RCC_I2C1_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C1SEL_Pos << 16U) | (RCC_CCIPR_I2C1SEL_0 >> RCC_CCIPR_I2C1SEL_Pos)) /*!< SYSCLK clock used as I2C1 clock source */ +#define LL_RCC_I2C1_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C1SEL_Pos << 16U) | (RCC_CCIPR_I2C1SEL_1 >> RCC_CCIPR_I2C1SEL_Pos)) /*!< HSI clock used as I2C1 clock source */ +#if defined(RCC_CCIPR_I2C2SEL) +#define LL_RCC_I2C2_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C2SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C2 clock source */ +#define LL_RCC_I2C2_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C2SEL_Pos << 16U) | (RCC_CCIPR_I2C2SEL_0 >> RCC_CCIPR_I2C2SEL_Pos)) /*!< SYSCLK clock used as I2C2 clock source */ +#define LL_RCC_I2C2_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C2SEL_Pos << 16U) | (RCC_CCIPR_I2C2SEL_1 >> RCC_CCIPR_I2C2SEL_Pos)) /*!< HSI clock used as I2C2 clock source */ +#endif /* RCC_CCIPR_I2C2SEL */ +#define LL_RCC_I2C3_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C3SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C3 clock source */ +#define LL_RCC_I2C3_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C3SEL_Pos << 16U) | (RCC_CCIPR_I2C3SEL_0 >> RCC_CCIPR_I2C3SEL_Pos)) /*!< SYSCLK clock used as I2C3 clock source */ +#define LL_RCC_I2C3_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C3SEL_Pos << 16U) | (RCC_CCIPR_I2C3SEL_1 >> RCC_CCIPR_I2C3SEL_Pos)) /*!< HSI clock used as I2C3 clock source */ +#if defined(RCC_CCIPR2_I2C4SEL) +#define LL_RCC_I2C4_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C4SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C4 clock source */ +#define LL_RCC_I2C4_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C4SEL_Pos << 16U) | (RCC_CCIPR2_I2C4SEL_0 >> RCC_CCIPR2_I2C4SEL_Pos)) /*!< SYSCLK clock used as I2C4 clock source */ +#define LL_RCC_I2C4_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C4SEL_Pos << 16U) | (RCC_CCIPR2_I2C4SEL_1 >> RCC_CCIPR2_I2C4SEL_Pos)) /*!< HSI clock used as I2C4 clock source */ +#endif /* RCC_CCIPR2_I2C4SEL */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_LPTIM1_CLKSOURCE Peripheral LPTIM clock source selection + * @{ + */ +#define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 RCC_CCIPR_LPTIM1SEL /*!< PCLK1 clock used as LPTIM1 clock source */ +#define LL_RCC_LPTIM1_CLKSOURCE_LSI (RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL_0 >> 16U)) /*!< LSI clock used as LPTIM1 clock source */ +#define LL_RCC_LPTIM1_CLKSOURCE_HSI (RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL_1 >> 16U)) /*!< HSI clock used as LPTIM1 clock source */ +#define LL_RCC_LPTIM1_CLKSOURCE_LSE (RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL >> 16U)) /*!< LSE clock used as LPTIM1 clock source */ +#define LL_RCC_LPTIM2_CLKSOURCE_PCLK1 RCC_CCIPR_LPTIM2SEL /*!< PCLK1 clock used as LPTIM2 clock source */ +#define LL_RCC_LPTIM2_CLKSOURCE_LSI (RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL_0 >> 16U)) /*!< LSI clock used as LPTIM2 clock source */ +#define LL_RCC_LPTIM2_CLKSOURCE_HSI (RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL_1 >> 16U)) /*!< HSI clock used as LPTIM2 clock source */ +#define LL_RCC_LPTIM2_CLKSOURCE_LSE (RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL >> 16U)) /*!< LSE clock used as LPTIM2 clock source */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SAI1_CLKSOURCE Peripheral SAI clock source selection + * @{ + */ +#if defined(RCC_CCIPR2_SAI1SEL) +#define LL_RCC_SAI1_CLKSOURCE_PLLSAI1 (RCC_CCIPR2_SAI1SEL << 16U) /*!< PLLSAI1 (PLLSAI1CLK) clock used as SAI1 clock source */ +#define LL_RCC_SAI1_CLKSOURCE_PLLSAI2 ((RCC_CCIPR2_SAI1SEL << 16U) | RCC_CCIPR2_SAI1SEL_0) /*!< PLLSAI2 (PLLSAI2CLK) clock used as SAI1 clock source */ +#define LL_RCC_SAI1_CLKSOURCE_PLL ((RCC_CCIPR2_SAI1SEL << 16U) | RCC_CCIPR2_SAI1SEL_1) /*!< PLL (PLLSAI3CLK) clock used as SAI1 clock source */ +#define LL_RCC_SAI1_CLKSOURCE_PIN ((RCC_CCIPR2_SAI1SEL << 16U) | (RCC_CCIPR2_SAI1SEL_1 | RCC_CCIPR2_SAI1SEL_0)) /*!< External input clock used as SAI1 clock source */ +#define LL_RCC_SAI1_CLKSOURCE_HSI ((RCC_CCIPR2_SAI1SEL << 16U) | RCC_CCIPR2_SAI1SEL_2) /*!< HSI clock used as SAI1 clock source */ +#elif defined(RCC_CCIPR_SAI1SEL) +#define LL_RCC_SAI1_CLKSOURCE_PLLSAI1 RCC_CCIPR_SAI1SEL /*!< PLLSAI1 clock used as SAI1 clock source */ +#if defined(RCC_PLLSAI2_SUPPORT) +#define LL_RCC_SAI1_CLKSOURCE_PLLSAI2 (RCC_CCIPR_SAI1SEL | (RCC_CCIPR_SAI1SEL_0 >> 16U)) /*!< PLLSAI2 clock used as SAI1 clock source */ +#endif /* RCC_PLLSAI2_SUPPORT */ +#define LL_RCC_SAI1_CLKSOURCE_PLL (RCC_CCIPR_SAI1SEL | (RCC_CCIPR_SAI1SEL_1 >> 16U)) /*!< PLL clock used as SAI1 clock source */ +#define LL_RCC_SAI1_CLKSOURCE_PIN (RCC_CCIPR_SAI1SEL | (RCC_CCIPR_SAI1SEL >> 16U)) /*!< External input clock used as SAI1 clock source */ +#endif /* RCC_CCIPR2_SAI1SEL */ + +#if defined(RCC_CCIPR2_SAI2SEL) +#define LL_RCC_SAI2_CLKSOURCE_PLLSAI1 (RCC_CCIPR2_SAI2SEL << 16U) /*!< PLLSAI1 (PLLSAI1CLK) clock used as SAI2 clock source */ +#define LL_RCC_SAI2_CLKSOURCE_PLLSAI2 ((RCC_CCIPR2_SAI2SEL << 16U) | RCC_CCIPR2_SAI2SEL_0) /*!< PLLSAI2 (PLLSAI2CLK) clock used as SAI2 clock source */ +#define LL_RCC_SAI2_CLKSOURCE_PLL ((RCC_CCIPR2_SAI2SEL << 16U) | RCC_CCIPR2_SAI2SEL_1) /*!< PLL (PLLSAI3CLK) clock used as SAI2 clock source */ +#define LL_RCC_SAI2_CLKSOURCE_PIN ((RCC_CCIPR2_SAI2SEL << 16U) | (RCC_CCIPR2_SAI2SEL_1 | RCC_CCIPR2_SAI2SEL_0)) /*!< External input clock used as SAI2 clock source */ +#define LL_RCC_SAI2_CLKSOURCE_HSI ((RCC_CCIPR2_SAI2SEL << 16U) | RCC_CCIPR2_SAI2SEL_2) /*!< HSI clock used as SAI2 clock source */ +#elif defined(RCC_CCIPR_SAI2SEL) +#define LL_RCC_SAI2_CLKSOURCE_PLLSAI1 RCC_CCIPR_SAI2SEL /*!< PLLSAI1 clock used as SAI2 clock source */ +#if defined(RCC_PLLSAI2_SUPPORT) +#define LL_RCC_SAI2_CLKSOURCE_PLLSAI2 (RCC_CCIPR_SAI2SEL | (RCC_CCIPR_SAI2SEL_0 >> 16U)) /*!< PLLSAI2 clock used as SAI2 clock source */ +#endif /* RCC_PLLSAI2_SUPPORT */ +#define LL_RCC_SAI2_CLKSOURCE_PLL (RCC_CCIPR_SAI2SEL | (RCC_CCIPR_SAI2SEL_1 >> 16U)) /*!< PLL clock used as SAI2 clock source */ +#define LL_RCC_SAI2_CLKSOURCE_PIN (RCC_CCIPR_SAI2SEL | (RCC_CCIPR_SAI2SEL >> 16U)) /*!< External input clock used as SAI2 clock source */ +#endif /* RCC_CCIPR2_SAI2SEL */ +/** + * @} + */ + +#if defined(RCC_CCIPR2_SDMMCSEL) +/** @defgroup RCC_LL_EC_SDMMC1_KERNELCLKSOURCE Peripheral SDMMC kernel clock source selection + * @{ + */ +#define LL_RCC_SDMMC1_KERNELCLKSOURCE_48CLK 0x00000000U /*!< 48MHz clock from internal multiplexor used as SDMMC1 clock source */ +#define LL_RCC_SDMMC1_KERNELCLKSOURCE_PLLP RCC_CCIPR2_SDMMCSEL /*!< PLLSAI3CLK clock used as SDMMC1 clock source */ +/** + * @} + */ +#endif /* RCC_CCIPR2_SDMMCSEL */ + +#if defined(SDMMC1) +/** @defgroup RCC_LL_EC_SDMMC1_CLKSOURCE Peripheral SDMMC clock source selection + * @{ + */ +#if defined(RCC_HSI48_SUPPORT) +#define LL_RCC_SDMMC1_CLKSOURCE_HSI48 0x00000000U /*!< HSI48 clock used as SDMMC1 clock source */ +#else +#define LL_RCC_SDMMC1_CLKSOURCE_NONE 0x00000000U /*!< No clock used as SDMMC1 clock source */ +#endif +#if defined(RCC_PLLSAI1_SUPPORT) +#define LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 /*!< PLLSAI1 clock used as SDMMC1 clock source */ +#endif /* RCC_PLLSAI1_SUPPORT */ +#define LL_RCC_SDMMC1_CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 /*!< PLL clock used as SDMMC1 clock source */ +#define LL_RCC_SDMMC1_CLKSOURCE_MSI RCC_CCIPR_CLK48SEL /*!< MSI clock used as SDMMC1 clock source */ +/** + * @} + */ +#endif /* SDMMC1 */ + +/** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection + * @{ + */ +#if defined(RCC_HSI48_SUPPORT) +#define LL_RCC_RNG_CLKSOURCE_HSI48 0x00000000U /*!< HSI48 clock used as RNG clock source */ +#else +#define LL_RCC_RNG_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RNG clock source */ +#endif +#if defined(RCC_PLLSAI1_SUPPORT) +#define LL_RCC_RNG_CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 /*!< PLLSAI1 clock used as RNG clock source */ +#endif /* RCC_PLLSAI1_SUPPORT */ +#define LL_RCC_RNG_CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 /*!< PLL clock used as RNG clock source */ +#define LL_RCC_RNG_CLKSOURCE_MSI RCC_CCIPR_CLK48SEL /*!< MSI clock used as RNG clock source */ +/** + * @} + */ + +#if defined(USB_OTG_FS) || defined(USB) +/** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection + * @{ + */ +#if defined(RCC_HSI48_SUPPORT) +#define LL_RCC_USB_CLKSOURCE_HSI48 0x00000000U /*!< HSI48 clock used as USB clock source */ +#else +#define LL_RCC_USB_CLKSOURCE_NONE 0x00000000U /*!< No clock used as USB clock source */ +#endif +#if defined(RCC_PLLSAI1_SUPPORT) +#define LL_RCC_USB_CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 /*!< PLLSAI1 clock used as USB clock source */ +#endif /* RCC_PLLSAI1_SUPPORT */ +#define LL_RCC_USB_CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 /*!< PLL clock used as USB clock source */ +#define LL_RCC_USB_CLKSOURCE_MSI RCC_CCIPR_CLK48SEL /*!< MSI clock used as USB clock source */ +/** + * @} + */ + +#endif /* USB_OTG_FS || USB */ + +/** @defgroup RCC_LL_EC_ADC_CLKSOURCE Peripheral ADC clock source selection + * @{ + */ +#define LL_RCC_ADC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as ADC clock source */ +#if defined(RCC_PLLSAI1_SUPPORT) +#define LL_RCC_ADC_CLKSOURCE_PLLSAI1 RCC_CCIPR_ADCSEL_0 /*!< PLLSAI1 clock used as ADC clock source */ +#endif /* RCC_PLLSAI1_SUPPORT */ +#if defined(RCC_PLLSAI2_SUPPORT) && !defined(LTDC) +#define LL_RCC_ADC_CLKSOURCE_PLLSAI2 RCC_CCIPR_ADCSEL_1 /*!< PLLSAI2 clock used as ADC clock source */ +#endif /* RCC_PLLSAI2_SUPPORT */ +#if defined(RCC_CCIPR_ADCSEL) +#define LL_RCC_ADC_CLKSOURCE_SYSCLK RCC_CCIPR_ADCSEL /*!< SYSCLK clock used as ADC clock source */ +#else +#define LL_RCC_ADC_CLKSOURCE_SYSCLK 0x30000000U /*!< SYSCLK clock used as ADC clock source */ +#endif +/** + * @} + */ + +#if defined(SWPMI1) +/** @defgroup RCC_LL_EC_SWPMI1_CLKSOURCE Peripheral SWPMI1 clock source selection + * @{ + */ +#define LL_RCC_SWPMI1_CLKSOURCE_PCLK1 0x00000000U /*!< PCLK1 used as SWPMI1 clock source */ +#define LL_RCC_SWPMI1_CLKSOURCE_HSI RCC_CCIPR_SWPMI1SEL /*!< HSI used as SWPMI1 clock source */ +/** + * @} + */ +#endif /* SWPMI1 */ + +#if defined(DFSDM1_Channel0) +#if defined(RCC_CCIPR2_ADFSDM1SEL) +/** @defgroup RCC_LL_EC_DFSDM1_AUDIO_CLKSOURCE Peripheral DFSDM1 Audio clock source selection + * @{ + */ +#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1 0x00000000U /*!< SAI1 clock used as DFSDM1 Audio clock */ +#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_HSI RCC_CCIPR2_ADFSDM1SEL_0 /*!< HSI clock used as DFSDM1 Audio clock */ +#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_MSI RCC_CCIPR2_ADFSDM1SEL_1 /*!< MSI clock used as DFSDM1 Audio clock */ +/** + * @} + */ +#endif /* RCC_CCIPR2_ADFSDM1SEL */ + +/** @defgroup RCC_LL_EC_DFSDM1_CLKSOURCE Peripheral DFSDM1 clock source selection + * @{ + */ +#if defined(RCC_CCIPR2_DFSDM1SEL) +#define LL_RCC_DFSDM1_CLKSOURCE_PCLK2 0x00000000U /*!< PCLK2 used as DFSDM1 clock source */ +#define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK RCC_CCIPR2_DFSDM1SEL /*!< SYSCLK used as DFSDM1 clock source */ +#else +#define LL_RCC_DFSDM1_CLKSOURCE_PCLK2 0x00000000U /*!< PCLK2 used as DFSDM1 clock source */ +#define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK RCC_CCIPR_DFSDM1SEL /*!< SYSCLK used as DFSDM1 clock source */ +#endif /* RCC_CCIPR2_DFSDM1SEL */ +/** + * @} + */ +#endif /* DFSDM1_Channel0 */ + +#if defined(DSI) +/** @defgroup RCC_LL_EC_DSI_CLKSOURCE Peripheral DSI clock source selection + * @{ + */ +#define LL_RCC_DSI_CLKSOURCE_PHY 0x00000000U /*!< DSI-PHY clock used as DSI byte lane clock source */ +#define LL_RCC_DSI_CLKSOURCE_PLL RCC_CCIPR2_DSISEL /*!< PLL clock used as DSI byte lane clock source */ +/** + * @} + */ +#endif /* DSI */ + +#if defined(LTDC) +/** @defgroup RCC_LL_EC_LTDC_CLKSOURCE Peripheral LTDC clock source selection + * @{ + */ +#define LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV2 0x00000000U /*!< PLLSAI2DIVR divided by 2 used as LTDC clock source */ +#define LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV4 RCC_CCIPR2_PLLSAI2DIVR_0 /*!< PLLSAI2DIVR divided by 4 used as LTDC clock source */ +#define LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV8 RCC_CCIPR2_PLLSAI2DIVR_1 /*!< PLLSAI2DIVR divided by 8 used as LTDC clock source */ +#define LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV16 RCC_CCIPR2_PLLSAI2DIVR /*!< PLLSAI2DIVR divided by 16 used as LTDC clock source */ +/** + * @} + */ +#endif /* LTDC */ + +#if defined(OCTOSPI1) +/** @defgroup RCC_LL_EC_OCTOSPI Peripheral OCTOSPI get clock source + * @{ + */ +#define LL_RCC_OCTOSPI_CLKSOURCE_SYSCLK 0x00000000U /*!< SYSCLK used as OctoSPI clock source */ +#define LL_RCC_OCTOSPI_CLKSOURCE_MSI RCC_CCIPR2_OSPISEL_0 /*!< MSI used as OctoSPI clock source */ +#define LL_RCC_OCTOSPI_CLKSOURCE_PLL RCC_CCIPR2_OSPISEL_1 /*!< PLL used as OctoSPI clock source */ +/** + * @} + */ +#endif /* OCTOSPI1 */ + +/** @defgroup RCC_LL_EC_USART1 Peripheral USART get clock source + * @{ + */ +#define LL_RCC_USART1_CLKSOURCE RCC_CCIPR_USART1SEL /*!< USART1 Clock source selection */ +#define LL_RCC_USART2_CLKSOURCE RCC_CCIPR_USART2SEL /*!< USART2 Clock source selection */ +#if defined(RCC_CCIPR_USART3SEL) +#define LL_RCC_USART3_CLKSOURCE RCC_CCIPR_USART3SEL /*!< USART3 Clock source selection */ +#endif /* RCC_CCIPR_USART3SEL */ +/** + * @} + */ + +#if defined(RCC_CCIPR_UART4SEL) || defined(RCC_CCIPR_UART5SEL) +/** @defgroup RCC_LL_EC_UART4 Peripheral UART get clock source + * @{ + */ +#if defined(RCC_CCIPR_UART4SEL) +#define LL_RCC_UART4_CLKSOURCE RCC_CCIPR_UART4SEL /*!< UART4 Clock source selection */ +#endif /* RCC_CCIPR_UART4SEL */ +#if defined(RCC_CCIPR_UART5SEL) +#define LL_RCC_UART5_CLKSOURCE RCC_CCIPR_UART5SEL /*!< UART5 Clock source selection */ +#endif /* RCC_CCIPR_UART5SEL */ +/** + * @} + */ +#endif /* RCC_CCIPR_UART4SEL || RCC_CCIPR_UART5SEL */ + +/** @defgroup RCC_LL_EC_LPUART1 Peripheral LPUART get clock source + * @{ + */ +#define LL_RCC_LPUART1_CLKSOURCE RCC_CCIPR_LPUART1SEL /*!< LPUART1 Clock source selection */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_I2C1 Peripheral I2C get clock source + * @{ + */ +#define LL_RCC_I2C1_CLKSOURCE ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C1SEL_Pos << 16U) | (RCC_CCIPR_I2C1SEL >> RCC_CCIPR_I2C1SEL_Pos)) /*!< I2C1 Clock source selection */ +#if defined(RCC_CCIPR_I2C2SEL) +#define LL_RCC_I2C2_CLKSOURCE ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C2SEL_Pos << 16U) | (RCC_CCIPR_I2C2SEL >> RCC_CCIPR_I2C2SEL_Pos)) /*!< I2C2 Clock source selection */ +#endif /* RCC_CCIPR_I2C2SEL */ +#define LL_RCC_I2C3_CLKSOURCE ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C3SEL_Pos << 16U) | (RCC_CCIPR_I2C3SEL >> RCC_CCIPR_I2C3SEL_Pos)) /*!< I2C3 Clock source selection */ +#if defined(RCC_CCIPR2_I2C4SEL) +#define LL_RCC_I2C4_CLKSOURCE ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C4SEL_Pos << 16U) | (RCC_CCIPR2_I2C4SEL >> RCC_CCIPR2_I2C4SEL_Pos)) /*!< I2C4 Clock source selection */ +#endif /* RCC_CCIPR2_I2C4SEL */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_LPTIM1 Peripheral LPTIM get clock source + * @{ + */ +#define LL_RCC_LPTIM1_CLKSOURCE RCC_CCIPR_LPTIM1SEL /*!< LPTIM1 Clock source selection */ +#define LL_RCC_LPTIM2_CLKSOURCE RCC_CCIPR_LPTIM2SEL /*!< LPTIM2 Clock source selection */ +/** + * @} + */ + +#if defined(RCC_CCIPR_SAI1SEL) || defined(RCC_CCIPR2_SAI1SEL) +/** @defgroup RCC_LL_EC_SAI1 Peripheral SAI get clock source + * @{ + */ +#if defined(RCC_CCIPR2_SAI1SEL) +#define LL_RCC_SAI1_CLKSOURCE RCC_CCIPR2_SAI1SEL /*!< SAI1 Clock source selection */ +#else +#define LL_RCC_SAI1_CLKSOURCE RCC_CCIPR_SAI1SEL /*!< SAI1 Clock source selection */ +#endif /* RCC_CCIPR2_SAI1SEL */ +#if defined(RCC_CCIPR2_SAI2SEL) +#define LL_RCC_SAI2_CLKSOURCE RCC_CCIPR2_SAI2SEL /*!< SAI2 Clock source selection */ +#elif defined(RCC_CCIPR_SAI2SEL) +#define LL_RCC_SAI2_CLKSOURCE RCC_CCIPR_SAI2SEL /*!< SAI2 Clock source selection */ +#endif /* RCC_CCIPR2_SAI2SEL */ +/** + * @} + */ +#endif /* RCC_CCIPR_SAI1SEL || RCC_CCIPR2_SAI1SEL */ + +#if defined(SDMMC1) +#if defined(RCC_CCIPR2_SDMMCSEL) +/** @defgroup RCC_LL_EC_SDMMC1_KERNEL Peripheral SDMMC get kernel clock source + * @{ + */ +#define LL_RCC_SDMMC1_KERNELCLKSOURCE RCC_CCIPR2_SDMMCSEL /*!< SDMMC1 Kernel Clock source selection */ +/** + * @} + */ +#endif /* RCC_CCIPR2_SDMMCSEL */ + +/** @defgroup RCC_LL_EC_SDMMC1 Peripheral SDMMC get clock source + * @{ + */ +#define LL_RCC_SDMMC1_CLKSOURCE RCC_CCIPR_CLK48SEL /*!< SDMMC1 Clock source selection */ +/** + * @} + */ +#endif /* SDMMC1 */ + +/** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source + * @{ + */ +#define LL_RCC_RNG_CLKSOURCE RCC_CCIPR_CLK48SEL /*!< RNG Clock source selection */ +/** + * @} + */ + +#if defined(USB_OTG_FS) || defined(USB) +/** @defgroup RCC_LL_EC_USB Peripheral USB get clock source + * @{ + */ +#define LL_RCC_USB_CLKSOURCE RCC_CCIPR_CLK48SEL /*!< USB Clock source selection */ +/** + * @} + */ +#endif /* USB_OTG_FS || USB */ + +/** @defgroup RCC_LL_EC_ADC Peripheral ADC get clock source + * @{ + */ +#if defined(RCC_CCIPR_ADCSEL) +#define LL_RCC_ADC_CLKSOURCE RCC_CCIPR_ADCSEL /*!< ADC Clock source selection */ +#else +#define LL_RCC_ADC_CLKSOURCE 0x30000000U /*!< ADC Clock source selection */ +#endif +/** + * @} + */ + +#if defined(SWPMI1) +/** @defgroup RCC_LL_EC_SWPMI1 Peripheral SWPMI1 get clock source + * @{ + */ +#define LL_RCC_SWPMI1_CLKSOURCE RCC_CCIPR_SWPMI1SEL /*!< SWPMI1 Clock source selection */ +/** + * @} + */ +#endif /* SWPMI1 */ + +#if defined(DFSDM1_Channel0) +#if defined(RCC_CCIPR2_ADFSDM1SEL) +/** @defgroup RCC_LL_EC_DFSDM1_AUDIO Peripheral DFSDM1 Audio get clock source + * @{ + */ +#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE RCC_CCIPR2_ADFSDM1SEL /* DFSDM1 Audio Clock source selection */ +/** + * @} + */ + +#endif /* RCC_CCIPR2_ADFSDM1SEL */ +/** @defgroup RCC_LL_EC_DFSDM1 Peripheral DFSDM1 get clock source + * @{ + */ +#if defined(RCC_CCIPR2_DFSDM1SEL) +#define LL_RCC_DFSDM1_CLKSOURCE RCC_CCIPR2_DFSDM1SEL /*!< DFSDM1 Clock source selection */ +#else +#define LL_RCC_DFSDM1_CLKSOURCE RCC_CCIPR_DFSDM1SEL /*!< DFSDM1 Clock source selection */ +#endif /* RCC_CCIPR2_DFSDM1SEL */ +/** + * @} + */ +#endif /* DFSDM1_Channel0 */ + +#if defined(DSI) +/** @defgroup RCC_LL_EC_DSI Peripheral DSI get clock source + * @{ + */ +#define LL_RCC_DSI_CLKSOURCE RCC_CCIPR2_DSISEL /*!< DSI Clock source selection */ +/** + * @} + */ +#endif /* DSI */ + +#if defined(LTDC) +/** @defgroup RCC_LL_EC_LTDC Peripheral LTDC get clock source + * @{ + */ +#define LL_RCC_LTDC_CLKSOURCE RCC_CCIPR2_PLLSAI2DIVR /*!< LTDC Clock source selection */ +/** + * @} + */ +#endif /* LTDC */ + +#if defined(OCTOSPI1) +/** @defgroup RCC_LL_EC_OCTOSPI Peripheral OCTOSPI get clock source + * @{ + */ +#define LL_RCC_OCTOSPI_CLKSOURCE RCC_CCIPR2_OSPISEL /*!< OctoSPI Clock source selection */ +/** + * @} + */ +#endif /* OCTOSPI1 */ + + +/** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection + * @{ + */ +#define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */ +#define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ +#define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ +#define LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */ +/** + * @} + */ + + +/** @defgroup RCC_LL_EC_PLLSOURCE PLL, PLLSAI1 and PLLSAI2 entry clock source + * @{ + */ +#define LL_RCC_PLLSOURCE_NONE 0x00000000U /*!< No clock */ +#define LL_RCC_PLLSOURCE_MSI RCC_PLLCFGR_PLLSRC_MSI /*!< MSI clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /*!< HSI16 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PLLM_DIV PLL division factor + * @{ + */ +#define LL_RCC_PLLM_DIV_1 0x00000000U /*!< Main PLL division factor for PLLM input by 1 */ +#define LL_RCC_PLLM_DIV_2 (RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 2 */ +#define LL_RCC_PLLM_DIV_3 (RCC_PLLCFGR_PLLM_1) /*!< Main PLL division factor for PLLM input by 3 */ +#define LL_RCC_PLLM_DIV_4 (RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 4 */ +#define LL_RCC_PLLM_DIV_5 (RCC_PLLCFGR_PLLM_2) /*!< Main PLL division factor for PLLM input by 5 */ +#define LL_RCC_PLLM_DIV_6 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 6 */ +#define LL_RCC_PLLM_DIV_7 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< Main PLL division factor for PLLM input by 7 */ +#define LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 8 */ +#if defined(RCC_PLLM_DIV_1_16_SUPPORT) +#define LL_RCC_PLLM_DIV_9 (RCC_PLLCFGR_PLLM_3) /*!< Main PLL division factor for PLLM input by 9 */ +#define LL_RCC_PLLM_DIV_10 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 10 */ +#define LL_RCC_PLLM_DIV_11 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< Main PLL division factor for PLLM input by 11 */ +#define LL_RCC_PLLM_DIV_12 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 12 */ +#define LL_RCC_PLLM_DIV_13 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< Main PLL division factor for PLLM input by 13 */ +#define LL_RCC_PLLM_DIV_14 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 14 */ +#define LL_RCC_PLLM_DIV_15 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< Main PLL division factor for PLLM input by 15 */ +#define LL_RCC_PLLM_DIV_16 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 16 */ +#endif /* RCC_PLLM_DIV_1_16_SUPPORT */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PLLR_DIV PLL division factor (PLLR) + * @{ + */ +#define LL_RCC_PLLR_DIV_2 0x00000000U /*!< Main PLL division factor for PLLCLK (system clock) by 2 */ +#define LL_RCC_PLLR_DIV_4 (RCC_PLLCFGR_PLLR_0) /*!< Main PLL division factor for PLLCLK (system clock) by 4 */ +#define LL_RCC_PLLR_DIV_6 (RCC_PLLCFGR_PLLR_1) /*!< Main PLL division factor for PLLCLK (system clock) by 6 */ +#define LL_RCC_PLLR_DIV_8 (RCC_PLLCFGR_PLLR) /*!< Main PLL division factor for PLLCLK (system clock) by 8 */ +/** + * @} + */ + +#if defined(RCC_PLLP_SUPPORT) +/** @defgroup RCC_LL_EC_PLLP_DIV PLL division factor (PLLP) + * @{ + */ +#if defined(RCC_PLLP_DIV_2_31_SUPPORT) +#define LL_RCC_PLLP_DIV_2 (RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 2 */ +#define LL_RCC_PLLP_DIV_3 (RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 3 */ +#define LL_RCC_PLLP_DIV_4 (RCC_PLLCFGR_PLLPDIV_2) /*!< Main PLL division factor for PLLP output by 4 */ +#define LL_RCC_PLLP_DIV_5 (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 5 */ +#define LL_RCC_PLLP_DIV_6 (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 6 */ +#define LL_RCC_PLLP_DIV_7 (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 7 */ +#define LL_RCC_PLLP_DIV_8 (RCC_PLLCFGR_PLLPDIV_3) /*!< Main PLL division factor for PLLP output by 8 */ +#define LL_RCC_PLLP_DIV_9 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 9 */ +#define LL_RCC_PLLP_DIV_10 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 10 */ +#define LL_RCC_PLLP_DIV_11 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 11 */ +#define LL_RCC_PLLP_DIV_12 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2) /*!< Main PLL division factor for PLLP output by 12 */ +#define LL_RCC_PLLP_DIV_13 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 13 */ +#define LL_RCC_PLLP_DIV_14 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 14 */ +#define LL_RCC_PLLP_DIV_15 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 15 */ +#define LL_RCC_PLLP_DIV_16 (RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 16 */ +#define LL_RCC_PLLP_DIV_17 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 17 */ +#define LL_RCC_PLLP_DIV_18 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 18 */ +#define LL_RCC_PLLP_DIV_19 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 19 */ +#define LL_RCC_PLLP_DIV_20 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2) /*!< Main PLL division factor for PLLP output by 20 */ +#define LL_RCC_PLLP_DIV_21 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 21 */ +#define LL_RCC_PLLP_DIV_22 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 22 */ +#define LL_RCC_PLLP_DIV_23 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 23 */ +#define LL_RCC_PLLP_DIV_24 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3) /*!< Main PLL division factor for PLLP output by 24 */ +#define LL_RCC_PLLP_DIV_25 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 25 */ +#define LL_RCC_PLLP_DIV_26 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 26 */ +#define LL_RCC_PLLP_DIV_27 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 27 */ +#define LL_RCC_PLLP_DIV_28 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2) /*!< Main PLL division factor for PLLP output by 28 */ +#define LL_RCC_PLLP_DIV_29 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 29 */ +#define LL_RCC_PLLP_DIV_30 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 30 */ +#define LL_RCC_PLLP_DIV_31 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 31 */ +#else +#define LL_RCC_PLLP_DIV_7 0x00000000U /*!< Main PLL division factor for PLLP output by 7 */ +#define LL_RCC_PLLP_DIV_17 (RCC_PLLCFGR_PLLP) /*!< Main PLL division factor for PLLP output by 17 */ +#endif /* RCC_PLLP_DIV_2_31_SUPPORT */ +/** + * @} + */ +#endif /* RCC_PLLP_SUPPORT */ + +/** @defgroup RCC_LL_EC_PLLQ_DIV PLL division factor (PLLQ) + * @{ + */ +#define LL_RCC_PLLQ_DIV_2 0x00000000U /*!< Main PLL division factor for PLLQ output by 2 */ +#define LL_RCC_PLLQ_DIV_4 (RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 4 */ +#define LL_RCC_PLLQ_DIV_6 (RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 6 */ +#define LL_RCC_PLLQ_DIV_8 (RCC_PLLCFGR_PLLQ) /*!< Main PLL division factor for PLLQ output by 8 */ +/** + * @} + */ + +#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) +/** @defgroup RCC_LL_EC_PLLSAI1M PLLSAI1 division factor (PLLSAI1M) + * @{ + */ +#define LL_RCC_PLLSAI1M_DIV_1 0x00000000U /*!< PLLSAI1 division factor for PLLSAI1M input by 1 */ +#define LL_RCC_PLLSAI1M_DIV_2 (RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 2 */ +#define LL_RCC_PLLSAI1M_DIV_3 (RCC_PLLSAI1CFGR_PLLSAI1M_1) /*!< PLLSAI1 division factor for PLLSAI1M input by 3 */ +#define LL_RCC_PLLSAI1M_DIV_4 (RCC_PLLSAI1CFGR_PLLSAI1M_1|RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 4 */ +#define LL_RCC_PLLSAI1M_DIV_5 (RCC_PLLSAI1CFGR_PLLSAI1M_2) /*!< PLLSAI1 division factor for PLLSAI1M input by 5 */ +#define LL_RCC_PLLSAI1M_DIV_6 (RCC_PLLSAI1CFGR_PLLSAI1M_2|RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 6 */ +#define LL_RCC_PLLSAI1M_DIV_7 (RCC_PLLSAI1CFGR_PLLSAI1M_2|RCC_PLLSAI1CFGR_PLLSAI1M_1) /*!< PLLSAI1 division factor for PLLSAI1M input by 7 */ +#define LL_RCC_PLLSAI1M_DIV_8 (RCC_PLLSAI1CFGR_PLLSAI1M_2|RCC_PLLSAI1CFGR_PLLSAI1M_1|RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 8 */ +#define LL_RCC_PLLSAI1M_DIV_9 (RCC_PLLSAI1CFGR_PLLSAI1M_3) /*!< PLLSAI1 division factor for PLLSAI1M input by 9 */ +#define LL_RCC_PLLSAI1M_DIV_10 (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 10 */ +#define LL_RCC_PLLSAI1M_DIV_11 (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_1) /*!< PLLSAI1 division factor for PLLSAI1M input by 11 */ +#define LL_RCC_PLLSAI1M_DIV_12 (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_1|RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 12 */ +#define LL_RCC_PLLSAI1M_DIV_13 (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_2) /*!< PLLSAI1 division factor for PLLSAI1M input by 13 */ +#define LL_RCC_PLLSAI1M_DIV_14 (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_2|RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 14 */ +#define LL_RCC_PLLSAI1M_DIV_15 (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_2|RCC_PLLSAI1CFGR_PLLSAI1M_1) /*!< PLLSAI1 division factor for PLLSAI1M input by 15 */ +#define LL_RCC_PLLSAI1M_DIV_16 (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_2|RCC_PLLSAI1CFGR_PLLSAI1M_1|RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 16 */ +/** + * @} + */ +#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ + +#if defined(RCC_PLLSAI1_SUPPORT) +/** @defgroup RCC_LL_EC_PLLSAI1Q PLLSAI1 division factor (PLLSAI1Q) + * @{ + */ +#define LL_RCC_PLLSAI1Q_DIV_2 0x00000000U /*!< PLLSAI1 division factor for PLLSAI1Q output by 2 */ +#define LL_RCC_PLLSAI1Q_DIV_4 (RCC_PLLSAI1CFGR_PLLSAI1Q_0) /*!< PLLSAI1 division factor for PLLSAI1Q output by 4 */ +#define LL_RCC_PLLSAI1Q_DIV_6 (RCC_PLLSAI1CFGR_PLLSAI1Q_1) /*!< PLLSAI1 division factor for PLLSAI1Q output by 6 */ +#define LL_RCC_PLLSAI1Q_DIV_8 (RCC_PLLSAI1CFGR_PLLSAI1Q) /*!< PLLSAI1 division factor for PLLSAI1Q output by 8 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PLLSAI1P PLLSAI1 division factor (PLLSAI1P) + * @{ + */ +#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) +#define LL_RCC_PLLSAI1P_DIV_2 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 2 */ +#define LL_RCC_PLLSAI1P_DIV_3 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 3 */ +#define LL_RCC_PLLSAI1P_DIV_4 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /*!< PLLSAI1 division factor for PLLSAI1P output by 4 */ +#define LL_RCC_PLLSAI1P_DIV_5 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 5 */ +#define LL_RCC_PLLSAI1P_DIV_6 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 6 */ +#define LL_RCC_PLLSAI1P_DIV_7 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 7 */ +#define LL_RCC_PLLSAI1P_DIV_8 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /*!< PLLSAI1 division factor for PLLSAI1P output by 8 */ +#define LL_RCC_PLLSAI1P_DIV_9 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 9 */ +#define LL_RCC_PLLSAI1P_DIV_10 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 10 */ +#define LL_RCC_PLLSAI1P_DIV_11 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 1 */ +#define LL_RCC_PLLSAI1P_DIV_12 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /*!< PLLSAI1 division factor for PLLSAI1P output by 12 */ +#define LL_RCC_PLLSAI1P_DIV_13 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 13 */ +#define LL_RCC_PLLSAI1P_DIV_14 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 14 */ +#define LL_RCC_PLLSAI1P_DIV_15 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 15 */ +#define LL_RCC_PLLSAI1P_DIV_16 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 16 */ +#define LL_RCC_PLLSAI1P_DIV_17 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 17 */ +#define LL_RCC_PLLSAI1P_DIV_18 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 18 */ +#define LL_RCC_PLLSAI1P_DIV_19 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 19 */ +#define LL_RCC_PLLSAI1P_DIV_20 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /*!< PLLSAI1 division factor for PLLSAI1P output by 20 */ +#define LL_RCC_PLLSAI1P_DIV_21 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division fctor for PLLSAI1P output by 21 */ +#define LL_RCC_PLLSAI1P_DIV_22 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 22 */ +#define LL_RCC_PLLSAI1P_DIV_23 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 23 */ +#define LL_RCC_PLLSAI1P_DIV_24 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /*!< PLLSAI1 division factor for PLLSAI1P output by 24 */ +#define LL_RCC_PLLSAI1P_DIV_25 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 25 */ +#define LL_RCC_PLLSAI1P_DIV_26 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 26 */ +#define LL_RCC_PLLSAI1P_DIV_27 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 27 */ +#define LL_RCC_PLLSAI1P_DIV_28 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /*!< PLLSAI1 division factor for PLLSAI1P output by 28 */ +#define LL_RCC_PLLSAI1P_DIV_29 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 29 */ +#define LL_RCC_PLLSAI1P_DIV_30 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 30 */ +#define LL_RCC_PLLSAI1P_DIV_31 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 31 */ +#else +#define LL_RCC_PLLSAI1P_DIV_7 0x00000000U /*!< PLLSAI1 division factor for PLLSAI1P output by 7 */ +#define LL_RCC_PLLSAI1P_DIV_17 (RCC_PLLSAI1CFGR_PLLSAI1P) /*!< PLLSAI1 division factor for PLLSAI1P output by 17 */ +#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PLLSAI1R PLLSAI1 division factor (PLLSAI1R) + * @{ + */ +#define LL_RCC_PLLSAI1R_DIV_2 0x00000000U /*!< PLLSAI1 division factor for PLLSAI1R output by 2 */ +#define LL_RCC_PLLSAI1R_DIV_4 (RCC_PLLSAI1CFGR_PLLSAI1R_0) /*!< PLLSAI1 division factor for PLLSAI1R output by 4 */ +#define LL_RCC_PLLSAI1R_DIV_6 (RCC_PLLSAI1CFGR_PLLSAI1R_1) /*!< PLLSAI1 division factor for PLLSAI1R output by 6 */ +#define LL_RCC_PLLSAI1R_DIV_8 (RCC_PLLSAI1CFGR_PLLSAI1R) /*!< PLLSAI1 division factor for PLLSAI1R output by 8 */ +/** + * @} + */ +#endif /* RCC_PLLSAI1_SUPPORT */ + +#if defined(RCC_PLLSAI2_SUPPORT) +#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) +/** @defgroup RCC_LL_EC_PLLSAI2M PLLSAI1 division factor (PLLSAI2M) + * @{ + */ +#define LL_RCC_PLLSAI2M_DIV_1 0x00000000U /*!< PLLSAI2 division factor for PLLSAI2M input by 1 */ +#define LL_RCC_PLLSAI2M_DIV_2 (RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 2 */ +#define LL_RCC_PLLSAI2M_DIV_3 (RCC_PLLSAI2CFGR_PLLSAI2M_1) /*!< PLLSAI2 division factor for PLLSAI2M input by 3 */ +#define LL_RCC_PLLSAI2M_DIV_4 (RCC_PLLSAI2CFGR_PLLSAI2M_1|RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 4 */ +#define LL_RCC_PLLSAI2M_DIV_5 (RCC_PLLSAI2CFGR_PLLSAI2M_2) /*!< PLLSAI2 division factor for PLLSAI2M input by 5 */ +#define LL_RCC_PLLSAI2M_DIV_6 (RCC_PLLSAI2CFGR_PLLSAI2M_2|RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 6 */ +#define LL_RCC_PLLSAI2M_DIV_7 (RCC_PLLSAI2CFGR_PLLSAI2M_2|RCC_PLLSAI2CFGR_PLLSAI2M_1) /*!< PLLSAI2 division factor for PLLSAI2M input by 7 */ +#define LL_RCC_PLLSAI2M_DIV_8 (RCC_PLLSAI2CFGR_PLLSAI2M_2|RCC_PLLSAI2CFGR_PLLSAI2M_1|RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 8 */ +#define LL_RCC_PLLSAI2M_DIV_9 (RCC_PLLSAI2CFGR_PLLSAI2M_3) /*!< PLLSAI2 division factor for PLLSAI2M input by 9 */ +#define LL_RCC_PLLSAI2M_DIV_10 (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 10 */ +#define LL_RCC_PLLSAI2M_DIV_11 (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_1) /*!< PLLSAI2 division factor for PLLSAI2M input by 11 */ +#define LL_RCC_PLLSAI2M_DIV_12 (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_1|RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 12 */ +#define LL_RCC_PLLSAI2M_DIV_13 (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_2) /*!< PLLSAI2 division factor for PLLSAI2M input by 13 */ +#define LL_RCC_PLLSAI2M_DIV_14 (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_2|RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 14 */ +#define LL_RCC_PLLSAI2M_DIV_15 (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_2|RCC_PLLSAI2CFGR_PLLSAI2M_1) /*!< PLLSAI2 division factor for PLLSAI2M input by 15 */ +#define LL_RCC_PLLSAI2M_DIV_16 (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_2|RCC_PLLSAI2CFGR_PLLSAI2M_1|RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 16 */ +/** + * @} + */ +#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */ + +#if defined(RCC_PLLSAI2Q_DIV_SUPPORT) +/** @defgroup RCC_LL_EC_PLLSAI2Q PLLSAI2 division factor (PLLSAI2Q) + * @{ + */ +#define LL_RCC_PLLSAI2Q_DIV_2 0x00000000U /*!< PLLSAI2 division factor for PLLSAI2Q output by 2 */ +#define LL_RCC_PLLSAI2Q_DIV_4 (RCC_PLLSAI2CFGR_PLLSAI2Q_0) /*!< PLLSAI2 division factor for PLLSAI2Q output by 4 */ +#define LL_RCC_PLLSAI2Q_DIV_6 (RCC_PLLSAI2CFGR_PLLSAI2Q_1) /*!< PLLSAI2 division factor for PLLSAI2Q output by 6 */ +#define LL_RCC_PLLSAI2Q_DIV_8 (RCC_PLLSAI2CFGR_PLLSAI2Q) /*!< PLLSAI2 division factor for PLLSAI2Q output by 8 */ +/** + * @} + */ +#endif /* RCC_PLLSAI2Q_DIV_SUPPORT */ + +/** @defgroup RCC_LL_EC_PLLSAI2P PLLSAI2 division factor (PLLSAI2P) + * @{ + */ +#if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) +#define LL_RCC_PLLSAI2P_DIV_2 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 2 */ +#define LL_RCC_PLLSAI2P_DIV_3 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 3 */ +#define LL_RCC_PLLSAI2P_DIV_4 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_2) /*!< PLLSAI2 division factor for PLLSAI2P output by 4 */ +#define LL_RCC_PLLSAI2P_DIV_5 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 5 */ +#define LL_RCC_PLLSAI2P_DIV_6 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 6 */ +#define LL_RCC_PLLSAI2P_DIV_7 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 7 */ +#define LL_RCC_PLLSAI2P_DIV_8 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3) /*!< PLLSAI2 division factor for PLLSAI2P output by 8 */ +#define LL_RCC_PLLSAI2P_DIV_9 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 9 */ +#define LL_RCC_PLLSAI2P_DIV_10 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 10 */ +#define LL_RCC_PLLSAI2P_DIV_11 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 1 */ +#define LL_RCC_PLLSAI2P_DIV_12 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2) /*!< PLLSAI2 division factor for PLLSAI2P output by 12 */ +#define LL_RCC_PLLSAI2P_DIV_13 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 13 */ +#define LL_RCC_PLLSAI2P_DIV_14 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 14 */ +#define LL_RCC_PLLSAI2P_DIV_15 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 15 */ +#define LL_RCC_PLLSAI2P_DIV_16 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4) /*!< PLLSAI2 division factor for PLLSAI2P output by 16 */ +#define LL_RCC_PLLSAI2P_DIV_17 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 17 */ +#define LL_RCC_PLLSAI2P_DIV_18 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 18 */ +#define LL_RCC_PLLSAI2P_DIV_19 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 19 */ +#define LL_RCC_PLLSAI2P_DIV_20 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2) /*!< PLLSAI2 division factor for PLLSAI2P output by 20 */ +#define LL_RCC_PLLSAI2P_DIV_21 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division fctor for PLLSAI2P output by 21 */ +#define LL_RCC_PLLSAI2P_DIV_22 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 22 */ +#define LL_RCC_PLLSAI2P_DIV_23 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 23 */ +#define LL_RCC_PLLSAI2P_DIV_24 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3) /*!< PLLSAI2 division factor for PLLSAI2P output by 24 */ +#define LL_RCC_PLLSAI2P_DIV_25 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 25 */ +#define LL_RCC_PLLSAI2P_DIV_26 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 26 */ +#define LL_RCC_PLLSAI2P_DIV_27 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 27 */ +#define LL_RCC_PLLSAI2P_DIV_28 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2) /*!< PLLSAI2 division factor for PLLSAI2P output by 28 */ +#define LL_RCC_PLLSAI2P_DIV_29 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 29 */ +#define LL_RCC_PLLSAI2P_DIV_30 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 30 */ +#define LL_RCC_PLLSAI2P_DIV_31 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 31 */ +#else +#define LL_RCC_PLLSAI2P_DIV_7 0x00000000U /*!< PLLSAI2 division factor for PLLSAI2P output by 7 */ +#define LL_RCC_PLLSAI2P_DIV_17 (RCC_PLLSAI2CFGR_PLLSAI2P) /*!< PLLSAI2 division factor for PLLSAI2P output by 17 */ +#endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PLLSAI2R PLLSAI2 division factor (PLLSAI2R) + * @{ + */ +#define LL_RCC_PLLSAI2R_DIV_2 0x00000000U /*!< PLLSAI2 division factor for PLLSAI2R output by 2 */ +#define LL_RCC_PLLSAI2R_DIV_4 (RCC_PLLSAI2CFGR_PLLSAI2R_0) /*!< PLLSAI2 division factor for PLLSAI2R output by 4 */ +#define LL_RCC_PLLSAI2R_DIV_6 (RCC_PLLSAI2CFGR_PLLSAI2R_1) /*!< PLLSAI2 division factor for PLLSAI2R output by 6 */ +#define LL_RCC_PLLSAI2R_DIV_8 (RCC_PLLSAI2CFGR_PLLSAI2R) /*!< PLLSAI2 division factor for PLLSAI2R output by 8 */ +/** + * @} + */ + +#if defined(RCC_CCIPR2_PLLSAI2DIVR) +/** @defgroup RCC_LL_EC_PLLSAI2DIVR PLLSAI2DIVR division factor (PLLSAI2DIVR) + * @{ + */ +#define LL_RCC_PLLSAI2DIVR_DIV_2 0x00000000U /*!< PLLSAI2 division factor for PLLSAI2DIVR output by 2 */ +#define LL_RCC_PLLSAI2DIVR_DIV_4 RCC_CCIPR2_PLLSAI2DIVR_0 /*!< PLLSAI2 division factor for PLLSAI2DIVR output by 4 */ +#define LL_RCC_PLLSAI2DIVR_DIV_8 RCC_CCIPR2_PLLSAI2DIVR_1 /*!< PLLSAI2 division factor for PLLSAI2DIVR output by 8 */ +#define LL_RCC_PLLSAI2DIVR_DIV_16 (RCC_CCIPR2_PLLSAI2DIVR_1 | RCC_CCIPR2_PLLSAI2DIVR_0) /*!< PLLSAI2 division factor for PLLSAI2DIVR output by 16 */ +/** + * @} + */ +#endif /* RCC_CCIPR2_PLLSAI2DIVR */ +#endif /* RCC_PLLSAI2_SUPPORT */ + +/** @defgroup RCC_LL_EC_MSIRANGESEL MSI clock range selection + * @{ + */ +#define LL_RCC_MSIRANGESEL_STANDBY 0U /*!< MSI Range is provided by MSISRANGE */ +#define LL_RCC_MSIRANGESEL_RUN 1U /*!< MSI Range is provided by MSIRANGE */ +/** + * @} + */ + +#if defined(RCC_CSR_LSIPREDIV) +/** @defgroup RCC_LL_EC_LSIPREDIV LSI division factor + * @{ + */ +#define LL_RCC_LSI_PREDIV_1 0x00000000U /*!< LSI division factor by 1 */ +#define LL_RCC_LSI_PREDIV_128 RCC_CSR_LSIPREDIV /*!< LSI division factor by 128 */ +/** + * @} + */ +#endif /* RCC_CSR_LSIPREDIV */ + +/** Legacy definitions for compatibility purpose +@cond 0 +*/ +#if defined(DFSDM1_Channel0) +#define LL_RCC_DFSDM1_CLKSOURCE_PCLK LL_RCC_DFSDM1_CLKSOURCE_PCLK2 +#define LL_RCC_DFSDM_CLKSOURCE_PCLK LL_RCC_DFSDM1_CLKSOURCE_PCLK2 +#define LL_RCC_DFSDM_CLKSOURCE_SYSCLK LL_RCC_DFSDM1_CLKSOURCE_SYSCLK +#define LL_RCC_DFSDM_CLKSOURCE LL_RCC_DFSDM1_CLKSOURCE +#endif /* DFSDM1_Channel0 */ +#if defined(SWPMI1) +#define LL_RCC_SWPMI1_CLKSOURCE_PCLK LL_RCC_SWPMI1_CLKSOURCE_PCLK1 +#endif /* SWPMI1 */ +/** +@endcond + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros + * @{ + */ + +/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in RCC register + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__)) + +/** + * @brief Read a value in RCC register + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__) +/** + * @} + */ + +/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies + * @{ + */ + +/** + * @brief Helper macro to calculate the PLLCLK frequency on system domain + * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), + * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ()); + * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI) + * @param __PLLM__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_1 + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 (*) + * @arg @ref LL_RCC_PLLM_DIV_10 (*) + * @arg @ref LL_RCC_PLLM_DIV_11 (*) + * @arg @ref LL_RCC_PLLM_DIV_12 (*) + * @arg @ref LL_RCC_PLLM_DIV_13 (*) + * @arg @ref LL_RCC_PLLM_DIV_14 (*) + * @arg @ref LL_RCC_PLLM_DIV_15 (*) + * @arg @ref LL_RCC_PLLM_DIV_16 (*) + * + * (*) value not defined in all devices. + * @param __PLLN__ Between 8 and 86 or 127 depending on devices + * @param __PLLR__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLR_DIV_2 + * @arg @ref LL_RCC_PLLR_DIV_4 + * @arg @ref LL_RCC_PLLR_DIV_6 + * @arg @ref LL_RCC_PLLR_DIV_8 + * @retval PLL clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \ + ((((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos) + 1U) * 2U)) + +#if defined(RCC_PLLSAI1_SUPPORT) +#if defined(RCC_PLLP_DIV_2_31_SUPPORT) +/** + * @brief Helper macro to calculate the PLLCLK frequency used on SAI domain + * @note ex: @ref __LL_RCC_CALC_PLLCLK_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), + * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ()); + * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI) + * @param __PLLM__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_1 + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 (*) + * @arg @ref LL_RCC_PLLM_DIV_10 (*) + * @arg @ref LL_RCC_PLLM_DIV_11 (*) + * @arg @ref LL_RCC_PLLM_DIV_12 (*) + * @arg @ref LL_RCC_PLLM_DIV_13 (*) + * @arg @ref LL_RCC_PLLM_DIV_14 (*) + * @arg @ref LL_RCC_PLLM_DIV_15 (*) + * @arg @ref LL_RCC_PLLM_DIV_16 (*) + * + * (*) value not defined in all devices. + * @param __PLLN__ Between 8 and 86 or 127 depending on devices + * @param __PLLP__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLP_DIV_2 + * @arg @ref LL_RCC_PLLP_DIV_3 + * @arg @ref LL_RCC_PLLP_DIV_4 + * @arg @ref LL_RCC_PLLP_DIV_5 + * @arg @ref LL_RCC_PLLP_DIV_6 + * @arg @ref LL_RCC_PLLP_DIV_7 + * @arg @ref LL_RCC_PLLP_DIV_8 + * @arg @ref LL_RCC_PLLP_DIV_9 + * @arg @ref LL_RCC_PLLP_DIV_10 + * @arg @ref LL_RCC_PLLP_DIV_11 + * @arg @ref LL_RCC_PLLP_DIV_12 + * @arg @ref LL_RCC_PLLP_DIV_13 + * @arg @ref LL_RCC_PLLP_DIV_14 + * @arg @ref LL_RCC_PLLP_DIV_15 + * @arg @ref LL_RCC_PLLP_DIV_16 + * @arg @ref LL_RCC_PLLP_DIV_17 + * @arg @ref LL_RCC_PLLP_DIV_18 + * @arg @ref LL_RCC_PLLP_DIV_19 + * @arg @ref LL_RCC_PLLP_DIV_20 + * @arg @ref LL_RCC_PLLP_DIV_21 + * @arg @ref LL_RCC_PLLP_DIV_22 + * @arg @ref LL_RCC_PLLP_DIV_23 + * @arg @ref LL_RCC_PLLP_DIV_24 + * @arg @ref LL_RCC_PLLP_DIV_25 + * @arg @ref LL_RCC_PLLP_DIV_26 + * @arg @ref LL_RCC_PLLP_DIV_27 + * @arg @ref LL_RCC_PLLP_DIV_28 + * @arg @ref LL_RCC_PLLP_DIV_29 + * @arg @ref LL_RCC_PLLP_DIV_30 + * @arg @ref LL_RCC_PLLP_DIV_31 + * @retval PLL clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \ + ((__PLLP__) >> RCC_PLLCFGR_PLLPDIV_Pos)) + +#else +/** + * @brief Helper macro to calculate the PLLCLK frequency used on SAI domain + * @note ex: @ref __LL_RCC_CALC_PLLCLK_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), + * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ()); + * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI) + * @param __PLLM__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_1 + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @param __PLLN__ Between 8 and 86 + * @param __PLLP__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLP_DIV_7 + * @arg @ref LL_RCC_PLLP_DIV_17 + * @retval PLL clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \ + (((__PLLP__) == LL_RCC_PLLP_DIV_7) ? 7U : 17U)) + +#endif /* RCC_PLLP_DIV_2_31_SUPPORT */ +#endif /* RCC_PLLSAI1_SUPPORT */ + +/** + * @brief Helper macro to calculate the PLLCLK frequency used on 48M domain + * @note ex: @ref __LL_RCC_CALC_PLLCLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), + * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ()); + * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI) + * @param __PLLM__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_1 + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 (*) + * @arg @ref LL_RCC_PLLM_DIV_10 (*) + * @arg @ref LL_RCC_PLLM_DIV_11 (*) + * @arg @ref LL_RCC_PLLM_DIV_12 (*) + * @arg @ref LL_RCC_PLLM_DIV_13 (*) + * @arg @ref LL_RCC_PLLM_DIV_14 (*) + * @arg @ref LL_RCC_PLLM_DIV_15 (*) + * @arg @ref LL_RCC_PLLM_DIV_16 (*) + * + * (*) value not defined in all devices. + * @param __PLLN__ Between 8 and 86 or 127 depending on devices + * @param __PLLQ__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLQ_DIV_2 + * @arg @ref LL_RCC_PLLQ_DIV_4 + * @arg @ref LL_RCC_PLLQ_DIV_6 + * @arg @ref LL_RCC_PLLQ_DIV_8 + * @retval PLL clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \ + ((((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U)) + +#if defined(RCC_PLLSAI1_SUPPORT) +#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) && defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) +/** + * @brief Helper macro to calculate the PLLSAI1 frequency used for SAI domain + * @note ex: @ref __LL_RCC_CALC_PLLSAI1_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI1_GetDivider (), + * @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetP ()); + * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI) + * @param __PLLSAI1M__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI1M_DIV_1 + * @arg @ref LL_RCC_PLLSAI1M_DIV_2 + * @arg @ref LL_RCC_PLLSAI1M_DIV_3 + * @arg @ref LL_RCC_PLLSAI1M_DIV_4 + * @arg @ref LL_RCC_PLLSAI1M_DIV_5 + * @arg @ref LL_RCC_PLLSAI1M_DIV_6 + * @arg @ref LL_RCC_PLLSAI1M_DIV_7 + * @arg @ref LL_RCC_PLLSAI1M_DIV_8 + * @arg @ref LL_RCC_PLLSAI1M_DIV_9 + * @arg @ref LL_RCC_PLLSAI1M_DIV_10 + * @arg @ref LL_RCC_PLLSAI1M_DIV_11 + * @arg @ref LL_RCC_PLLSAI1M_DIV_12 + * @arg @ref LL_RCC_PLLSAI1M_DIV_13 + * @arg @ref LL_RCC_PLLSAI1M_DIV_14 + * @arg @ref LL_RCC_PLLSAI1M_DIV_15 + * @arg @ref LL_RCC_PLLSAI1M_DIV_16 + * @param __PLLSAI1N__ Between 8 and 86 or 127 depending on devices + * @param __PLLSAI1P__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI1P_DIV_2 + * @arg @ref LL_RCC_PLLSAI1P_DIV_3 + * @arg @ref LL_RCC_PLLSAI1P_DIV_4 + * @arg @ref LL_RCC_PLLSAI1P_DIV_5 + * @arg @ref LL_RCC_PLLSAI1P_DIV_6 + * @arg @ref LL_RCC_PLLSAI1P_DIV_7 + * @arg @ref LL_RCC_PLLSAI1P_DIV_8 + * @arg @ref LL_RCC_PLLSAI1P_DIV_9 + * @arg @ref LL_RCC_PLLSAI1P_DIV_10 + * @arg @ref LL_RCC_PLLSAI1P_DIV_11 + * @arg @ref LL_RCC_PLLSAI1P_DIV_12 + * @arg @ref LL_RCC_PLLSAI1P_DIV_13 + * @arg @ref LL_RCC_PLLSAI1P_DIV_14 + * @arg @ref LL_RCC_PLLSAI1P_DIV_15 + * @arg @ref LL_RCC_PLLSAI1P_DIV_16 + * @arg @ref LL_RCC_PLLSAI1P_DIV_17 + * @arg @ref LL_RCC_PLLSAI1P_DIV_18 + * @arg @ref LL_RCC_PLLSAI1P_DIV_19 + * @arg @ref LL_RCC_PLLSAI1P_DIV_20 + * @arg @ref LL_RCC_PLLSAI1P_DIV_21 + * @arg @ref LL_RCC_PLLSAI1P_DIV_22 + * @arg @ref LL_RCC_PLLSAI1P_DIV_23 + * @arg @ref LL_RCC_PLLSAI1P_DIV_24 + * @arg @ref LL_RCC_PLLSAI1P_DIV_25 + * @arg @ref LL_RCC_PLLSAI1P_DIV_26 + * @arg @ref LL_RCC_PLLSAI1P_DIV_27 + * @arg @ref LL_RCC_PLLSAI1P_DIV_28 + * @arg @ref LL_RCC_PLLSAI1P_DIV_29 + * @arg @ref LL_RCC_PLLSAI1P_DIV_30 + * @arg @ref LL_RCC_PLLSAI1P_DIV_31 + * @retval PLLSAI1 clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLSAI1_SAI_FREQ(__INPUTFREQ__, __PLLSAI1M__, __PLLSAI1N__, __PLLSAI1P__) \ + ((__INPUTFREQ__) / ((((__PLLSAI1M__) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)) * (__PLLSAI1N__) / \ + ((__PLLSAI1P__) >> RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos)) + +#elif defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) +/** + * @brief Helper macro to calculate the PLLSAI1 frequency used for SAI domain + * @note ex: @ref __LL_RCC_CALC_PLLSAI1_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), + * @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetP ()); + * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI) + * @param __PLLM__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_1 + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @param __PLLSAI1N__ Between 8 and 86 or 127 depending on devices + * @param __PLLSAI1P__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI1P_DIV_2 + * @arg @ref LL_RCC_PLLSAI1P_DIV_3 + * @arg @ref LL_RCC_PLLSAI1P_DIV_4 + * @arg @ref LL_RCC_PLLSAI1P_DIV_5 + * @arg @ref LL_RCC_PLLSAI1P_DIV_6 + * @arg @ref LL_RCC_PLLSAI1P_DIV_7 + * @arg @ref LL_RCC_PLLSAI1P_DIV_8 + * @arg @ref LL_RCC_PLLSAI1P_DIV_9 + * @arg @ref LL_RCC_PLLSAI1P_DIV_10 + * @arg @ref LL_RCC_PLLSAI1P_DIV_11 + * @arg @ref LL_RCC_PLLSAI1P_DIV_12 + * @arg @ref LL_RCC_PLLSAI1P_DIV_13 + * @arg @ref LL_RCC_PLLSAI1P_DIV_14 + * @arg @ref LL_RCC_PLLSAI1P_DIV_15 + * @arg @ref LL_RCC_PLLSAI1P_DIV_16 + * @arg @ref LL_RCC_PLLSAI1P_DIV_17 + * @arg @ref LL_RCC_PLLSAI1P_DIV_18 + * @arg @ref LL_RCC_PLLSAI1P_DIV_19 + * @arg @ref LL_RCC_PLLSAI1P_DIV_20 + * @arg @ref LL_RCC_PLLSAI1P_DIV_21 + * @arg @ref LL_RCC_PLLSAI1P_DIV_22 + * @arg @ref LL_RCC_PLLSAI1P_DIV_23 + * @arg @ref LL_RCC_PLLSAI1P_DIV_24 + * @arg @ref LL_RCC_PLLSAI1P_DIV_25 + * @arg @ref LL_RCC_PLLSAI1P_DIV_26 + * @arg @ref LL_RCC_PLLSAI1P_DIV_27 + * @arg @ref LL_RCC_PLLSAI1P_DIV_28 + * @arg @ref LL_RCC_PLLSAI1P_DIV_29 + * @arg @ref LL_RCC_PLLSAI1P_DIV_30 + * @arg @ref LL_RCC_PLLSAI1P_DIV_31 + * @retval PLLSAI1 clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLSAI1_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1P__) \ + ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI1N__) / \ + ((__PLLSAI1P__) >> RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos)) + +#else +/** + * @brief Helper macro to calculate the PLLSAI1 frequency used for SAI domain + * @note ex: @ref __LL_RCC_CALC_PLLSAI1_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), + * @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetP ()); + * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI) + * @param __PLLM__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_1 + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @param __PLLSAI1N__ Between 8 and 86 + * @param __PLLSAI1P__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI1P_DIV_7 + * @arg @ref LL_RCC_PLLSAI1P_DIV_17 + * @retval PLLSAI1 clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLSAI1_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1P__) \ + ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI1N__) / \ + (((__PLLSAI1P__) == LL_RCC_PLLSAI1P_DIV_7) ? 7U : 17U)) + +#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ + +#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) +/** + * @brief Helper macro to calculate the PLLSAI1 frequency used on 48M domain + * @note ex: @ref __LL_RCC_CALC_PLLSAI1_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI1_GetDivider (), + * @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetQ ()); + * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI) + * @param __PLLSAI1M__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI1M_DIV_1 + * @arg @ref LL_RCC_PLLSAI1M_DIV_2 + * @arg @ref LL_RCC_PLLSAI1M_DIV_3 + * @arg @ref LL_RCC_PLLSAI1M_DIV_4 + * @arg @ref LL_RCC_PLLSAI1M_DIV_5 + * @arg @ref LL_RCC_PLLSAI1M_DIV_6 + * @arg @ref LL_RCC_PLLSAI1M_DIV_7 + * @arg @ref LL_RCC_PLLSAI1M_DIV_8 + * @arg @ref LL_RCC_PLLSAI1M_DIV_9 + * @arg @ref LL_RCC_PLLSAI1M_DIV_10 + * @arg @ref LL_RCC_PLLSAI1M_DIV_11 + * @arg @ref LL_RCC_PLLSAI1M_DIV_12 + * @arg @ref LL_RCC_PLLSAI1M_DIV_13 + * @arg @ref LL_RCC_PLLSAI1M_DIV_14 + * @arg @ref LL_RCC_PLLSAI1M_DIV_15 + * @arg @ref LL_RCC_PLLSAI1M_DIV_16 + * @param __PLLSAI1N__ Between 8 and 86 or 127 depending on devices + * @param __PLLSAI1Q__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI1Q_DIV_2 + * @arg @ref LL_RCC_PLLSAI1Q_DIV_4 + * @arg @ref LL_RCC_PLLSAI1Q_DIV_6 + * @arg @ref LL_RCC_PLLSAI1Q_DIV_8 + * @retval PLLSAI1 clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLSAI1_48M_FREQ(__INPUTFREQ__, __PLLSAI1M__, __PLLSAI1N__, __PLLSAI1Q__) \ + ((__INPUTFREQ__) / ((((__PLLSAI1M__) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)) * (__PLLSAI1N__) / \ + ((((__PLLSAI1Q__) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) + 1U) << 1U)) + +#else +/** + * @brief Helper macro to calculate the PLLSAI1 frequency used on 48M domain + * @note ex: @ref __LL_RCC_CALC_PLLSAI1_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), + * @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetQ ()); + * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI) + * @param __PLLM__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_1 + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @param __PLLSAI1N__ Between 8 and 86 + * @param __PLLSAI1Q__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI1Q_DIV_2 + * @arg @ref LL_RCC_PLLSAI1Q_DIV_4 + * @arg @ref LL_RCC_PLLSAI1Q_DIV_6 + * @arg @ref LL_RCC_PLLSAI1Q_DIV_8 + * @retval PLLSAI1 clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLSAI1_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1Q__) \ + ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI1N__) / \ + ((((__PLLSAI1Q__) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) + 1U) << 1U)) + +#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ + +#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) +/** + * @brief Helper macro to calculate the PLLSAI1 frequency used on ADC domain + * @note ex: @ref __LL_RCC_CALC_PLLSAI1_ADC_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI1_GetDivider (), + * @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetR ()); + * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI) + * @param __PLLSAI1M__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI1M_DIV_1 + * @arg @ref LL_RCC_PLLSAI1M_DIV_2 + * @arg @ref LL_RCC_PLLSAI1M_DIV_3 + * @arg @ref LL_RCC_PLLSAI1M_DIV_4 + * @arg @ref LL_RCC_PLLSAI1M_DIV_5 + * @arg @ref LL_RCC_PLLSAI1M_DIV_6 + * @arg @ref LL_RCC_PLLSAI1M_DIV_7 + * @arg @ref LL_RCC_PLLSAI1M_DIV_8 + * @arg @ref LL_RCC_PLLSAI1M_DIV_9 + * @arg @ref LL_RCC_PLLSAI1M_DIV_10 + * @arg @ref LL_RCC_PLLSAI1M_DIV_11 + * @arg @ref LL_RCC_PLLSAI1M_DIV_12 + * @arg @ref LL_RCC_PLLSAI1M_DIV_13 + * @arg @ref LL_RCC_PLLSAI1M_DIV_14 + * @arg @ref LL_RCC_PLLSAI1M_DIV_15 + * @arg @ref LL_RCC_PLLSAI1M_DIV_16 + * @param __PLLSAI1N__ Between 8 and 86 or 127 depending on devices + * @param __PLLSAI1R__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI1R_DIV_2 + * @arg @ref LL_RCC_PLLSAI1R_DIV_4 + * @arg @ref LL_RCC_PLLSAI1R_DIV_6 + * @arg @ref LL_RCC_PLLSAI1R_DIV_8 + * @retval PLLSAI1 clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLSAI1_ADC_FREQ(__INPUTFREQ__, __PLLSAI1M__, __PLLSAI1N__, __PLLSAI1R__) \ + ((__INPUTFREQ__) / ((((__PLLSAI1M__) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)) * (__PLLSAI1N__) / \ + ((((__PLLSAI1R__) >> RCC_PLLSAI1CFGR_PLLSAI1R_Pos) + 1U) << 1U)) + +#else +/** + * @brief Helper macro to calculate the PLLSAI1 frequency used on ADC domain + * @note ex: @ref __LL_RCC_CALC_PLLSAI1_ADC_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), + * @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetR ()); + * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI) + * @param __PLLM__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_1 + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @param __PLLSAI1N__ Between 8 and 86 + * @param __PLLSAI1R__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI1R_DIV_2 + * @arg @ref LL_RCC_PLLSAI1R_DIV_4 + * @arg @ref LL_RCC_PLLSAI1R_DIV_6 + * @arg @ref LL_RCC_PLLSAI1R_DIV_8 + * @retval PLLSAI1 clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLSAI1_ADC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1R__) \ + ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI1N__) / \ + ((((__PLLSAI1R__) >> RCC_PLLSAI1CFGR_PLLSAI1R_Pos) + 1U) << 1U)) + +#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ +#endif /* RCC_PLLSAI1_SUPPORT */ + +#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) && defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) +/** + * @brief Helper macro to calculate the PLLSAI2 frequency used for SAI domain + * @note ex: @ref __LL_RCC_CALC_PLLSAI2_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI2_GetDivider (), + * @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetP ()); + * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI) + * @param __PLLSAI2M__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI2M_DIV_1 + * @arg @ref LL_RCC_PLLSAI2M_DIV_2 + * @arg @ref LL_RCC_PLLSAI2M_DIV_3 + * @arg @ref LL_RCC_PLLSAI2M_DIV_4 + * @arg @ref LL_RCC_PLLSAI2M_DIV_5 + * @arg @ref LL_RCC_PLLSAI2M_DIV_6 + * @arg @ref LL_RCC_PLLSAI2M_DIV_7 + * @arg @ref LL_RCC_PLLSAI2M_DIV_8 + * @arg @ref LL_RCC_PLLSAI2M_DIV_9 + * @arg @ref LL_RCC_PLLSAI2M_DIV_10 + * @arg @ref LL_RCC_PLLSAI2M_DIV_11 + * @arg @ref LL_RCC_PLLSAI2M_DIV_12 + * @arg @ref LL_RCC_PLLSAI2M_DIV_13 + * @arg @ref LL_RCC_PLLSAI2M_DIV_14 + * @arg @ref LL_RCC_PLLSAI2M_DIV_15 + * @arg @ref LL_RCC_PLLSAI2M_DIV_16 + * @param __PLLSAI2N__ Between 8 and 86 or 127 depending on devices + * @param __PLLSAI2P__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI2P_DIV_2 + * @arg @ref LL_RCC_PLLSAI2P_DIV_3 + * @arg @ref LL_RCC_PLLSAI2P_DIV_4 + * @arg @ref LL_RCC_PLLSAI2P_DIV_5 + * @arg @ref LL_RCC_PLLSAI2P_DIV_6 + * @arg @ref LL_RCC_PLLSAI2P_DIV_7 + * @arg @ref LL_RCC_PLLSAI2P_DIV_8 + * @arg @ref LL_RCC_PLLSAI2P_DIV_9 + * @arg @ref LL_RCC_PLLSAI2P_DIV_10 + * @arg @ref LL_RCC_PLLSAI2P_DIV_11 + * @arg @ref LL_RCC_PLLSAI2P_DIV_12 + * @arg @ref LL_RCC_PLLSAI2P_DIV_13 + * @arg @ref LL_RCC_PLLSAI2P_DIV_14 + * @arg @ref LL_RCC_PLLSAI2P_DIV_15 + * @arg @ref LL_RCC_PLLSAI2P_DIV_16 + * @arg @ref LL_RCC_PLLSAI2P_DIV_17 + * @arg @ref LL_RCC_PLLSAI2P_DIV_18 + * @arg @ref LL_RCC_PLLSAI2P_DIV_19 + * @arg @ref LL_RCC_PLLSAI2P_DIV_20 + * @arg @ref LL_RCC_PLLSAI2P_DIV_21 + * @arg @ref LL_RCC_PLLSAI2P_DIV_22 + * @arg @ref LL_RCC_PLLSAI2P_DIV_23 + * @arg @ref LL_RCC_PLLSAI2P_DIV_24 + * @arg @ref LL_RCC_PLLSAI2P_DIV_25 + * @arg @ref LL_RCC_PLLSAI2P_DIV_26 + * @arg @ref LL_RCC_PLLSAI2P_DIV_27 + * @arg @ref LL_RCC_PLLSAI2P_DIV_28 + * @arg @ref LL_RCC_PLLSAI2P_DIV_29 + * @arg @ref LL_RCC_PLLSAI2P_DIV_30 + * @arg @ref LL_RCC_PLLSAI2P_DIV_31 + * @retval PLLSAI2 clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLSAI2_SAI_FREQ(__INPUTFREQ__, __PLLSAI2M__, __PLLSAI2N__, __PLLSAI2P__) \ + ((__INPUTFREQ__) / ((((__PLLSAI2M__) >> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U)) * (__PLLSAI2N__) / \ + ((__PLLSAI2P__) >> RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos)) + +#elif defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) +/** + * @brief Helper macro to calculate the PLLSAI2 frequency used for SAI domain + * @note ex: @ref __LL_RCC_CALC_PLLSAI2_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), + * @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetP ()); + * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI) + * @param __PLLM__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_1 + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @param __PLLSAI2N__ Between 8 and 86 or 127 depending on devices + * @param __PLLSAI2P__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI2P_DIV_2 + * @arg @ref LL_RCC_PLLSAI2P_DIV_3 + * @arg @ref LL_RCC_PLLSAI2P_DIV_4 + * @arg @ref LL_RCC_PLLSAI2P_DIV_5 + * @arg @ref LL_RCC_PLLSAI2P_DIV_6 + * @arg @ref LL_RCC_PLLSAI2P_DIV_7 + * @arg @ref LL_RCC_PLLSAI2P_DIV_8 + * @arg @ref LL_RCC_PLLSAI2P_DIV_9 + * @arg @ref LL_RCC_PLLSAI2P_DIV_10 + * @arg @ref LL_RCC_PLLSAI2P_DIV_11 + * @arg @ref LL_RCC_PLLSAI2P_DIV_12 + * @arg @ref LL_RCC_PLLSAI2P_DIV_13 + * @arg @ref LL_RCC_PLLSAI2P_DIV_14 + * @arg @ref LL_RCC_PLLSAI2P_DIV_15 + * @arg @ref LL_RCC_PLLSAI2P_DIV_16 + * @arg @ref LL_RCC_PLLSAI2P_DIV_17 + * @arg @ref LL_RCC_PLLSAI2P_DIV_18 + * @arg @ref LL_RCC_PLLSAI2P_DIV_19 + * @arg @ref LL_RCC_PLLSAI2P_DIV_20 + * @arg @ref LL_RCC_PLLSAI2P_DIV_21 + * @arg @ref LL_RCC_PLLSAI2P_DIV_22 + * @arg @ref LL_RCC_PLLSAI2P_DIV_23 + * @arg @ref LL_RCC_PLLSAI2P_DIV_24 + * @arg @ref LL_RCC_PLLSAI2P_DIV_25 + * @arg @ref LL_RCC_PLLSAI2P_DIV_26 + * @arg @ref LL_RCC_PLLSAI2P_DIV_27 + * @arg @ref LL_RCC_PLLSAI2P_DIV_28 + * @arg @ref LL_RCC_PLLSAI2P_DIV_29 + * @arg @ref LL_RCC_PLLSAI2P_DIV_30 + * @arg @ref LL_RCC_PLLSAI2P_DIV_31 + * @retval PLLSAI2 clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLSAI2_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI2N__, __PLLSAI2P__) \ + ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI2N__) / \ + ((__PLLSAI2P__) >> RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos)) + +#else +/** + * @brief Helper macro to calculate the PLLSAI2 frequency used for SAI domain + * @note ex: @ref __LL_RCC_CALC_PLLSAI2_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), + * @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetP ()); + * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI) + * @param __PLLM__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_1 + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @param __PLLSAI2N__ Between 8 and 86 + * @param __PLLSAI2P__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI2P_DIV_7 + * @arg @ref LL_RCC_PLLSAI2P_DIV_17 + * @retval PLLSAI2 clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLSAI2_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI2N__, __PLLSAI2P__) \ + ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1)) * (__PLLSAI2N__) / \ + (((__PLLSAI2P__) == LL_RCC_PLLSAI2P_DIV_7) ? 7U : 17U)) + +#endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */ + +#if defined(LTDC) +/** + * @brief Helper macro to calculate the PLLSAI2 frequency used for LTDC domain + * @note ex: @ref __LL_RCC_CALC_PLLSAI2_LTDC_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI2_GetDivider (), + * @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetR (), @ref LL_RCC_PLLSAI2_GetDIVR ()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI/MSI) + * @param __PLLSAI2M__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI2M_DIV_1 + * @arg @ref LL_RCC_PLLSAI2M_DIV_2 + * @arg @ref LL_RCC_PLLSAI2M_DIV_3 + * @arg @ref LL_RCC_PLLSAI2M_DIV_4 + * @arg @ref LL_RCC_PLLSAI2M_DIV_5 + * @arg @ref LL_RCC_PLLSAI2M_DIV_6 + * @arg @ref LL_RCC_PLLSAI2M_DIV_7 + * @arg @ref LL_RCC_PLLSAI2M_DIV_8 + * @arg @ref LL_RCC_PLLSAI2M_DIV_9 + * @arg @ref LL_RCC_PLLSAI2M_DIV_10 + * @arg @ref LL_RCC_PLLSAI2M_DIV_11 + * @arg @ref LL_RCC_PLLSAI2M_DIV_12 + * @arg @ref LL_RCC_PLLSAI2M_DIV_13 + * @arg @ref LL_RCC_PLLSAI2M_DIV_14 + * @arg @ref LL_RCC_PLLSAI2M_DIV_15 + * @arg @ref LL_RCC_PLLSAI2M_DIV_16 + * @param __PLLSAI2N__ Between 8 and 127 + * @param __PLLSAI2R__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI2R_DIV_2 + * @arg @ref LL_RCC_PLLSAI2R_DIV_4 + * @arg @ref LL_RCC_PLLSAI2R_DIV_6 + * @arg @ref LL_RCC_PLLSAI2R_DIV_8 + * @param __PLLSAI2DIVR__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_2 + * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_4 + * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_8 + * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_16 + * @retval PLLSAI2 clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLSAI2_LTDC_FREQ(__INPUTFREQ__, __PLLSAI2M__, __PLLSAI2N__, __PLLSAI2R__, __PLLSAI2DIVR__) \ + (((__INPUTFREQ__) / (((__PLLSAI2M__)>> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U)) * (__PLLSAI2N__) / \ + (((((__PLLSAI2R__) >> RCC_PLLSAI2CFGR_PLLSAI2R_Pos ) + 1U) << 1U) * (2UL << ((__PLLSAI2DIVR__) >> RCC_CCIPR2_PLLSAI2DIVR_Pos)))) +#elif defined(RCC_PLLSAI2_SUPPORT) +/** + * @brief Helper macro to calculate the PLLSAI2 frequency used on ADC domain + * @note ex: @ref __LL_RCC_CALC_PLLSAI2_ADC_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), + * @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetR ()); + * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI) + * @param __PLLM__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_1 + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @param __PLLSAI2N__ Between 8 and 86 + * @param __PLLSAI2R__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI2R_DIV_2 + * @arg @ref LL_RCC_PLLSAI2R_DIV_4 + * @arg @ref LL_RCC_PLLSAI2R_DIV_6 + * @arg @ref LL_RCC_PLLSAI2R_DIV_8 + * @retval PLLSAI2 clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLSAI2_ADC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI2N__, __PLLSAI2R__) \ + ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI2N__) / \ + ((((__PLLSAI2R__) >> RCC_PLLSAI2CFGR_PLLSAI2R_Pos ) + 1U) << 1U)) + +#endif /* LTDC */ + +#if defined(DSI) +/** + * @brief Helper macro to calculate the PLLDSICLK frequency used on DSI + * @note ex: @ref __LL_RCC_CALC_PLLSAI2_DSI_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI2_GetDivider (), + * @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetQ ()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI/MSI) + * @param __PLLSAI2M__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI2M_DIV_1 + * @arg @ref LL_RCC_PLLSAI2M_DIV_2 + * @arg @ref LL_RCC_PLLSAI2M_DIV_3 + * @arg @ref LL_RCC_PLLSAI2M_DIV_4 + * @arg @ref LL_RCC_PLLSAI2M_DIV_5 + * @arg @ref LL_RCC_PLLSAI2M_DIV_6 + * @arg @ref LL_RCC_PLLSAI2M_DIV_7 + * @arg @ref LL_RCC_PLLSAI2M_DIV_8 + * @arg @ref LL_RCC_PLLSAI2M_DIV_9 + * @arg @ref LL_RCC_PLLSAI2M_DIV_10 + * @arg @ref LL_RCC_PLLSAI2M_DIV_11 + * @arg @ref LL_RCC_PLLSAI2M_DIV_12 + * @arg @ref LL_RCC_PLLSAI2M_DIV_13 + * @arg @ref LL_RCC_PLLSAI2M_DIV_14 + * @arg @ref LL_RCC_PLLSAI2M_DIV_15 + * @arg @ref LL_RCC_PLLSAI2M_DIV_16 + * @param __PLLSAI2N__ Between 8 and 127 + * @param __PLLSAI2Q__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI2Q_DIV_2 + * @arg @ref LL_RCC_PLLSAI2Q_DIV_4 + * @arg @ref LL_RCC_PLLSAI2Q_DIV_6 + * @arg @ref LL_RCC_PLLSAI2Q_DIV_8 + * @retval PLL clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLSAI2_DSI_FREQ(__INPUTFREQ__, __PLLSAI2M__, __PLLSAI2N__, __PLLSAI2Q__) \ + ((__INPUTFREQ__) / ((((__PLLSAI2M__) >> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U)) * (__PLLSAI2N__) / \ + ((((__PLLSAI2Q__) >> RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) + 1U) << 1U)) +#endif /* DSI */ + + + +/** + * @brief Helper macro to calculate the HCLK frequency + * @param __SYSCLKFREQ__ SYSCLK frequency (based on MSI/HSE/HSI/PLLCLK) + * @param __AHBPRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_SYSCLK_DIV_1 + * @arg @ref LL_RCC_SYSCLK_DIV_2 + * @arg @ref LL_RCC_SYSCLK_DIV_4 + * @arg @ref LL_RCC_SYSCLK_DIV_8 + * @arg @ref LL_RCC_SYSCLK_DIV_16 + * @arg @ref LL_RCC_SYSCLK_DIV_64 + * @arg @ref LL_RCC_SYSCLK_DIV_128 + * @arg @ref LL_RCC_SYSCLK_DIV_256 + * @arg @ref LL_RCC_SYSCLK_DIV_512 + * @retval HCLK clock frequency (in Hz) + */ +#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]) + +/** + * @brief Helper macro to calculate the PCLK1 frequency (ABP1) + * @param __HCLKFREQ__ HCLK frequency + * @param __APB1PRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_APB1_DIV_1 + * @arg @ref LL_RCC_APB1_DIV_2 + * @arg @ref LL_RCC_APB1_DIV_4 + * @arg @ref LL_RCC_APB1_DIV_8 + * @arg @ref LL_RCC_APB1_DIV_16 + * @retval PCLK1 clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos]) + +/** + * @brief Helper macro to calculate the PCLK2 frequency (ABP2) + * @param __HCLKFREQ__ HCLK frequency + * @param __APB2PRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_APB2_DIV_1 + * @arg @ref LL_RCC_APB2_DIV_2 + * @arg @ref LL_RCC_APB2_DIV_4 + * @arg @ref LL_RCC_APB2_DIV_8 + * @arg @ref LL_RCC_APB2_DIV_16 + * @retval PCLK2 clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos]) + +/** + * @brief Helper macro to calculate the MSI frequency (in Hz) + * @note __MSISEL__ can be retrieved thanks to function LL_RCC_MSI_IsEnabledRangeSelect() + * @note if __MSISEL__ is equal to LL_RCC_MSIRANGESEL_STANDBY, + * __MSIRANGE__can be retrieved by LL_RCC_MSI_GetRangeAfterStandby() + * else by LL_RCC_MSI_GetRange() + * ex: __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), + * (LL_RCC_MSI_IsEnabledRangeSelect()? + * LL_RCC_MSI_GetRange(): + * LL_RCC_MSI_GetRangeAfterStandby())) + * @param __MSISEL__ This parameter can be one of the following values: + * @arg @ref LL_RCC_MSIRANGESEL_STANDBY + * @arg @ref LL_RCC_MSIRANGESEL_RUN + * @param __MSIRANGE__ This parameter can be one of the following values: + * @arg @ref LL_RCC_MSIRANGE_0 + * @arg @ref LL_RCC_MSIRANGE_1 + * @arg @ref LL_RCC_MSIRANGE_2 + * @arg @ref LL_RCC_MSIRANGE_3 + * @arg @ref LL_RCC_MSIRANGE_4 + * @arg @ref LL_RCC_MSIRANGE_5 + * @arg @ref LL_RCC_MSIRANGE_6 + * @arg @ref LL_RCC_MSIRANGE_7 + * @arg @ref LL_RCC_MSIRANGE_8 + * @arg @ref LL_RCC_MSIRANGE_9 + * @arg @ref LL_RCC_MSIRANGE_10 + * @arg @ref LL_RCC_MSIRANGE_11 + * @arg @ref LL_RCC_MSISRANGE_4 + * @arg @ref LL_RCC_MSISRANGE_5 + * @arg @ref LL_RCC_MSISRANGE_6 + * @arg @ref LL_RCC_MSISRANGE_7 + * @retval MSI clock frequency (in Hz) + */ +#define __LL_RCC_CALC_MSI_FREQ(__MSISEL__, __MSIRANGE__) (((__MSISEL__) == LL_RCC_MSIRANGESEL_STANDBY) ? \ + (MSIRangeTable[(__MSIRANGE__) >> 8U]) : \ + (MSIRangeTable[(__MSIRANGE__) >> 4U])) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions + * @{ + */ + +/** @defgroup RCC_LL_EF_HSE HSE + * @{ + */ + +/** + * @brief Enable the Clock Security System. + * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void) +{ + SET_BIT(RCC->CR, RCC_CR_CSSON); +} + +/** + * @brief Enable HSE external oscillator (HSE Bypass) + * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSEBYP); +} + +/** + * @brief Disable HSE external oscillator (HSE Bypass) + * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); +} + +/** + * @brief Enable HSE crystal oscillator (HSE ON) + * @rmtoll CR HSEON LL_RCC_HSE_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSEON); +} + +/** + * @brief Disable HSE crystal oscillator (HSE ON) + * @rmtoll CR HSEON LL_RCC_HSE_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); +} + +/** + * @brief Check if HSE oscillator Ready + * @rmtoll CR HSERDY LL_RCC_HSE_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == RCC_CR_HSERDY) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_HSI HSI + * @{ + */ + +/** + * @brief Enable HSI even in stop mode + * @note HSI oscillator is forced ON even in Stop mode + * @rmtoll CR HSIKERON LL_RCC_HSI_EnableInStopMode + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_EnableInStopMode(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSIKERON); +} + +/** + * @brief Disable HSI in stop mode + * @rmtoll CR HSIKERON LL_RCC_HSI_DisableInStopMode + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_DisableInStopMode(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON); +} + +/** + * @brief Check if HSI is enabled in stop mode + * @rmtoll CR HSIKERON LL_RCC_HSI_IsEnabledInStopMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_IsEnabledInStopMode(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_HSIKERON) == RCC_CR_HSIKERON) ? 1UL : 0UL); +} + +/** + * @brief Enable HSI oscillator + * @rmtoll CR HSION LL_RCC_HSI_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSION); +} + +/** + * @brief Disable HSI oscillator + * @rmtoll CR HSION LL_RCC_HSI_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSION); +} + +/** + * @brief Check if HSI clock is ready + * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RCC_CR_HSIRDY) ? 1UL : 0UL); +} + +/** + * @brief Enable HSI Automatic from stop mode + * @rmtoll CR HSIASFS LL_RCC_HSI_EnableAutoFromStop + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_EnableAutoFromStop(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSIASFS); +} + +/** + * @brief Disable HSI Automatic from stop mode + * @rmtoll CR HSIASFS LL_RCC_HSI_DisableAutoFromStop + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_DisableAutoFromStop(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSIASFS); +} +/** + * @brief Get HSI Calibration value + * @note When HSITRIM is written, HSICAL is updated with the sum of + * HSITRIM and the factory trim value + * @rmtoll ICSCR HSICAL LL_RCC_HSI_GetCalibration + * @retval Between Min_Data = 0x00 and Max_Data = 0xFF + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void) +{ + return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSICAL) >> RCC_ICSCR_HSICAL_Pos); +} + +/** + * @brief Set HSI Calibration trimming + * @note user-programmable trimming value that is added to the HSICAL + * @note Default value is 16 on STM32L43x/STM32L44x/STM32L47x/STM32L48x or 64 on other devices, + * which, when added to the HSICAL value, should trim the HSI to 16 MHz +/- 1 % + * @rmtoll ICSCR HSITRIM LL_RCC_HSI_SetCalibTrimming + * @param Value Between Min_Data = 0 and Max_Data = 31 on STM32L43x/STM32L44x/STM32L47x/STM32L48x or + * between Min_Data = 0 and Max_Data = 127 on other devices + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value) +{ + MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, Value << RCC_ICSCR_HSITRIM_Pos); +} + +/** + * @brief Get HSI Calibration trimming + * @rmtoll ICSCR HSITRIM LL_RCC_HSI_GetCalibTrimming + * @retval Between Min_Data = 0 and Max_Data = 31 on STM32L43x/STM32L44x/STM32L47x/STM32L48x or + * between Min_Data = 0 and Max_Data = 127 on other devices + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void) +{ + return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos); +} + +/** + * @} + */ + +#if defined(RCC_HSI48_SUPPORT) +/** @defgroup RCC_LL_EF_HSI48 HSI48 + * @{ + */ + +/** + * @brief Enable HSI48 + * @rmtoll CRRCR HSI48ON LL_RCC_HSI48_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI48_Enable(void) +{ + SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON); +} + +/** + * @brief Disable HSI48 + * @rmtoll CRRCR HSI48ON LL_RCC_HSI48_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI48_Disable(void) +{ + CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON); +} + +/** + * @brief Check if HSI48 oscillator Ready + * @rmtoll CRRCR HSI48RDY LL_RCC_HSI48_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void) +{ + return ((READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == RCC_CRRCR_HSI48RDY) ? 1UL : 0UL); +} + +/** + * @brief Get HSI48 Calibration value + * @rmtoll CRRCR HSI48CAL LL_RCC_HSI48_GetCalibration + * @retval Between Min_Data = 0x00 and Max_Data = 0x1FF + */ +__STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void) +{ + return (uint32_t)(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48CAL) >> RCC_CRRCR_HSI48CAL_Pos); +} + +/** + * @} + */ +#endif /* RCC_HSI48_SUPPORT */ + +/** @defgroup RCC_LL_EF_LSE LSE + * @{ + */ + +/** + * @brief Enable Low Speed External (LSE) crystal. + * @rmtoll BDCR LSEON LL_RCC_LSE_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_Enable(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); +} + +/** + * @brief Disable Low Speed External (LSE) crystal. + * @rmtoll BDCR LSEON LL_RCC_LSE_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_Disable(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); +} + +/** + * @brief Enable external clock source (LSE bypass). + * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); +} + +/** + * @brief Disable external clock source (LSE bypass). + * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); +} + +/** + * @brief Set LSE oscillator drive capability + * @note The oscillator is in Xtal mode when it is not in bypass mode. + * @rmtoll BDCR LSEDRV LL_RCC_LSE_SetDriveCapability + * @param LSEDrive This parameter can be one of the following values: + * @arg @ref LL_RCC_LSEDRIVE_LOW + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH + * @arg @ref LL_RCC_LSEDRIVE_HIGH + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive) +{ + MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive); +} + +/** + * @brief Get LSE oscillator drive capability + * @rmtoll BDCR LSEDRV LL_RCC_LSE_GetDriveCapability + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_LSEDRIVE_LOW + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH + * @arg @ref LL_RCC_LSEDRIVE_HIGH + */ +__STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void) +{ + return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV)); +} + +/** + * @brief Enable Clock security system on LSE. + * @rmtoll BDCR LSECSSON LL_RCC_LSE_EnableCSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_EnableCSS(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON); +} + +/** + * @brief Disable Clock security system on LSE. + * @note Clock security system can be disabled only after a LSE + * failure detection. In that case it MUST be disabled by software. + * @rmtoll BDCR LSECSSON LL_RCC_LSE_DisableCSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_DisableCSS(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON); +} + +/** + * @brief Check if LSE oscillator Ready + * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void) +{ + return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == RCC_BDCR_LSERDY) ? 1UL : 0UL); +} + +/** + * @brief Check if CSS on LSE failure Detection + * @rmtoll BDCR LSECSSD LL_RCC_LSE_IsCSSDetected + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected(void) +{ + return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) == RCC_BDCR_LSECSSD) ? 1UL : 0UL); +} + +#if defined(RCC_BDCR_LSESYSDIS) +/** + * @brief Disable LSE oscillator propagation + * @note LSE clock is not propagated to any peripheral except to RTC which remains clocked + * @note A 2 LSE-clock delay is needed for LSESYSDIS setting to be taken into account + * @rmtoll BDCR LSESYSDIS LL_RCC_LSE_DisablePropagation + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_DisablePropagation(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSESYSDIS); +} + +/** + * @brief Enable LSE oscillator propagation + * @note A 2 LSE-clock delay is needed for LSESYSDIS resetting to be taken into account + * @rmtoll BDCR LSESYSDIS LL_RCC_LSE_EnablePropagation + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_EnablePropagation(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSESYSDIS); +} + +/** + * @brief Check if LSE oscillator propagation is enabled + * @rmtoll BDCR LSESYSDIS LL_RCC_LSE_IsPropagationEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSE_IsPropagationEnabled(void) +{ + return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSDIS) == 0U) ? 1UL : 0UL); +} +#endif /* RCC_BDCR_LSESYSDIS */ +/** + * @} + */ + +/** @defgroup RCC_LL_EF_LSI LSI + * @{ + */ + +/** + * @brief Enable LSI Oscillator + * @rmtoll CSR LSION LL_RCC_LSI_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSI_Enable(void) +{ + SET_BIT(RCC->CSR, RCC_CSR_LSION); +} + +/** + * @brief Disable LSI Oscillator + * @rmtoll CSR LSION LL_RCC_LSI_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSI_Disable(void) +{ + CLEAR_BIT(RCC->CSR, RCC_CSR_LSION); +} + +/** + * @brief Check if LSI is Ready + * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == RCC_CSR_LSIRDY) ? 1UL : 0UL); +} + +#if defined(RCC_CSR_LSIPREDIV) +/** + * @brief Set LSI division factor + * @rmtoll CSR LSIPREDIV LL_RCC_LSI_SetPrediv + * @param LSI_PREDIV This parameter can be one of the following values: + * @arg @ref LL_RCC_LSI_PREDIV_1 + * @arg @ref LL_RCC_LSI_PREDIV_128 + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSI_SetPrediv(uint32_t LSI_PREDIV) +{ + MODIFY_REG(RCC->CSR, RCC_CSR_LSIPREDIV, LSI_PREDIV); +} + +/** + * @brief Get LSI division factor + * @rmtoll CSR LSIPREDIV LL_RCC_LSI_GetPrediv + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_LSI_PREDIV_1 + * @arg @ref LL_RCC_LSI_PREDIV_128 + */ +__STATIC_INLINE uint32_t LL_RCC_LSI_GetPrediv(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_LSIPREDIV)); +} +#endif /* RCC_CSR_LSIPREDIV */ + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_MSI MSI + * @{ + */ + +/** + * @brief Enable MSI oscillator + * @rmtoll CR MSION LL_RCC_MSI_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_MSI_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_MSION); +} + +/** + * @brief Disable MSI oscillator + * @rmtoll CR MSION LL_RCC_MSI_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_MSI_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_MSION); +} + +/** + * @brief Check if MSI oscillator Ready + * @rmtoll CR MSIRDY LL_RCC_MSI_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_MSI_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_MSIRDY) == RCC_CR_MSIRDY) ? 1UL : 0UL); +} + +/** + * @brief Enable MSI PLL-mode (Hardware auto calibration with LSE) + * @note MSIPLLEN must be enabled after LSE is enabled (LSEON enabled) + * and ready (LSERDY set by hardware) + * @note hardware protection to avoid enabling MSIPLLEN if LSE is not + * ready + * @rmtoll CR MSIPLLEN LL_RCC_MSI_EnablePLLMode + * @retval None + */ +__STATIC_INLINE void LL_RCC_MSI_EnablePLLMode(void) +{ + SET_BIT(RCC->CR, RCC_CR_MSIPLLEN); +} + +/** + * @brief Disable MSI-PLL mode + * @note cleared by hardware when LSE is disabled (LSEON = 0) or when + * the Clock Security System on LSE detects a LSE failure + * @rmtoll CR MSIPLLEN LL_RCC_MSI_DisablePLLMode + * @retval None + */ +__STATIC_INLINE void LL_RCC_MSI_DisablePLLMode(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_MSIPLLEN); +} + +/** + * @brief Enable MSI clock range selection with MSIRANGE register + * @note Write 0 has no effect. After a standby or a reset + * MSIRGSEL is at 0 and the MSI range value is provided by + * MSISRANGE + * @rmtoll CR MSIRGSEL LL_RCC_MSI_EnableRangeSelection + * @retval None + */ +__STATIC_INLINE void LL_RCC_MSI_EnableRangeSelection(void) +{ + SET_BIT(RCC->CR, RCC_CR_MSIRGSEL); +} + +/** + * @brief Check if MSI clock range is selected with MSIRANGE register + * @rmtoll CR MSIRGSEL LL_RCC_MSI_IsEnabledRangeSelect + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_MSI_IsEnabledRangeSelect(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == RCC_CR_MSIRGSEL) ? 1UL : 0UL); +} + +/** + * @brief Configure the Internal Multi Speed oscillator (MSI) clock range in run mode. + * @rmtoll CR MSIRANGE LL_RCC_MSI_SetRange + * @param Range This parameter can be one of the following values: + * @arg @ref LL_RCC_MSIRANGE_0 + * @arg @ref LL_RCC_MSIRANGE_1 + * @arg @ref LL_RCC_MSIRANGE_2 + * @arg @ref LL_RCC_MSIRANGE_3 + * @arg @ref LL_RCC_MSIRANGE_4 + * @arg @ref LL_RCC_MSIRANGE_5 + * @arg @ref LL_RCC_MSIRANGE_6 + * @arg @ref LL_RCC_MSIRANGE_7 + * @arg @ref LL_RCC_MSIRANGE_8 + * @arg @ref LL_RCC_MSIRANGE_9 + * @arg @ref LL_RCC_MSIRANGE_10 + * @arg @ref LL_RCC_MSIRANGE_11 + * @retval None + */ +__STATIC_INLINE void LL_RCC_MSI_SetRange(uint32_t Range) +{ + MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, Range); +} + +/** + * @brief Get the Internal Multi Speed oscillator (MSI) clock range in run mode. + * @rmtoll CR MSIRANGE LL_RCC_MSI_GetRange + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_MSIRANGE_0 + * @arg @ref LL_RCC_MSIRANGE_1 + * @arg @ref LL_RCC_MSIRANGE_2 + * @arg @ref LL_RCC_MSIRANGE_3 + * @arg @ref LL_RCC_MSIRANGE_4 + * @arg @ref LL_RCC_MSIRANGE_5 + * @arg @ref LL_RCC_MSIRANGE_6 + * @arg @ref LL_RCC_MSIRANGE_7 + * @arg @ref LL_RCC_MSIRANGE_8 + * @arg @ref LL_RCC_MSIRANGE_9 + * @arg @ref LL_RCC_MSIRANGE_10 + * @arg @ref LL_RCC_MSIRANGE_11 + */ +__STATIC_INLINE uint32_t LL_RCC_MSI_GetRange(void) +{ + return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_MSIRANGE)); +} + +/** + * @brief Configure MSI range used after standby + * @rmtoll CSR MSISRANGE LL_RCC_MSI_SetRangeAfterStandby + * @param Range This parameter can be one of the following values: + * @arg @ref LL_RCC_MSISRANGE_4 + * @arg @ref LL_RCC_MSISRANGE_5 + * @arg @ref LL_RCC_MSISRANGE_6 + * @arg @ref LL_RCC_MSISRANGE_7 + * @retval None + */ +__STATIC_INLINE void LL_RCC_MSI_SetRangeAfterStandby(uint32_t Range) +{ + MODIFY_REG(RCC->CSR, RCC_CSR_MSISRANGE, Range); +} + +/** + * @brief Get MSI range used after standby + * @rmtoll CSR MSISRANGE LL_RCC_MSI_GetRangeAfterStandby + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_MSISRANGE_4 + * @arg @ref LL_RCC_MSISRANGE_5 + * @arg @ref LL_RCC_MSISRANGE_6 + * @arg @ref LL_RCC_MSISRANGE_7 + */ +__STATIC_INLINE uint32_t LL_RCC_MSI_GetRangeAfterStandby(void) +{ + return (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE)); +} + +/** + * @brief Get MSI Calibration value + * @note When MSITRIM is written, MSICAL is updated with the sum of + * MSITRIM and the factory trim value + * @rmtoll ICSCR MSICAL LL_RCC_MSI_GetCalibration + * @retval Between Min_Data = 0 and Max_Data = 255 + */ +__STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibration(void) +{ + return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSICAL) >> RCC_ICSCR_MSICAL_Pos); +} + +/** + * @brief Set MSI Calibration trimming + * @note user-programmable trimming value that is added to the MSICAL + * @rmtoll ICSCR MSITRIM LL_RCC_MSI_SetCalibTrimming + * @param Value Between Min_Data = 0 and Max_Data = 255 + * @retval None + */ +__STATIC_INLINE void LL_RCC_MSI_SetCalibTrimming(uint32_t Value) +{ + MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, Value << RCC_ICSCR_MSITRIM_Pos); +} + +/** + * @brief Get MSI Calibration trimming + * @rmtoll ICSCR MSITRIM LL_RCC_MSI_GetCalibTrimming + * @retval Between 0 and 255 + */ +__STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibTrimming(void) +{ + return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSITRIM) >> RCC_ICSCR_MSITRIM_Pos); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_LSCO LSCO + * @{ + */ + +/** + * @brief Enable Low speed clock + * @rmtoll BDCR LSCOEN LL_RCC_LSCO_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSCO_Enable(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSCOEN); +} + +/** + * @brief Disable Low speed clock + * @rmtoll BDCR LSCOEN LL_RCC_LSCO_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSCO_Disable(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN); +} + +/** + * @brief Configure Low speed clock selection + * @rmtoll BDCR LSCOSEL LL_RCC_LSCO_SetSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI + * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSCO_SetSource(uint32_t Source) +{ + MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL, Source); +} + +/** + * @brief Get Low speed clock selection + * @rmtoll BDCR LSCOSEL LL_RCC_LSCO_GetSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI + * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE + */ +__STATIC_INLINE uint32_t LL_RCC_LSCO_GetSource(void) +{ + return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSCOSEL)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_System System + * @{ + */ + +/** + * @brief Configure the system clock source + * @rmtoll CFGR SW LL_RCC_SetSysClkSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_SYS_CLKSOURCE_MSI + * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI + * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE + * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source); +} + +/** + * @brief Get the system clock source + * @rmtoll CFGR SWS LL_RCC_GetSysClkSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_MSI + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL + */ +__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)); +} + +/** + * @brief Set AHB prescaler + * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_SYSCLK_DIV_1 + * @arg @ref LL_RCC_SYSCLK_DIV_2 + * @arg @ref LL_RCC_SYSCLK_DIV_4 + * @arg @ref LL_RCC_SYSCLK_DIV_8 + * @arg @ref LL_RCC_SYSCLK_DIV_16 + * @arg @ref LL_RCC_SYSCLK_DIV_64 + * @arg @ref LL_RCC_SYSCLK_DIV_128 + * @arg @ref LL_RCC_SYSCLK_DIV_256 + * @arg @ref LL_RCC_SYSCLK_DIV_512 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler); +} + +/** + * @brief Set APB1 prescaler + * @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_APB1_DIV_1 + * @arg @ref LL_RCC_APB1_DIV_2 + * @arg @ref LL_RCC_APB1_DIV_4 + * @arg @ref LL_RCC_APB1_DIV_8 + * @arg @ref LL_RCC_APB1_DIV_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler); +} + +/** + * @brief Set APB2 prescaler + * @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_APB2_DIV_1 + * @arg @ref LL_RCC_APB2_DIV_2 + * @arg @ref LL_RCC_APB2_DIV_4 + * @arg @ref LL_RCC_APB2_DIV_8 + * @arg @ref LL_RCC_APB2_DIV_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler); +} + +/** + * @brief Get AHB prescaler + * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SYSCLK_DIV_1 + * @arg @ref LL_RCC_SYSCLK_DIV_2 + * @arg @ref LL_RCC_SYSCLK_DIV_4 + * @arg @ref LL_RCC_SYSCLK_DIV_8 + * @arg @ref LL_RCC_SYSCLK_DIV_16 + * @arg @ref LL_RCC_SYSCLK_DIV_64 + * @arg @ref LL_RCC_SYSCLK_DIV_128 + * @arg @ref LL_RCC_SYSCLK_DIV_256 + * @arg @ref LL_RCC_SYSCLK_DIV_512 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE)); +} + +/** + * @brief Get APB1 prescaler + * @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_APB1_DIV_1 + * @arg @ref LL_RCC_APB1_DIV_2 + * @arg @ref LL_RCC_APB1_DIV_4 + * @arg @ref LL_RCC_APB1_DIV_8 + * @arg @ref LL_RCC_APB1_DIV_16 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1)); +} + +/** + * @brief Get APB2 prescaler + * @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_APB2_DIV_1 + * @arg @ref LL_RCC_APB2_DIV_2 + * @arg @ref LL_RCC_APB2_DIV_4 + * @arg @ref LL_RCC_APB2_DIV_8 + * @arg @ref LL_RCC_APB2_DIV_16 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2)); +} + +/** + * @brief Set Clock After Wake-Up From Stop mode + * @rmtoll CFGR STOPWUCK LL_RCC_SetClkAfterWakeFromStop + * @param Clock This parameter can be one of the following values: + * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_MSI + * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSI + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetClkAfterWakeFromStop(uint32_t Clock) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, Clock); +} + +/** + * @brief Get Clock After Wake-Up From Stop mode + * @rmtoll CFGR STOPWUCK LL_RCC_GetClkAfterWakeFromStop + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_MSI + * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSI + */ +__STATIC_INLINE uint32_t LL_RCC_GetClkAfterWakeFromStop(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_STOPWUCK)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_MCO MCO + * @{ + */ + +/** + * @brief Configure MCOx + * @rmtoll CFGR MCOSEL LL_RCC_ConfigMCO\n + * CFGR MCOPRE LL_RCC_ConfigMCO + * @param MCOxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK + * @arg @ref LL_RCC_MCO1SOURCE_SYSCLK + * @arg @ref LL_RCC_MCO1SOURCE_MSI + * @arg @ref LL_RCC_MCO1SOURCE_HSI + * @arg @ref LL_RCC_MCO1SOURCE_HSE + * @arg @ref LL_RCC_MCO1SOURCE_HSI48 (*) + * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK + * @arg @ref LL_RCC_MCO1SOURCE_LSI + * @arg @ref LL_RCC_MCO1SOURCE_LSE + * + * (*) value not defined in all devices. + * @param MCOxPrescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_MCO1_DIV_1 + * @arg @ref LL_RCC_MCO1_DIV_2 + * @arg @ref LL_RCC_MCO1_DIV_4 + * @arg @ref LL_RCC_MCO1_DIV_8 + * @arg @ref LL_RCC_MCO1_DIV_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE, MCOxSource | MCOxPrescaler); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source + * @{ + */ + +/** + * @brief Configure USARTx clock source + * @rmtoll CCIPR USARTxSEL LL_RCC_SetUSARTClockSource + * @param USARTxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*) + * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource) +{ + MODIFY_REG(RCC->CCIPR, (USARTxSource >> 16U), (USARTxSource & 0x0000FFFFU)); +} + +#if defined(UART4) || defined(UART5) +/** + * @brief Configure UARTx clock source + * @rmtoll CCIPR UARTxSEL LL_RCC_SetUARTClockSource + * @param UARTxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI + * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE + * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI + * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetUARTClockSource(uint32_t UARTxSource) +{ + MODIFY_REG(RCC->CCIPR, (UARTxSource >> 16U), (UARTxSource & 0x0000FFFFU)); +} +#endif /* UART4 || UART5 */ + +/** + * @brief Configure LPUART1x clock source + * @rmtoll CCIPR LPUART1SEL LL_RCC_SetLPUARTClockSource + * @param LPUARTxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource) +{ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, LPUARTxSource); +} + +/** + * @brief Configure I2Cx clock source + * @rmtoll CCIPR I2CxSEL LL_RCC_SetI2CClockSource + * @param I2CxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK (*) + * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_I2C4_CLKSOURCE_SYSCLK (*) + * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource) +{ + __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0x88U + (I2CxSource >> 24U)); + MODIFY_REG(*reg, 3UL << ((I2CxSource & 0x001F0000U) >> 16U), ((I2CxSource & 0x000000FFU) << ((I2CxSource & 0x001F0000U) >> 16U))); +} + +/** + * @brief Configure LPTIMx clock source + * @rmtoll CCIPR LPTIMxSEL LL_RCC_SetLPTIMClockSource + * @param LPTIMxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_HSI + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource) +{ + MODIFY_REG(RCC->CCIPR, (LPTIMxSource & 0xFFFF0000U), (LPTIMxSource << 16U)); +} + +#if defined(RCC_CCIPR_SAI1SEL) || defined(RCC_CCIPR2_SAI1SEL) +/** + * @brief Configure SAIx clock source + @if STM32L4S9xx + * @rmtoll CCIPR2 SAIxSEL LL_RCC_SetSAIClockSource + @else + * @rmtoll CCIPR SAIxSEL LL_RCC_SetSAIClockSource + @endif + * @param SAIxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI1 + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI2 (*) + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI1 (*) + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI2 (*) + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL (*) + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource) +{ +#if defined(RCC_CCIPR2_SAI1SEL) + MODIFY_REG(RCC->CCIPR2, (SAIxSource >> 16U), (SAIxSource & 0x0000FFFFU)); +#else + MODIFY_REG(RCC->CCIPR, (SAIxSource & 0xFFFF0000U), (SAIxSource << 16U)); +#endif /* RCC_CCIPR2_SAI1SEL */ +} +#endif /* RCC_CCIPR_SAI1SEL || RCC_CCIPR2_SAI1SEL */ + +#if defined(RCC_CCIPR2_SDMMCSEL) +/** + * @brief Configure SDMMC1 kernel clock source + * @rmtoll CCIPR2 SDMMCSEL LL_RCC_SetSDMMCKernelClockSource + * @param SDMMCxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE_48CLK (*) + * @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE_PLLP (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSDMMCKernelClockSource(uint32_t SDMMCxSource) +{ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL, SDMMCxSource); +} +#endif /* RCC_CCIPR2_SDMMCSEL */ + +/** + * @brief Configure SDMMC1 clock source + * @rmtoll CCIPR CLK48SEL LL_RCC_SetSDMMCClockSource + * @param SDMMCxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_NONE (*) + * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_HSI48 (*) + * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1 (*) + * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL + * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_MSI (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSDMMCClockSource(uint32_t SDMMCxSource) +{ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, SDMMCxSource); +} + +/** + * @brief Configure RNG clock source + * @rmtoll CCIPR CLK48SEL LL_RCC_SetRNGClockSource + * @param RNGxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_RNG_CLKSOURCE_NONE (*) + * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48 (*) + * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI1 (*) + * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL + * @arg @ref LL_RCC_RNG_CLKSOURCE_MSI + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource) +{ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, RNGxSource); +} + +#if defined(USB_OTG_FS) || defined(USB) +/** + * @brief Configure USB clock source + * @rmtoll CCIPR CLK48SEL LL_RCC_SetUSBClockSource + * @param USBxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_USB_CLKSOURCE_NONE (*) + * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48 (*) + * @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI1 (*) + * @arg @ref LL_RCC_USB_CLKSOURCE_PLL + * @arg @ref LL_RCC_USB_CLKSOURCE_MSI + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource) +{ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, USBxSource); +} +#endif /* USB_OTG_FS || USB */ + +#if defined(RCC_CCIPR_ADCSEL) +/** + * @brief Configure ADC clock source + * @rmtoll CCIPR ADCSEL LL_RCC_SetADCClockSource + * @param ADCxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_ADC_CLKSOURCE_NONE + * @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI1 (*) + * @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI2 (*) + * @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource) +{ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, ADCxSource); +} +#endif /* RCC_CCIPR_ADCSEL */ + +#if defined(SWPMI1) +/** + * @brief Configure SWPMI clock source + * @rmtoll CCIPR SWPMI1SEL LL_RCC_SetSWPMIClockSource + * @param SWPMIxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_SWPMI1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_SWPMI1_CLKSOURCE_HSI + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSWPMIClockSource(uint32_t SWPMIxSource) +{ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL, SWPMIxSource); +} +#endif /* SWPMI1 */ + +#if defined(DFSDM1_Channel0) +#if defined(RCC_CCIPR2_ADFSDM1SEL) +/** + * @brief Configure DFSDM Audio clock source + * @rmtoll CCIPR2 ADFSDM1SEL LL_RCC_SetDFSDMAudioClockSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1 + * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_HSI + * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_MSI + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetDFSDMAudioClockSource(uint32_t Source) +{ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_ADFSDM1SEL, Source); +} +#endif /* RCC_CCIPR2_ADFSDM1SEL */ + +/** + * @brief Configure DFSDM Kernel clock source + @if STM32L4S9xx + * @rmtoll CCIPR2 DFSDM1SEL LL_RCC_SetDFSDMClockSource + @else + * @rmtoll CCIPR DFSDM1SEL LL_RCC_SetDFSDMClockSource + @endif + * @param DFSDMxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetDFSDMClockSource(uint32_t DFSDMxSource) +{ +#if defined(RCC_CCIPR2_DFSDM1SEL) + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_DFSDM1SEL, DFSDMxSource); +#else + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL, DFSDMxSource); +#endif /* RCC_CCIPR2_DFSDM1SEL */ +} +#endif /* DFSDM1_Channel0 */ + +#if defined(DSI) +/** + * @brief Configure DSI clock source + * @rmtoll CCIPR2 DSISEL LL_RCC_SetDSIClockSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_DSI_CLKSOURCE_PHY + * @arg @ref LL_RCC_DSI_CLKSOURCE_PLL + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetDSIClockSource(uint32_t Source) +{ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_DSISEL, Source); +} +#endif /* DSI */ + +#if defined(LTDC) +/** + * @brief Configure LTDC Clock Source + * @rmtoll CCIPR2 PLLSAI2DIVR LL_RCC_SetLTDCClockSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV2 + * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV4 + * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV8 + * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetLTDCClockSource(uint32_t Source) +{ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_PLLSAI2DIVR, Source); +} +#endif /* LTDC */ + +#if defined(OCTOSPI1) +/** + * @brief Configure OCTOSPI clock source + * @rmtoll CCIPR2 OSPISEL LL_RCC_SetOCTOSPIClockSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_MSI + * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_PLL + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetOCTOSPIClockSource(uint32_t Source) +{ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_OSPISEL, Source); +} +#endif /* OCTOSPI1 */ + +/** + * @brief Get USARTx clock source + * @rmtoll CCIPR USARTxSEL LL_RCC_GetUSARTClockSource + * @param USARTx This parameter can be one of the following values: + * @arg @ref LL_RCC_USART1_CLKSOURCE + * @arg @ref LL_RCC_USART2_CLKSOURCE + * @arg @ref LL_RCC_USART3_CLKSOURCE (*) + * + * (*) value not defined in all devices. + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*) + * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*) + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR, USARTx) | (USARTx << 16U)); +} + +#if defined(UART4) || defined(UART5) +/** + * @brief Get UARTx clock source + * @rmtoll CCIPR UARTxSEL LL_RCC_GetUARTClockSource + * @param UARTx This parameter can be one of the following values: + * @arg @ref LL_RCC_UART4_CLKSOURCE + * @arg @ref LL_RCC_UART5_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI + * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE + * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI + * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE + */ +__STATIC_INLINE uint32_t LL_RCC_GetUARTClockSource(uint32_t UARTx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR, UARTx) | (UARTx << 16U)); +} +#endif /* UART4 || UART5 */ + +/** + * @brief Get LPUARTx clock source + * @rmtoll CCIPR LPUART1SEL LL_RCC_GetLPUARTClockSource + * @param LPUARTx This parameter can be one of the following values: + * @arg @ref LL_RCC_LPUART1_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE + */ +__STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR, LPUARTx)); +} + +/** + * @brief Get I2Cx clock source + * @rmtoll CCIPR I2CxSEL LL_RCC_GetI2CClockSource + * @param I2Cx This parameter can be one of the following values: + * @arg @ref LL_RCC_I2C1_CLKSOURCE + * @arg @ref LL_RCC_I2C2_CLKSOURCE (*) + * @arg @ref LL_RCC_I2C3_CLKSOURCE + * @arg @ref LL_RCC_I2C4_CLKSOURCE (*) + * + * (*) value not defined in all devices. + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK (*) + * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_I2C4_CLKSOURCE_SYSCLK (*) + * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI (*) + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx) +{ + __IO const uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0x88U + (I2Cx >> 24U)); + return (uint32_t)((READ_BIT(*reg, 3UL << ((I2Cx & 0x001F0000U) >> 16U)) >> ((I2Cx & 0x001F0000U) >> 16U)) | (I2Cx & 0xFFFF0000U)); +} + +/** + * @brief Get LPTIMx clock source + * @rmtoll CCIPR LPTIMxSEL LL_RCC_GetLPTIMClockSource + * @param LPTIMx This parameter can be one of the following values: + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_HSI + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE + */ +__STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx) +{ + return (uint32_t)((READ_BIT(RCC->CCIPR, LPTIMx) >> 16U) | LPTIMx); +} + +#if defined(RCC_CCIPR_SAI1SEL) || defined(RCC_CCIPR2_SAI1SEL) +/** + * @brief Get SAIx clock source + @if STM32L4S9xx + * @rmtoll CCIPR2 SAIxSEL LL_RCC_GetSAIClockSource + @else + * @rmtoll CCIPR SAIxSEL LL_RCC_GetSAIClockSource + @endif + * @param SAIx This parameter can be one of the following values: + * @arg @ref LL_RCC_SAI1_CLKSOURCE + * @arg @ref LL_RCC_SAI2_CLKSOURCE (*) + * + * (*) value not defined in all devices. + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI1 + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI2 (*) + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI1 (*) + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI2 (*) + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL (*) + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN (*) + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx) +{ +#if defined(RCC_CCIPR2_SAI1SEL) + return (uint32_t)(READ_BIT(RCC->CCIPR2, SAIx) | (SAIx << 16U)); +#else + return (uint32_t)(READ_BIT(RCC->CCIPR, SAIx) >> 16U | SAIx); +#endif /* RCC_CCIPR2_SAI1SEL */ +} +#endif /* RCC_CCIPR_SAI1SEL || RCC_CCIPR2_SAI1SEL */ + +#if defined(SDMMC1) +#if defined(RCC_CCIPR2_SDMMCSEL) +/** + * @brief Get SDMMCx kernel clock source + * @rmtoll CCIPR2 SDMMCSEL LL_RCC_GetSDMMCKernelClockSource + * @param SDMMCx This parameter can be one of the following values: + * @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE_48CLK (*) + * @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE_PLL (*) + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_RCC_GetSDMMCKernelClockSource(uint32_t SDMMCx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR2, SDMMCx)); +} +#endif /* RCC_CCIPR2_SDMMCSEL */ + +/** + * @brief Get SDMMCx clock source + * @rmtoll CCIPR CLK48SEL LL_RCC_GetSDMMCClockSource + * @param SDMMCx This parameter can be one of the following values: + * @arg @ref LL_RCC_SDMMC1_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_NONE (*) + * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_HSI48 (*) + * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1 (*) + * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL + * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_MSI (*) + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_RCC_GetSDMMCClockSource(uint32_t SDMMCx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR, SDMMCx)); +} +#endif /* SDMMC1 */ + +/** + * @brief Get RNGx clock source + * @rmtoll CCIPR CLK48SEL LL_RCC_GetRNGClockSource + * @param RNGx This parameter can be one of the following values: + * @arg @ref LL_RCC_RNG_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_RNG_CLKSOURCE_NONE (*) + * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48 (*) + * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI1 (*) + * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL + * @arg @ref LL_RCC_RNG_CLKSOURCE_MSI + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR, RNGx)); +} + +#if defined(USB_OTG_FS) || defined(USB) +/** + * @brief Get USBx clock source + * @rmtoll CCIPR CLK48SEL LL_RCC_GetUSBClockSource + * @param USBx This parameter can be one of the following values: + * @arg @ref LL_RCC_USB_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_USB_CLKSOURCE_NONE (*) + * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48 (*) + * @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI1 (*) + * @arg @ref LL_RCC_USB_CLKSOURCE_PLL + * @arg @ref LL_RCC_USB_CLKSOURCE_MSI + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR, USBx)); +} +#endif /* USB_OTG_FS || USB */ + +/** + * @brief Get ADCx clock source + * @rmtoll CCIPR ADCSEL LL_RCC_GetADCClockSource + * @param ADCx This parameter can be one of the following values: + * @arg @ref LL_RCC_ADC_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_ADC_CLKSOURCE_NONE + * @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI1 (*) + * @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI2 (*) + * @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx) +{ +#if defined(RCC_CCIPR_ADCSEL) + return (uint32_t)(READ_BIT(RCC->CCIPR, ADCx)); +#else + (void)ADCx; /* unused */ + return ((READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) != 0U) ? LL_RCC_ADC_CLKSOURCE_SYSCLK : LL_RCC_ADC_CLKSOURCE_NONE); +#endif /* RCC_CCIPR_ADCSEL */ +} + +#if defined(SWPMI1) +/** + * @brief Get SWPMIx clock source + * @rmtoll CCIPR SWPMI1SEL LL_RCC_GetSWPMIClockSource + * @param SPWMIx This parameter can be one of the following values: + * @arg @ref LL_RCC_SWPMI1_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SWPMI1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_SWPMI1_CLKSOURCE_HSI + */ +__STATIC_INLINE uint32_t LL_RCC_GetSWPMIClockSource(uint32_t SPWMIx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR, SPWMIx)); +} +#endif /* SWPMI1 */ + +#if defined(DFSDM1_Channel0) +#if defined(RCC_CCIPR2_ADFSDM1SEL) +/** + * @brief Get DFSDM Audio Clock Source + * @rmtoll CCIPR2 ADFSDM1SEL LL_RCC_GetDFSDMAudioClockSource + * @param DFSDMx This parameter can be one of the following values: + * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1 + * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_HSI + * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_MSI + */ +__STATIC_INLINE uint32_t LL_RCC_GetDFSDMAudioClockSource(uint32_t DFSDMx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR2, DFSDMx)); +} +#endif /* RCC_CCIPR2_ADFSDM1SEL */ + +/** + * @brief Get DFSDMx Kernel clock source + @if STM32L4S9xx + * @rmtoll CCIPR2 DFSDM1SEL LL_RCC_GetDFSDMClockSource + @else + * @rmtoll CCIPR DFSDM1SEL LL_RCC_GetDFSDMClockSource + @endif + * @param DFSDMx This parameter can be one of the following values: + * @arg @ref LL_RCC_DFSDM1_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK + */ +__STATIC_INLINE uint32_t LL_RCC_GetDFSDMClockSource(uint32_t DFSDMx) +{ +#if defined(RCC_CCIPR2_DFSDM1SEL) + return (uint32_t)(READ_BIT(RCC->CCIPR2, DFSDMx)); +#else + return (uint32_t)(READ_BIT(RCC->CCIPR, DFSDMx)); +#endif /* RCC_CCIPR2_DFSDM1SEL */ +} +#endif /* DFSDM1_Channel0 */ + +#if defined(DSI) +/** + * @brief Get DSI Clock Source + * @rmtoll CCIPR2 DSISEL LL_RCC_GetDSIClockSource + * @param DSIx This parameter can be one of the following values: + * @arg @ref LL_RCC_DSI_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_DSI_CLKSOURCE_PHY + * @arg @ref LL_RCC_DSI_CLKSOURCE_PLL + */ +__STATIC_INLINE uint32_t LL_RCC_GetDSIClockSource(uint32_t DSIx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR2, DSIx)); +} +#endif /* DSI */ + +#if defined(LTDC) +/** + * @brief Get LTDC Clock Source + * @rmtoll CCIPR2 PLLSAI2DIVR LL_RCC_GetLTDCClockSource + * @param LTDCx This parameter can be one of the following values: + * @arg @ref LL_RCC_LTDC_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV2 + * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV4 + * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV8 + * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV16 + */ +__STATIC_INLINE uint32_t LL_RCC_GetLTDCClockSource(uint32_t LTDCx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR2, LTDCx)); +} +#endif /* LTDC */ + +#if defined(OCTOSPI1) +/** + * @brief Get OCTOSPI clock source + * @rmtoll CCIPR2 OSPISEL LL_RCC_GetOCTOSPIClockSource + * @param OCTOSPIx This parameter can be one of the following values: + * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_MSI + * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_PLL + */ +__STATIC_INLINE uint32_t LL_RCC_GetOCTOSPIClockSource(uint32_t OCTOSPIx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR2, OCTOSPIx)); +} +#endif /* OCTOSPI1 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EF_RTC RTC + * @{ + */ + +/** + * @brief Set RTC Clock Source + * @note Once the RTC clock source has been selected, it cannot be changed anymore unless + * the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is + * set). The BDRST bit can be used to reset them. + * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI + * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source) +{ + MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source); +} + +/** + * @brief Get RTC Clock Source + * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI + * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32 + */ +__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void) +{ + return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)); +} + +/** + * @brief Enable RTC + * @rmtoll BDCR RTCEN LL_RCC_EnableRTC + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableRTC(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN); +} + +/** + * @brief Disable RTC + * @rmtoll BDCR RTCEN LL_RCC_DisableRTC + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableRTC(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN); +} + +/** + * @brief Check if RTC has been enabled or not + * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void) +{ + return ((READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == RCC_BDCR_RTCEN) ? 1UL : 0UL); +} + +/** + * @brief Force the Backup domain reset + * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset + * @retval None + */ +__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_BDRST); +} + +/** + * @brief Release the Backup domain reset + * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset + * @retval None + */ +__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST); +} + +/** + * @} + */ + + +/** @defgroup RCC_LL_EF_PLL PLL + * @{ + */ + +/** + * @brief Enable PLL + * @rmtoll CR PLLON LL_RCC_PLL_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_PLLON); +} + +/** + * @brief Disable PLL + * @note Cannot be disabled if the PLL clock is used as the system clock + * @rmtoll CR PLLON LL_RCC_PLL_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_PLLON); +} + +/** + * @brief Check if PLL Ready + * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_PLLRDY) == RCC_CR_PLLRDY) ? 1UL : 0UL); +} + +/** + * @brief Configure PLL used for SYSCLK Domain + * @note PLL Source and PLLM Divider can be written only when PLL, + * PLLSAI1 and PLLSAI2 (*) are disabled. + * @note PLLN/PLLR can be written only when PLL is disabled. + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n + * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SYS\n + * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SYS\n + * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SYS + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_NONE + * @arg @ref LL_RCC_PLLSOURCE_MSI + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_1 + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 (*) + * @arg @ref LL_RCC_PLLM_DIV_10 (*) + * @arg @ref LL_RCC_PLLM_DIV_11 (*) + * @arg @ref LL_RCC_PLLM_DIV_12 (*) + * @arg @ref LL_RCC_PLLM_DIV_13 (*) + * @arg @ref LL_RCC_PLLM_DIV_14 (*) + * @arg @ref LL_RCC_PLLM_DIV_15 (*) + * @arg @ref LL_RCC_PLLM_DIV_16 (*) + * + * (*) value not defined in all devices. + * @param PLLN Between 8 and 86 or 127 depending on devices + * @param PLLR This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLR_DIV_2 + * @arg @ref LL_RCC_PLLR_DIV_4 + * @arg @ref LL_RCC_PLLR_DIV_6 + * @arg @ref LL_RCC_PLLR_DIV_8 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR, + Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLR); +} + +#if defined(RCC_PLLP_SUPPORT) +#if defined(RCC_PLLP_DIV_2_31_SUPPORT) +/** + * @brief Configure PLL used for SAI domain clock + * @note PLL Source and PLLM Divider can be written only when PLL, + * PLLSAI1 and PLLSAI2 (*) are disabled. + * @note PLLN/PLLP can be written only when PLL is disabled. + * @note This can be selected for SAI1 or SAI2 (*) + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SAI\n + * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SAI\n + * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SAI\n + * PLLCFGR PLLPDIV LL_RCC_PLL_ConfigDomain_SAI + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_NONE + * @arg @ref LL_RCC_PLLSOURCE_MSI + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_1 + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 (*) + * @arg @ref LL_RCC_PLLM_DIV_10 (*) + * @arg @ref LL_RCC_PLLM_DIV_11 (*) + * @arg @ref LL_RCC_PLLM_DIV_12 (*) + * @arg @ref LL_RCC_PLLM_DIV_13 (*) + * @arg @ref LL_RCC_PLLM_DIV_14 (*) + * @arg @ref LL_RCC_PLLM_DIV_15 (*) + * @arg @ref LL_RCC_PLLM_DIV_16 (*) + * + * (*) value not defined in all devices. + * @param PLLN Between 8 and 86 or 127 depending on devices + * @param PLLP This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLP_DIV_2 + * @arg @ref LL_RCC_PLLP_DIV_3 + * @arg @ref LL_RCC_PLLP_DIV_4 + * @arg @ref LL_RCC_PLLP_DIV_5 + * @arg @ref LL_RCC_PLLP_DIV_6 + * @arg @ref LL_RCC_PLLP_DIV_7 + * @arg @ref LL_RCC_PLLP_DIV_8 + * @arg @ref LL_RCC_PLLP_DIV_9 + * @arg @ref LL_RCC_PLLP_DIV_10 + * @arg @ref LL_RCC_PLLP_DIV_11 + * @arg @ref LL_RCC_PLLP_DIV_12 + * @arg @ref LL_RCC_PLLP_DIV_13 + * @arg @ref LL_RCC_PLLP_DIV_14 + * @arg @ref LL_RCC_PLLP_DIV_15 + * @arg @ref LL_RCC_PLLP_DIV_16 + * @arg @ref LL_RCC_PLLP_DIV_17 + * @arg @ref LL_RCC_PLLP_DIV_18 + * @arg @ref LL_RCC_PLLP_DIV_19 + * @arg @ref LL_RCC_PLLP_DIV_20 + * @arg @ref LL_RCC_PLLP_DIV_21 + * @arg @ref LL_RCC_PLLP_DIV_22 + * @arg @ref LL_RCC_PLLP_DIV_23 + * @arg @ref LL_RCC_PLLP_DIV_24 + * @arg @ref LL_RCC_PLLP_DIV_25 + * @arg @ref LL_RCC_PLLP_DIV_26 + * @arg @ref LL_RCC_PLLP_DIV_27 + * @arg @ref LL_RCC_PLLP_DIV_28 + * @arg @ref LL_RCC_PLLP_DIV_29 + * @arg @ref LL_RCC_PLLP_DIV_30 + * @arg @ref LL_RCC_PLLP_DIV_31 + * @retval None + */ +#else +/** + * @brief Configure PLL used for SAI domain clock + * @note PLL Source and PLLM Divider can be written only when PLL, + * PLLSAI1 and PLLSAI2 (*) are disabled. + * @note PLLN/PLLP can be written only when PLL is disabled. + * @note This can be selected for SAI1 or SAI2 (*) + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SAI\n + * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SAI\n + * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SAI\n + * PLLCFGR PLLP LL_RCC_PLL_ConfigDomain_SAI + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_NONE + * @arg @ref LL_RCC_PLLSOURCE_MSI + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_1 + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @param PLLN Between 8 and 86 + * @param PLLP This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLP_DIV_7 + * @arg @ref LL_RCC_PLLP_DIV_17 + * @retval None + */ +#endif /* RCC_PLLP_DIV_2_31_SUPPORT */ +__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP) +{ +#if defined(RCC_PLLP_DIV_2_31_SUPPORT) + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLPDIV, + Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLP); +#else + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLP, + Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLP); +#endif /* RCC_PLLP_DIV_2_31_SUPPORT */ +} +#endif /* RCC_PLLP_SUPPORT */ + +/** + * @brief Configure PLL used for 48Mhz domain clock + * @note PLL Source and PLLM Divider can be written only when PLL, + * PLLSAI1 and PLLSAI2 (*) are disabled. + * @note PLLN/PLLQ can be written only when PLL is disabled. + * @note This can be selected for USB, RNG, SDMMC + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_48M\n + * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_48M\n + * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_48M\n + * PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_48M + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_NONE + * @arg @ref LL_RCC_PLLSOURCE_MSI + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_1 + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 (*) + * @arg @ref LL_RCC_PLLM_DIV_10 (*) + * @arg @ref LL_RCC_PLLM_DIV_11 (*) + * @arg @ref LL_RCC_PLLM_DIV_12 (*) + * @arg @ref LL_RCC_PLLM_DIV_13 (*) + * @arg @ref LL_RCC_PLLM_DIV_14 (*) + * @arg @ref LL_RCC_PLLM_DIV_15 (*) + * @arg @ref LL_RCC_PLLM_DIV_16 (*) + * + * (*) value not defined in all devices. + * @param PLLN Between 8 and 86 or 127 depending on devices + * @param PLLQ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLQ_DIV_2 + * @arg @ref LL_RCC_PLLQ_DIV_4 + * @arg @ref LL_RCC_PLLQ_DIV_6 + * @arg @ref LL_RCC_PLLQ_DIV_8 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ, + Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLQ); +} + +/** + * @brief Configure PLL clock source + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_SetMainSource + * @param PLLSource This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_NONE + * @arg @ref LL_RCC_PLLSOURCE_MSI + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSource); +} + +/** + * @brief Get the oscillator used as PLL clock source. + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_NONE + * @arg @ref LL_RCC_PLLSOURCE_MSI + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC)); +} + +/** + * @brief Get Main PLL multiplication factor for VCO + * @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN + * @retval Between 8 and 86 or 127 depending on devices + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); +} + +#if defined(RCC_PLLP_SUPPORT) +#if defined(RCC_PLLP_DIV_2_31_SUPPORT) +/** + * @brief Get Main PLL division factor for PLLP + * @note Used for PLLSAI3CLK (SAI1 and SAI2 clock) + * @rmtoll PLLCFGR PLLPDIV LL_RCC_PLL_GetP + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLP_DIV_2 + * @arg @ref LL_RCC_PLLP_DIV_3 + * @arg @ref LL_RCC_PLLP_DIV_4 + * @arg @ref LL_RCC_PLLP_DIV_5 + * @arg @ref LL_RCC_PLLP_DIV_6 + * @arg @ref LL_RCC_PLLP_DIV_7 + * @arg @ref LL_RCC_PLLP_DIV_8 + * @arg @ref LL_RCC_PLLP_DIV_9 + * @arg @ref LL_RCC_PLLP_DIV_10 + * @arg @ref LL_RCC_PLLP_DIV_11 + * @arg @ref LL_RCC_PLLP_DIV_12 + * @arg @ref LL_RCC_PLLP_DIV_13 + * @arg @ref LL_RCC_PLLP_DIV_14 + * @arg @ref LL_RCC_PLLP_DIV_15 + * @arg @ref LL_RCC_PLLP_DIV_16 + * @arg @ref LL_RCC_PLLP_DIV_17 + * @arg @ref LL_RCC_PLLP_DIV_18 + * @arg @ref LL_RCC_PLLP_DIV_19 + * @arg @ref LL_RCC_PLLP_DIV_20 + * @arg @ref LL_RCC_PLLP_DIV_21 + * @arg @ref LL_RCC_PLLP_DIV_22 + * @arg @ref LL_RCC_PLLP_DIV_23 + * @arg @ref LL_RCC_PLLP_DIV_24 + * @arg @ref LL_RCC_PLLP_DIV_25 + * @arg @ref LL_RCC_PLLP_DIV_26 + * @arg @ref LL_RCC_PLLP_DIV_27 + * @arg @ref LL_RCC_PLLP_DIV_28 + * @arg @ref LL_RCC_PLLP_DIV_29 + * @arg @ref LL_RCC_PLLP_DIV_30 + * @arg @ref LL_RCC_PLLP_DIV_31 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV)); +} +#else +/** + * @brief Get Main PLL division factor for PLLP + * @note Used for PLLSAI3CLK (SAI1 and SAI2 clock) + * @rmtoll PLLCFGR PLLP LL_RCC_PLL_GetP + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLP_DIV_7 + * @arg @ref LL_RCC_PLLP_DIV_17 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP)); +} +#endif /* RCC_PLLP_DIV_2_31_SUPPORT */ +#endif /* RCC_PLLP_SUPPORT */ + +/** + * @brief Get Main PLL division factor for PLLQ + * @note Used for PLL48M1CLK selected for USB, RNG, SDMMC (48 MHz clock) + * @rmtoll PLLCFGR PLLQ LL_RCC_PLL_GetQ + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLQ_DIV_2 + * @arg @ref LL_RCC_PLLQ_DIV_4 + * @arg @ref LL_RCC_PLLQ_DIV_6 + * @arg @ref LL_RCC_PLLQ_DIV_8 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ)); +} + +/** + * @brief Get Main PLL division factor for PLLR + * @note Used for PLLCLK (system clock) + * @rmtoll PLLCFGR PLLR LL_RCC_PLL_GetR + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLR_DIV_2 + * @arg @ref LL_RCC_PLLR_DIV_4 + * @arg @ref LL_RCC_PLLR_DIV_6 + * @arg @ref LL_RCC_PLLR_DIV_8 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR)); +} + +/** + * @brief Get Division factor for the main PLL and other PLL + * @rmtoll PLLCFGR PLLM LL_RCC_PLL_GetDivider + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_1 + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 (*) + * @arg @ref LL_RCC_PLLM_DIV_10 (*) + * @arg @ref LL_RCC_PLLM_DIV_11 (*) + * @arg @ref LL_RCC_PLLM_DIV_12 (*) + * @arg @ref LL_RCC_PLLM_DIV_13 (*) + * @arg @ref LL_RCC_PLLM_DIV_14 (*) + * @arg @ref LL_RCC_PLLM_DIV_15 (*) + * @arg @ref LL_RCC_PLLM_DIV_16 (*) + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM)); +} + +#if defined(RCC_PLLP_SUPPORT) +/** + * @brief Enable PLL output mapped on SAI domain clock + * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_EnableDomain_SAI + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_EnableDomain_SAI(void) +{ + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN); +} + +/** + * @brief Disable PLL output mapped on SAI domain clock + * @note Cannot be disabled if the PLL clock is used as the system + * clock + * @note In order to save power, when the PLLCLK of the PLL is + * not used, should be 0 + * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_DisableDomain_SAI + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_DisableDomain_SAI(void) +{ + CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN); +} + +/** + * @brief Check if PLL output mapped on SAI domain clock is enabled + * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_IsEnabledDomain_SAI + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_SAI(void) +{ + return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN) == (RCC_PLLCFGR_PLLPEN)) ? 1UL : 0UL); +} + +#endif /* RCC_PLLP_SUPPORT */ + +/** + * @brief Enable PLL output mapped on 48MHz domain clock + * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_EnableDomain_48M + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_EnableDomain_48M(void) +{ + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN); +} + +/** + * @brief Disable PLL output mapped on 48MHz domain clock + * @note Cannot be disabled if the PLL clock is used as the system + * clock + * @note In order to save power, when the PLLCLK of the PLL is + * not used, should be 0 + * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_DisableDomain_48M + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_DisableDomain_48M(void) +{ + CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN); +} + +/** + * @brief Check if PLL output mapped on 48MHz domain clock is enabled + * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_IsEnabledDomain_48M + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_48M(void) +{ + return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN) == (RCC_PLLCFGR_PLLQEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable PLL output mapped on SYSCLK domain + * @rmtoll PLLCFGR PLLREN LL_RCC_PLL_EnableDomain_SYS + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_EnableDomain_SYS(void) +{ + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN); +} + +/** + * @brief Disable PLL output mapped on SYSCLK domain + * @note Cannot be disabled if the PLL clock is used as the system + * clock + * @note In order to save power, when the PLLCLK of the PLL is + * not used, Main PLL should be 0 + * @rmtoll PLLCFGR PLLREN LL_RCC_PLL_DisableDomain_SYS + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_DisableDomain_SYS(void) +{ + CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN); +} + +/** + * @brief Check if PLL output mapped on SYSCLK domain clock is enabled + * @rmtoll PLLCFGR PLLREN LL_RCC_PLL_IsEnabledDomain_SYS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_SYS(void) +{ + return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN) == (RCC_PLLCFGR_PLLREN)) ? 1UL : 0UL); +} + +/** + * @} + */ + +#if defined(RCC_PLLSAI1_SUPPORT) +/** @defgroup RCC_LL_EF_PLLSAI1 PLLSAI1 + * @{ + */ + +/** + * @brief Enable PLLSAI1 + * @rmtoll CR PLLSAI1ON LL_RCC_PLLSAI1_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLSAI1_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_PLLSAI1ON); +} + +/** + * @brief Disable PLLSAI1 + * @rmtoll CR PLLSAI1ON LL_RCC_PLLSAI1_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLSAI1_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI1ON); +} + +/** + * @brief Check if PLLSAI1 Ready + * @rmtoll CR PLLSAI1RDY LL_RCC_PLLSAI1_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == RCC_CR_PLLSAI1RDY) ? 1UL : 0UL); +} + +#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) +/** + * @brief Configure PLLSAI1 used for 48Mhz domain clock + * @note PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled. + * @note PLLSAI1M/PLLSAI1N/PLLSAI1Q can be written only when PLLSAI1 is disabled. + * @note This can be selected for USB, RNG, SDMMC + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_48M\n + * PLLSAI1CFGR PLLSAI1M LL_RCC_PLLSAI1_ConfigDomain_48M\n + * PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_48M\n + * PLLSAI1CFGR PLLSAI1Q LL_RCC_PLLSAI1_ConfigDomain_48M + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_NONE + * @arg @ref LL_RCC_PLLSOURCE_MSI + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI1M_DIV_1 + * @arg @ref LL_RCC_PLLSAI1M_DIV_2 + * @arg @ref LL_RCC_PLLSAI1M_DIV_3 + * @arg @ref LL_RCC_PLLSAI1M_DIV_4 + * @arg @ref LL_RCC_PLLSAI1M_DIV_5 + * @arg @ref LL_RCC_PLLSAI1M_DIV_6 + * @arg @ref LL_RCC_PLLSAI1M_DIV_7 + * @arg @ref LL_RCC_PLLSAI1M_DIV_8 + * @arg @ref LL_RCC_PLLSAI1M_DIV_9 + * @arg @ref LL_RCC_PLLSAI1M_DIV_10 + * @arg @ref LL_RCC_PLLSAI1M_DIV_11 + * @arg @ref LL_RCC_PLLSAI1M_DIV_12 + * @arg @ref LL_RCC_PLLSAI1M_DIV_13 + * @arg @ref LL_RCC_PLLSAI1M_DIV_14 + * @arg @ref LL_RCC_PLLSAI1M_DIV_15 + * @arg @ref LL_RCC_PLLSAI1M_DIV_16 + * @param PLLN Between 8 and 86 or 127 depending on devices + * @param PLLQ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI1Q_DIV_2 + * @arg @ref LL_RCC_PLLSAI1Q_DIV_4 + * @arg @ref LL_RCC_PLLSAI1Q_DIV_6 + * @arg @ref LL_RCC_PLLSAI1Q_DIV_8 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source); + MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M | RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1Q, + PLLM | (PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | PLLQ); +} +#else +/** + * @brief Configure PLLSAI1 used for 48Mhz domain clock + * @note PLL Source and PLLM Divider can be written only when PLL, + * PLLSAI1 and PLLSAI2 (*) are disabled. + * @note PLLSAI1N/PLLSAI1Q can be written only when PLLSAI1 is disabled. + * @note This can be selected for USB, RNG, SDMMC + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_48M\n + * PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_48M\n + * PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_48M\n + * PLLSAI1CFGR PLLSAI1Q LL_RCC_PLLSAI1_ConfigDomain_48M + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_NONE + * @arg @ref LL_RCC_PLLSOURCE_MSI + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_1 + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @param PLLN Between 8 and 86 or 127 depending on devices + * @param PLLQ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI1Q_DIV_2 + * @arg @ref LL_RCC_PLLSAI1Q_DIV_4 + * @arg @ref LL_RCC_PLLSAI1Q_DIV_6 + * @arg @ref LL_RCC_PLLSAI1Q_DIV_8 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM); + MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1Q, PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos | PLLQ); +} +#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ + +#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) && defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) +/** + * @brief Configure PLLSAI1 used for SAI domain clock + * @note PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled. + * @note PLLSAI1M/PLLSAI1N/PLLSAI1PDIV can be written only when PLLSAI1 is disabled. + * @note This can be selected for SAI1 or SAI2 + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_SAI\n + * PLLSAI1CFGR PLLSAI1M LL_RCC_PLLSAI1_ConfigDomain_SAI\n + * PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_SAI\n + * PLLSAI1CFGR PLLSAI1PDIV LL_RCC_PLLSAI1_ConfigDomain_SAI + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_NONE + * @arg @ref LL_RCC_PLLSOURCE_MSI + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI1M_DIV_1 + * @arg @ref LL_RCC_PLLSAI1M_DIV_2 + * @arg @ref LL_RCC_PLLSAI1M_DIV_3 + * @arg @ref LL_RCC_PLLSAI1M_DIV_4 + * @arg @ref LL_RCC_PLLSAI1M_DIV_5 + * @arg @ref LL_RCC_PLLSAI1M_DIV_6 + * @arg @ref LL_RCC_PLLSAI1M_DIV_7 + * @arg @ref LL_RCC_PLLSAI1M_DIV_8 + * @arg @ref LL_RCC_PLLSAI1M_DIV_9 + * @arg @ref LL_RCC_PLLSAI1M_DIV_10 + * @arg @ref LL_RCC_PLLSAI1M_DIV_11 + * @arg @ref LL_RCC_PLLSAI1M_DIV_12 + * @arg @ref LL_RCC_PLLSAI1M_DIV_13 + * @arg @ref LL_RCC_PLLSAI1M_DIV_14 + * @arg @ref LL_RCC_PLLSAI1M_DIV_15 + * @arg @ref LL_RCC_PLLSAI1M_DIV_16 + * @param PLLN Between 8 and 86 or 127 depending on devices + * @param PLLP This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI1P_DIV_2 + * @arg @ref LL_RCC_PLLSAI1P_DIV_3 + * @arg @ref LL_RCC_PLLSAI1P_DIV_4 + * @arg @ref LL_RCC_PLLSAI1P_DIV_5 + * @arg @ref LL_RCC_PLLSAI1P_DIV_6 + * @arg @ref LL_RCC_PLLSAI1P_DIV_7 + * @arg @ref LL_RCC_PLLSAI1P_DIV_8 + * @arg @ref LL_RCC_PLLSAI1P_DIV_9 + * @arg @ref LL_RCC_PLLSAI1P_DIV_10 + * @arg @ref LL_RCC_PLLSAI1P_DIV_11 + * @arg @ref LL_RCC_PLLSAI1P_DIV_12 + * @arg @ref LL_RCC_PLLSAI1P_DIV_13 + * @arg @ref LL_RCC_PLLSAI1P_DIV_14 + * @arg @ref LL_RCC_PLLSAI1P_DIV_15 + * @arg @ref LL_RCC_PLLSAI1P_DIV_16 + * @arg @ref LL_RCC_PLLSAI1P_DIV_17 + * @arg @ref LL_RCC_PLLSAI1P_DIV_18 + * @arg @ref LL_RCC_PLLSAI1P_DIV_19 + * @arg @ref LL_RCC_PLLSAI1P_DIV_20 + * @arg @ref LL_RCC_PLLSAI1P_DIV_21 + * @arg @ref LL_RCC_PLLSAI1P_DIV_22 + * @arg @ref LL_RCC_PLLSAI1P_DIV_23 + * @arg @ref LL_RCC_PLLSAI1P_DIV_24 + * @arg @ref LL_RCC_PLLSAI1P_DIV_25 + * @arg @ref LL_RCC_PLLSAI1P_DIV_26 + * @arg @ref LL_RCC_PLLSAI1P_DIV_27 + * @arg @ref LL_RCC_PLLSAI1P_DIV_28 + * @arg @ref LL_RCC_PLLSAI1P_DIV_29 + * @arg @ref LL_RCC_PLLSAI1P_DIV_30 + * @arg @ref LL_RCC_PLLSAI1P_DIV_31 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source); + MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M | RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1PDIV, + PLLM | (PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | PLLP); +} +#elif defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) +/** + * @brief Configure PLLSAI1 used for SAI domain clock + * @note PLL Source and PLLM Divider can be written only when PLL, + * PLLSAI1 and PLLSAI2 (*) are disabled. + * @note PLLSAI1N/PLLSAI1PDIV can be written only when PLLSAI1 is disabled. + * @note This can be selected for SAI1 or SAI2 (*) + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_SAI\n + * PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_SAI\n + * PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_SAI\n + * PLLSAI1CFGR PLLSAI1PDIV LL_RCC_PLLSAI1_ConfigDomain_SAI + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_NONE + * @arg @ref LL_RCC_PLLSOURCE_MSI + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_1 + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @param PLLN Between 8 and 86 or 127 depending on devices + * @param PLLP This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI1P_DIV_2 + * @arg @ref LL_RCC_PLLSAI1P_DIV_3 + * @arg @ref LL_RCC_PLLSAI1P_DIV_4 + * @arg @ref LL_RCC_PLLSAI1P_DIV_5 + * @arg @ref LL_RCC_PLLSAI1P_DIV_6 + * @arg @ref LL_RCC_PLLSAI1P_DIV_7 + * @arg @ref LL_RCC_PLLSAI1P_DIV_8 + * @arg @ref LL_RCC_PLLSAI1P_DIV_9 + * @arg @ref LL_RCC_PLLSAI1P_DIV_10 + * @arg @ref LL_RCC_PLLSAI1P_DIV_11 + * @arg @ref LL_RCC_PLLSAI1P_DIV_12 + * @arg @ref LL_RCC_PLLSAI1P_DIV_13 + * @arg @ref LL_RCC_PLLSAI1P_DIV_14 + * @arg @ref LL_RCC_PLLSAI1P_DIV_15 + * @arg @ref LL_RCC_PLLSAI1P_DIV_16 + * @arg @ref LL_RCC_PLLSAI1P_DIV_17 + * @arg @ref LL_RCC_PLLSAI1P_DIV_18 + * @arg @ref LL_RCC_PLLSAI1P_DIV_19 + * @arg @ref LL_RCC_PLLSAI1P_DIV_20 + * @arg @ref LL_RCC_PLLSAI1P_DIV_21 + * @arg @ref LL_RCC_PLLSAI1P_DIV_22 + * @arg @ref LL_RCC_PLLSAI1P_DIV_23 + * @arg @ref LL_RCC_PLLSAI1P_DIV_24 + * @arg @ref LL_RCC_PLLSAI1P_DIV_25 + * @arg @ref LL_RCC_PLLSAI1P_DIV_26 + * @arg @ref LL_RCC_PLLSAI1P_DIV_27 + * @arg @ref LL_RCC_PLLSAI1P_DIV_28 + * @arg @ref LL_RCC_PLLSAI1P_DIV_29 + * @arg @ref LL_RCC_PLLSAI1P_DIV_30 + * @arg @ref LL_RCC_PLLSAI1P_DIV_31 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM); + MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1PDIV, + PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos | PLLP); +} +#else +/** + * @brief Configure PLLSAI1 used for SAI domain clock + * @note PLL Source and PLLM Divider can be written only when PLL, + * PLLSAI1 and PLLSAI2 (*) are disabled. + * @note PLLSAI1N/PLLSAI1P can be written only when PLLSAI1 is disabled. + * @note This can be selected for SAI1 or SAI2 (*) + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_SAI\n + * PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_SAI\n + * PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_SAI\n + * PLLSAI1CFGR PLLSAI1P LL_RCC_PLLSAI1_ConfigDomain_SAI + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_NONE + * @arg @ref LL_RCC_PLLSOURCE_MSI + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_1 + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @param PLLN Between 8 and 86 + * @param PLLP This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI1P_DIV_7 + * @arg @ref LL_RCC_PLLSAI1P_DIV_17 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM); + MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1P, PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos | PLLP); +} +#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT && RCC_PLLSAI1P_DIV_2_31_SUPPORT */ + +#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) +/** + * @brief Configure PLLSAI1 used for ADC domain clock + * @note PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled. + * @note PLLSAI1M/PLLSAI1N/PLLSAI1R can be written only when PLLSAI1 is disabled. + * @note This can be selected for ADC + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_ADC\n + * PLLSAI1CFGR PLLSAI1M LL_RCC_PLLSAI1_ConfigDomain_ADC\n + * PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_ADC\n + * PLLSAI1CFGR PLLSAI1R LL_RCC_PLLSAI1_ConfigDomain_ADC + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_NONE + * @arg @ref LL_RCC_PLLSOURCE_MSI + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI1M_DIV_1 + * @arg @ref LL_RCC_PLLSAI1M_DIV_2 + * @arg @ref LL_RCC_PLLSAI1M_DIV_3 + * @arg @ref LL_RCC_PLLSAI1M_DIV_4 + * @arg @ref LL_RCC_PLLSAI1M_DIV_5 + * @arg @ref LL_RCC_PLLSAI1M_DIV_6 + * @arg @ref LL_RCC_PLLSAI1M_DIV_7 + * @arg @ref LL_RCC_PLLSAI1M_DIV_8 + * @arg @ref LL_RCC_PLLSAI1M_DIV_9 + * @arg @ref LL_RCC_PLLSAI1M_DIV_10 + * @arg @ref LL_RCC_PLLSAI1M_DIV_11 + * @arg @ref LL_RCC_PLLSAI1M_DIV_12 + * @arg @ref LL_RCC_PLLSAI1M_DIV_13 + * @arg @ref LL_RCC_PLLSAI1M_DIV_14 + * @arg @ref LL_RCC_PLLSAI1M_DIV_15 + * @arg @ref LL_RCC_PLLSAI1M_DIV_16 + * @param PLLN Between 8 and 86 or 127 depending on devices + * @param PLLR This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI1R_DIV_2 + * @arg @ref LL_RCC_PLLSAI1R_DIV_4 + * @arg @ref LL_RCC_PLLSAI1R_DIV_6 + * @arg @ref LL_RCC_PLLSAI1R_DIV_8 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source); + MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M | RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1R, + PLLM | (PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | PLLR); +} +#else +/** + * @brief Configure PLLSAI1 used for ADC domain clock + * @note PLL Source and PLLM Divider can be written only when PLL, + * PLLSAI1 and PLLSAI2 (*) are disabled. + * @note PLLN/PLLR can be written only when PLLSAI1 is disabled. + * @note This can be selected for ADC + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_ADC\n + * PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_ADC\n + * PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_ADC\n + * PLLSAI1CFGR PLLSAI1R LL_RCC_PLLSAI1_ConfigDomain_ADC + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_NONE + * @arg @ref LL_RCC_PLLSOURCE_MSI + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_1 + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @param PLLN Between 8 and 86 or 127 depending on devices + * @param PLLR This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI1R_DIV_2 + * @arg @ref LL_RCC_PLLSAI1R_DIV_4 + * @arg @ref LL_RCC_PLLSAI1R_DIV_6 + * @arg @ref LL_RCC_PLLSAI1R_DIV_8 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM); + MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1R, PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos | PLLR); +} +#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ + +/** + * @brief Get SAI1PLL multiplication factor for VCO + * @rmtoll PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_GetN + * @retval Between 8 and 86 or 127 depending on devices + */ +__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetN(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos); +} + +#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) +/** + * @brief Get SAI1PLL division factor for PLLSAI1P + * @note Used for PLLSAI1CLK (SAI1 or SAI2 (*) clock). + * @rmtoll PLLSAI1CFGR PLLSAI1PDIV LL_RCC_PLLSAI1_GetP + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLSAI1P_DIV_2 + * @arg @ref LL_RCC_PLLSAI1P_DIV_3 + * @arg @ref LL_RCC_PLLSAI1P_DIV_4 + * @arg @ref LL_RCC_PLLSAI1P_DIV_5 + * @arg @ref LL_RCC_PLLSAI1P_DIV_6 + * @arg @ref LL_RCC_PLLSAI1P_DIV_7 + * @arg @ref LL_RCC_PLLSAI1P_DIV_8 + * @arg @ref LL_RCC_PLLSAI1P_DIV_9 + * @arg @ref LL_RCC_PLLSAI1P_DIV_10 + * @arg @ref LL_RCC_PLLSAI1P_DIV_11 + * @arg @ref LL_RCC_PLLSAI1P_DIV_12 + * @arg @ref LL_RCC_PLLSAI1P_DIV_13 + * @arg @ref LL_RCC_PLLSAI1P_DIV_14 + * @arg @ref LL_RCC_PLLSAI1P_DIV_15 + * @arg @ref LL_RCC_PLLSAI1P_DIV_16 + * @arg @ref LL_RCC_PLLSAI1P_DIV_17 + * @arg @ref LL_RCC_PLLSAI1P_DIV_18 + * @arg @ref LL_RCC_PLLSAI1P_DIV_19 + * @arg @ref LL_RCC_PLLSAI1P_DIV_20 + * @arg @ref LL_RCC_PLLSAI1P_DIV_21 + * @arg @ref LL_RCC_PLLSAI1P_DIV_22 + * @arg @ref LL_RCC_PLLSAI1P_DIV_23 + * @arg @ref LL_RCC_PLLSAI1P_DIV_24 + * @arg @ref LL_RCC_PLLSAI1P_DIV_25 + * @arg @ref LL_RCC_PLLSAI1P_DIV_26 + * @arg @ref LL_RCC_PLLSAI1P_DIV_27 + * @arg @ref LL_RCC_PLLSAI1P_DIV_28 + * @arg @ref LL_RCC_PLLSAI1P_DIV_29 + * @arg @ref LL_RCC_PLLSAI1P_DIV_30 + * @arg @ref LL_RCC_PLLSAI1P_DIV_31 + */ +__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetP(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV)); +} +#else +/** + * @brief Get SAI1PLL division factor for PLLSAI1P + * @note Used for PLLSAI1CLK (SAI1 or SAI2 (*) clock). + * @rmtoll PLLSAI1CFGR PLLSAI1P LL_RCC_PLLSAI1_GetP + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLSAI1P_DIV_7 + * @arg @ref LL_RCC_PLLSAI1P_DIV_17 + */ +__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetP(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P)); +} +#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ + +/** + * @brief Get SAI1PLL division factor for PLLSAI1Q + * @note Used PLL48M2CLK selected for USB, RNG, SDMMC (48 MHz clock) + * @rmtoll PLLSAI1CFGR PLLSAI1Q LL_RCC_PLLSAI1_GetQ + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLSAI1Q_DIV_2 + * @arg @ref LL_RCC_PLLSAI1Q_DIV_4 + * @arg @ref LL_RCC_PLLSAI1Q_DIV_6 + * @arg @ref LL_RCC_PLLSAI1Q_DIV_8 + */ +__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetQ(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q)); +} + +/** + * @brief Get PLLSAI1 division factor for PLLSAIR + * @note Used for PLLADC1CLK (ADC clock) + * @rmtoll PLLSAI1CFGR PLLSAI1R LL_RCC_PLLSAI1_GetR + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLSAI1R_DIV_2 + * @arg @ref LL_RCC_PLLSAI1R_DIV_4 + * @arg @ref LL_RCC_PLLSAI1R_DIV_6 + * @arg @ref LL_RCC_PLLSAI1R_DIV_8 + */ +__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetR(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R)); +} + +#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) +/** + * @brief Get Division factor for the PLLSAI1 + * @rmtoll PLLSAI1CFGR PLLSAI1M LL_RCC_PLLSAI1_GetDivider + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLSAI1M_DIV_1 + * @arg @ref LL_RCC_PLLSAI1M_DIV_2 + * @arg @ref LL_RCC_PLLSAI1M_DIV_3 + * @arg @ref LL_RCC_PLLSAI1M_DIV_4 + * @arg @ref LL_RCC_PLLSAI1M_DIV_5 + * @arg @ref LL_RCC_PLLSAI1M_DIV_6 + * @arg @ref LL_RCC_PLLSAI1M_DIV_7 + * @arg @ref LL_RCC_PLLSAI1M_DIV_8 + * @arg @ref LL_RCC_PLLSAI1M_DIV_9 + * @arg @ref LL_RCC_PLLSAI1M_DIV_10 + * @arg @ref LL_RCC_PLLSAI1M_DIV_11 + * @arg @ref LL_RCC_PLLSAI1M_DIV_12 + * @arg @ref LL_RCC_PLLSAI1M_DIV_13 + * @arg @ref LL_RCC_PLLSAI1M_DIV_14 + * @arg @ref LL_RCC_PLLSAI1M_DIV_15 + * @arg @ref LL_RCC_PLLSAI1M_DIV_16 + */ +__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetDivider(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M)); +} +#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ + +/** + * @brief Enable PLLSAI1 output mapped on SAI domain clock + * @rmtoll PLLSAI1CFGR PLLSAI1PEN LL_RCC_PLLSAI1_EnableDomain_SAI + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_SAI(void) +{ + SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PEN); +} + +/** + * @brief Disable PLLSAI1 output mapped on SAI domain clock + * @note In order to save power, when of the PLLSAI1 is + * not used, should be 0 + * @rmtoll PLLSAI1CFGR PLLSAI1PEN LL_RCC_PLLSAI1_DisableDomain_SAI + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_SAI(void) +{ + CLEAR_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PEN); +} + +/** + * @brief Check if PLLSAI1 output mapped on SAI domain clock is enabled + * @rmtoll PLLSAI1CFGR PLLSAI1PEN LL_RCC_PLLSAI1_IsEnabledDomain_SAI + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_IsEnabledDomain_SAI(void) +{ + return ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PEN) == (RCC_PLLSAI1CFGR_PLLSAI1PEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable PLLSAI1 output mapped on 48MHz domain clock + * @rmtoll PLLSAI1CFGR PLLSAI1QEN LL_RCC_PLLSAI1_EnableDomain_48M + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_48M(void) +{ + SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN); +} + +/** + * @brief Disable PLLSAI1 output mapped on 48MHz domain clock + * @note In order to save power, when of the PLLSAI1 is + * not used, should be 0 + * @rmtoll PLLSAI1CFGR PLLSAI1QEN LL_RCC_PLLSAI1_DisableDomain_48M + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_48M(void) +{ + CLEAR_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN); +} + +/** + * @brief Check if PLLSAI1 output mapped on SAI domain clock is enabled + * @rmtoll PLLSAI1CFGR PLLSAI1QEN LL_RCC_PLLSAI1_IsEnabledDomain_48M + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_IsEnabledDomain_48M(void) +{ + return ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN) == (RCC_PLLSAI1CFGR_PLLSAI1QEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable PLLSAI1 output mapped on ADC domain clock + * @rmtoll PLLSAI1CFGR PLLSAI1REN LL_RCC_PLLSAI1_EnableDomain_ADC + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_ADC(void) +{ + SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1REN); +} + +/** + * @brief Disable PLLSAI1 output mapped on ADC domain clock + * @note In order to save power, when of the PLLSAI1 is + * not used, Main PLLSAI1 should be 0 + * @rmtoll PLLSAI1CFGR PLLSAI1REN LL_RCC_PLLSAI1_DisableDomain_ADC + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_ADC(void) +{ + CLEAR_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1REN); +} + +/** + * @brief Check if PLLSAI1 output mapped on ADC domain clock is enabled + * @rmtoll PLLSAI1CFGR PLLSAI1REN LL_RCC_PLLSAI1_IsEnabledDomain_ADC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_IsEnabledDomain_ADC(void) +{ + return ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1REN) == (RCC_PLLSAI1CFGR_PLLSAI1REN)) ? 1UL : 0UL); +} + +/** + * @} + */ +#endif /* RCC_PLLSAI1_SUPPORT */ + +#if defined(RCC_PLLSAI2_SUPPORT) +/** @defgroup RCC_LL_EF_PLLSAI2 PLLSAI2 + * @{ + */ + +/** + * @brief Enable PLLSAI2 + * @rmtoll CR PLLSAI2ON LL_RCC_PLLSAI2_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLSAI2_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_PLLSAI2ON); +} + +/** + * @brief Disable PLLSAI2 + * @rmtoll CR PLLSAI2ON LL_RCC_PLLSAI2_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLSAI2_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI2ON); +} + +/** + * @brief Check if PLLSAI2 Ready + * @rmtoll CR PLLSAI2RDY LL_RCC_PLLSAI2_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == RCC_CR_PLLSAI2RDY) ? 1UL : 0UL); +} + +#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) && defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) +/** + * @brief Configure PLLSAI2 used for SAI domain clock + * @note PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled. + * @note PLLSAI2M/PLLSAI2N/PLLSAI2PDIV can be written only when PLLSAI2 is disabled. + * @note This can be selected for SAI1 or SAI2 + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_SAI\n + * PLLSAI2CFGR PLLSAI2M LL_RCC_PLLSAI2_ConfigDomain_SAI\n + * PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_SAI\n + * PLLSAI2CFGR PLLSAI2PDIV LL_RCC_PLLSAI2_ConfigDomain_SAI + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_NONE + * @arg @ref LL_RCC_PLLSOURCE_MSI + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI2M_DIV_1 + * @arg @ref LL_RCC_PLLSAI2M_DIV_2 + * @arg @ref LL_RCC_PLLSAI2M_DIV_3 + * @arg @ref LL_RCC_PLLSAI2M_DIV_4 + * @arg @ref LL_RCC_PLLSAI2M_DIV_5 + * @arg @ref LL_RCC_PLLSAI2M_DIV_6 + * @arg @ref LL_RCC_PLLSAI2M_DIV_7 + * @arg @ref LL_RCC_PLLSAI2M_DIV_8 + * @arg @ref LL_RCC_PLLSAI2M_DIV_9 + * @arg @ref LL_RCC_PLLSAI2M_DIV_10 + * @arg @ref LL_RCC_PLLSAI2M_DIV_11 + * @arg @ref LL_RCC_PLLSAI2M_DIV_12 + * @arg @ref LL_RCC_PLLSAI2M_DIV_13 + * @arg @ref LL_RCC_PLLSAI2M_DIV_14 + * @arg @ref LL_RCC_PLLSAI2M_DIV_15 + * @arg @ref LL_RCC_PLLSAI2M_DIV_16 + * @param PLLN Between 8 and 86 or 127 depending on devices + * @param PLLP This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI2P_DIV_2 + * @arg @ref LL_RCC_PLLSAI2P_DIV_3 + * @arg @ref LL_RCC_PLLSAI2P_DIV_4 + * @arg @ref LL_RCC_PLLSAI2P_DIV_5 + * @arg @ref LL_RCC_PLLSAI2P_DIV_6 + * @arg @ref LL_RCC_PLLSAI2P_DIV_7 + * @arg @ref LL_RCC_PLLSAI2P_DIV_8 + * @arg @ref LL_RCC_PLLSAI2P_DIV_9 + * @arg @ref LL_RCC_PLLSAI2P_DIV_10 + * @arg @ref LL_RCC_PLLSAI2P_DIV_11 + * @arg @ref LL_RCC_PLLSAI2P_DIV_12 + * @arg @ref LL_RCC_PLLSAI2P_DIV_13 + * @arg @ref LL_RCC_PLLSAI2P_DIV_14 + * @arg @ref LL_RCC_PLLSAI2P_DIV_15 + * @arg @ref LL_RCC_PLLSAI2P_DIV_16 + * @arg @ref LL_RCC_PLLSAI2P_DIV_17 + * @arg @ref LL_RCC_PLLSAI2P_DIV_18 + * @arg @ref LL_RCC_PLLSAI2P_DIV_19 + * @arg @ref LL_RCC_PLLSAI2P_DIV_20 + * @arg @ref LL_RCC_PLLSAI2P_DIV_21 + * @arg @ref LL_RCC_PLLSAI2P_DIV_22 + * @arg @ref LL_RCC_PLLSAI2P_DIV_23 + * @arg @ref LL_RCC_PLLSAI2P_DIV_24 + * @arg @ref LL_RCC_PLLSAI2P_DIV_25 + * @arg @ref LL_RCC_PLLSAI2P_DIV_26 + * @arg @ref LL_RCC_PLLSAI2P_DIV_27 + * @arg @ref LL_RCC_PLLSAI2P_DIV_28 + * @arg @ref LL_RCC_PLLSAI2P_DIV_29 + * @arg @ref LL_RCC_PLLSAI2P_DIV_30 + * @arg @ref LL_RCC_PLLSAI2P_DIV_31 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source); + MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M | RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2PDIV, + PLLM | (PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | PLLP); +} +#elif defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) +/** + * @brief Configure PLLSAI2 used for SAI domain clock + * @note PLL Source and PLLM Divider can be written only when PLL, + * PLLSAI1 and PLLSAI2 are disabled. + * @note PLLSAI2N/PLLSAI2PDIV can be written only when PLLSAI2 is disabled. + * @note This can be selected for SAI1 or SAI2 + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_SAI\n + * PLLCFGR PLLM LL_RCC_PLLSAI2_ConfigDomain_SAI\n + * PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_SAI\n + * PLLSAI2CFGR PLLSAI2PDIV LL_RCC_PLLSAI2_ConfigDomain_SAI + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_NONE + * @arg @ref LL_RCC_PLLSOURCE_MSI + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_1 + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @param PLLN Between 8 and 86 or 127 depending on devices + * @param PLLP This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI2P_DIV_2 + * @arg @ref LL_RCC_PLLSAI2P_DIV_3 + * @arg @ref LL_RCC_PLLSAI2P_DIV_4 + * @arg @ref LL_RCC_PLLSAI2P_DIV_5 + * @arg @ref LL_RCC_PLLSAI2P_DIV_6 + * @arg @ref LL_RCC_PLLSAI2P_DIV_7 + * @arg @ref LL_RCC_PLLSAI2P_DIV_8 + * @arg @ref LL_RCC_PLLSAI2P_DIV_9 + * @arg @ref LL_RCC_PLLSAI2P_DIV_10 + * @arg @ref LL_RCC_PLLSAI2P_DIV_11 + * @arg @ref LL_RCC_PLLSAI2P_DIV_12 + * @arg @ref LL_RCC_PLLSAI2P_DIV_13 + * @arg @ref LL_RCC_PLLSAI2P_DIV_14 + * @arg @ref LL_RCC_PLLSAI2P_DIV_15 + * @arg @ref LL_RCC_PLLSAI2P_DIV_16 + * @arg @ref LL_RCC_PLLSAI2P_DIV_17 + * @arg @ref LL_RCC_PLLSAI2P_DIV_18 + * @arg @ref LL_RCC_PLLSAI2P_DIV_19 + * @arg @ref LL_RCC_PLLSAI2P_DIV_20 + * @arg @ref LL_RCC_PLLSAI2P_DIV_21 + * @arg @ref LL_RCC_PLLSAI2P_DIV_22 + * @arg @ref LL_RCC_PLLSAI2P_DIV_23 + * @arg @ref LL_RCC_PLLSAI2P_DIV_24 + * @arg @ref LL_RCC_PLLSAI2P_DIV_25 + * @arg @ref LL_RCC_PLLSAI2P_DIV_26 + * @arg @ref LL_RCC_PLLSAI2P_DIV_27 + * @arg @ref LL_RCC_PLLSAI2P_DIV_28 + * @arg @ref LL_RCC_PLLSAI2P_DIV_29 + * @arg @ref LL_RCC_PLLSAI2P_DIV_30 + * @arg @ref LL_RCC_PLLSAI2P_DIV_31 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM); + MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2PDIV, PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos | PLLP); +} +#else +/** + * @brief Configure PLLSAI2 used for SAI domain clock + * @note PLL Source and PLLM Divider can be written only when PLL, + * PLLSAI2 and PLLSAI2 are disabled. + * @note PLLSAI2N/PLLSAI2P can be written only when PLLSAI2 is disabled. + * @note This can be selected for SAI1 or SAI2 + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_SAI\n + * PLLCFGR PLLM LL_RCC_PLLSAI2_ConfigDomain_SAI\n + * PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_SAI\n + * PLLSAI2CFGR PLLSAI2P LL_RCC_PLLSAI2_ConfigDomain_SAI + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_NONE + * @arg @ref LL_RCC_PLLSOURCE_MSI + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_1 + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @param PLLN Between 8 and 86 + * @param PLLP This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI2P_DIV_7 + * @arg @ref LL_RCC_PLLSAI2P_DIV_17 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM); + MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P, PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos | PLLP); +} +#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT && RCC_PLLSAI2P_DIV_2_31_SUPPORT */ + +#if defined(DSI) +/** + * @brief Configure PLLSAI2 used for DSI domain clock + * @note PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled. + * @note PLLSAI2M/PLLSAI2N/PLLSAI2Q can be written only when PLLSAI2 is disabled. + * @note This can be selected for DSI + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_DSI\n + * PLLSAI2CFGR PLLSAI2M LL_RCC_PLLSAI2_ConfigDomain_DSI\n + * PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_DSI\n + * PLLSAI2CFGR PLLSAI2Q LL_RCC_PLLSAI2_ConfigDomain_DSI + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_NONE + * @arg @ref LL_RCC_PLLSOURCE_MSI + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI2M_DIV_1 + * @arg @ref LL_RCC_PLLSAI2M_DIV_2 + * @arg @ref LL_RCC_PLLSAI2M_DIV_3 + * @arg @ref LL_RCC_PLLSAI2M_DIV_4 + * @arg @ref LL_RCC_PLLSAI2M_DIV_5 + * @arg @ref LL_RCC_PLLSAI2M_DIV_6 + * @arg @ref LL_RCC_PLLSAI2M_DIV_7 + * @arg @ref LL_RCC_PLLSAI2M_DIV_8 + * @arg @ref LL_RCC_PLLSAI2M_DIV_9 + * @arg @ref LL_RCC_PLLSAI2M_DIV_10 + * @arg @ref LL_RCC_PLLSAI2M_DIV_11 + * @arg @ref LL_RCC_PLLSAI2M_DIV_12 + * @arg @ref LL_RCC_PLLSAI2M_DIV_13 + * @arg @ref LL_RCC_PLLSAI2M_DIV_14 + * @arg @ref LL_RCC_PLLSAI2M_DIV_15 + * @arg @ref LL_RCC_PLLSAI2M_DIV_16 + * @param PLLN Between 8 and 127 + * @param PLLQ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI2Q_DIV_2 + * @arg @ref LL_RCC_PLLSAI2Q_DIV_4 + * @arg @ref LL_RCC_PLLSAI2Q_DIV_6 + * @arg @ref LL_RCC_PLLSAI2Q_DIV_8 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_DSI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source); + MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M | RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2Q, + (PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | PLLQ | PLLM); +} +#endif /* DSI */ + +#if defined(LTDC) +/** + * @brief Configure PLLSAI2 used for LTDC domain clock + * @note PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled. + * @note PLLSAI2M/PLLSAI2N/PLLSAI2R can be written only when PLLSAI2 is disabled. + * @note This can be selected for LTDC + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_LTDC\n + * PLLSAI2CFGR PLLSAI2M LL_RCC_PLLSAI2_ConfigDomain_LTDC\n + * PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_LTDC\n + * PLLSAI2CFGR PLLSAI2R LL_RCC_PLLSAI2_ConfigDomain_LTDC\n + * CCIPR2 PLLSAI2DIVR LL_RCC_PLLSAI2_ConfigDomain_LTDC + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_NONE + * @arg @ref LL_RCC_PLLSOURCE_MSI + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI2M_DIV_1 + * @arg @ref LL_RCC_PLLSAI2M_DIV_2 + * @arg @ref LL_RCC_PLLSAI2M_DIV_3 + * @arg @ref LL_RCC_PLLSAI2M_DIV_4 + * @arg @ref LL_RCC_PLLSAI2M_DIV_5 + * @arg @ref LL_RCC_PLLSAI2M_DIV_6 + * @arg @ref LL_RCC_PLLSAI2M_DIV_7 + * @arg @ref LL_RCC_PLLSAI2M_DIV_8 + * @arg @ref LL_RCC_PLLSAI2M_DIV_9 + * @arg @ref LL_RCC_PLLSAI2M_DIV_10 + * @arg @ref LL_RCC_PLLSAI2M_DIV_11 + * @arg @ref LL_RCC_PLLSAI2M_DIV_12 + * @arg @ref LL_RCC_PLLSAI2M_DIV_13 + * @arg @ref LL_RCC_PLLSAI2M_DIV_14 + * @arg @ref LL_RCC_PLLSAI2M_DIV_15 + * @arg @ref LL_RCC_PLLSAI2M_DIV_16 + * @param PLLN Between 8 and 127 + * @param PLLR This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI2R_DIV_2 + * @arg @ref LL_RCC_PLLSAI2R_DIV_4 + * @arg @ref LL_RCC_PLLSAI2R_DIV_6 + * @arg @ref LL_RCC_PLLSAI2R_DIV_8 + * @param PLLDIVR This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_2 + * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_4 + * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_8 + * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_LTDC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR, uint32_t PLLDIVR) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source); + MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M | RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2R, + (PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | PLLR | PLLM); + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_PLLSAI2DIVR, PLLDIVR); +} +#else +/** + * @brief Configure PLLSAI2 used for ADC domain clock + * @note PLL Source and PLLM Divider can be written only when PLL, + * PLLSAI2 and PLLSAI2 are disabled. + * @note PLLSAI2N/PLLSAI2R can be written only when PLLSAI2 is disabled. + * @note This can be selected for ADC + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_ADC\n + * PLLCFGR PLLM LL_RCC_PLLSAI2_ConfigDomain_ADC\n + * PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_ADC\n + * PLLSAI2CFGR PLLSAI2R LL_RCC_PLLSAI2_ConfigDomain_ADC + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_NONE + * @arg @ref LL_RCC_PLLSOURCE_MSI + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_1 + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @param PLLN Between 8 and 86 + * @param PLLR This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI2R_DIV_2 + * @arg @ref LL_RCC_PLLSAI2R_DIV_4 + * @arg @ref LL_RCC_PLLSAI2R_DIV_6 + * @arg @ref LL_RCC_PLLSAI2R_DIV_8 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM); + MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2R, PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos | PLLR); +} +#endif /* LTDC */ + +/** + * @brief Get SAI2PLL multiplication factor for VCO + * @rmtoll PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_GetN + * @retval Between 8 and 86 or 127 depending on devices + */ +__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetN(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> RCC_PLLSAI2CFGR_PLLSAI2N_Pos); +} + +#if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) +/** + * @brief Get SAI2PLL division factor for PLLSAI2P + * @note Used for PLLSAI2CLK (SAI1 or SAI2 clock). + * @rmtoll PLLSAI2CFGR PLLSAI2PDIV LL_RCC_PLLSAI2_GetP + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLSAI2P_DIV_2 + * @arg @ref LL_RCC_PLLSAI2P_DIV_3 + * @arg @ref LL_RCC_PLLSAI2P_DIV_4 + * @arg @ref LL_RCC_PLLSAI2P_DIV_5 + * @arg @ref LL_RCC_PLLSAI2P_DIV_6 + * @arg @ref LL_RCC_PLLSAI2P_DIV_7 + * @arg @ref LL_RCC_PLLSAI2P_DIV_8 + * @arg @ref LL_RCC_PLLSAI2P_DIV_9 + * @arg @ref LL_RCC_PLLSAI2P_DIV_10 + * @arg @ref LL_RCC_PLLSAI2P_DIV_11 + * @arg @ref LL_RCC_PLLSAI2P_DIV_12 + * @arg @ref LL_RCC_PLLSAI2P_DIV_13 + * @arg @ref LL_RCC_PLLSAI2P_DIV_14 + * @arg @ref LL_RCC_PLLSAI2P_DIV_15 + * @arg @ref LL_RCC_PLLSAI2P_DIV_16 + * @arg @ref LL_RCC_PLLSAI2P_DIV_17 + * @arg @ref LL_RCC_PLLSAI2P_DIV_18 + * @arg @ref LL_RCC_PLLSAI2P_DIV_19 + * @arg @ref LL_RCC_PLLSAI2P_DIV_20 + * @arg @ref LL_RCC_PLLSAI2P_DIV_21 + * @arg @ref LL_RCC_PLLSAI2P_DIV_22 + * @arg @ref LL_RCC_PLLSAI2P_DIV_23 + * @arg @ref LL_RCC_PLLSAI2P_DIV_24 + * @arg @ref LL_RCC_PLLSAI2P_DIV_25 + * @arg @ref LL_RCC_PLLSAI2P_DIV_26 + * @arg @ref LL_RCC_PLLSAI2P_DIV_27 + * @arg @ref LL_RCC_PLLSAI2P_DIV_28 + * @arg @ref LL_RCC_PLLSAI2P_DIV_29 + * @arg @ref LL_RCC_PLLSAI2P_DIV_30 + * @arg @ref LL_RCC_PLLSAI2P_DIV_31 + */ +__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetP(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PDIV)); +} +#else +/** + * @brief Get SAI2PLL division factor for PLLSAI2P + * @note Used for PLLSAI2CLK (SAI1 or SAI2 clock). + * @rmtoll PLLSAI2CFGR PLLSAI2P LL_RCC_PLLSAI2_GetP + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLSAI2P_DIV_7 + * @arg @ref LL_RCC_PLLSAI2P_DIV_17 + */ +__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetP(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P)); +} +#endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */ + +#if defined(RCC_PLLSAI2Q_DIV_SUPPORT) +/** + * @brief Get division factor for PLLSAI2Q + * @note Used for PLLDSICLK (DSI clock) + * @rmtoll PLLSAI2CFGR PLLSAI2Q LL_RCC_PLLSAI2_GetQ + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLSAI2Q_DIV_2 + * @arg @ref LL_RCC_PLLSAI2Q_DIV_4 + * @arg @ref LL_RCC_PLLSAI2Q_DIV_6 + * @arg @ref LL_RCC_PLLSAI2Q_DIV_8 + */ +__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetQ(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2Q)); +} +#endif /* RCC_PLLSAI2Q_DIV_SUPPORT */ + +/** + * @brief Get SAI2PLL division factor for PLLSAI2R + * @note Used for PLLADC2CLK (ADC clock) or PLLLCDCLK (LTDC clock) depending on devices + * @rmtoll PLLSAI2CFGR PLLSAI2R LL_RCC_PLLSAI2_GetR + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLSAI2R_DIV_2 + * @arg @ref LL_RCC_PLLSAI2R_DIV_4 + * @arg @ref LL_RCC_PLLSAI2R_DIV_6 + * @arg @ref LL_RCC_PLLSAI2R_DIV_8 + */ +__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetR(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R)); +} + +#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) +/** + * @brief Get Division factor for the PLLSAI2 + * @rmtoll PLLSAI2CFGR PLLSAI2M LL_RCC_PLLSAI2_GetDivider + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLSAI2M_DIV_1 + * @arg @ref LL_RCC_PLLSAI2M_DIV_2 + * @arg @ref LL_RCC_PLLSAI2M_DIV_3 + * @arg @ref LL_RCC_PLLSAI2M_DIV_4 + * @arg @ref LL_RCC_PLLSAI2M_DIV_5 + * @arg @ref LL_RCC_PLLSAI2M_DIV_6 + * @arg @ref LL_RCC_PLLSAI2M_DIV_7 + * @arg @ref LL_RCC_PLLSAI2M_DIV_8 + * @arg @ref LL_RCC_PLLSAI2M_DIV_9 + * @arg @ref LL_RCC_PLLSAI2M_DIV_10 + * @arg @ref LL_RCC_PLLSAI2M_DIV_11 + * @arg @ref LL_RCC_PLLSAI2M_DIV_12 + * @arg @ref LL_RCC_PLLSAI2M_DIV_13 + * @arg @ref LL_RCC_PLLSAI2M_DIV_14 + * @arg @ref LL_RCC_PLLSAI2M_DIV_15 + * @arg @ref LL_RCC_PLLSAI2M_DIV_16 + */ +__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetDivider(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M)); +} +#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */ + +#if defined(RCC_CCIPR2_PLLSAI2DIVR) +/** + * @brief Get PLLSAI2 division factor for PLLSAI2DIVR + * @note Used for LTDC domain clock + * @rmtoll CCIPR2 PLLSAI2DIVR LL_RCC_PLLSAI2_GetDIVR + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_2 + * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_4 + * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_8 + * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_16 + */ +__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetDIVR(void) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_PLLSAI2DIVR)); +} +#endif /* RCC_CCIPR2_PLLSAI2DIVR */ + +/** + * @brief Enable PLLSAI2 output mapped on SAI domain clock + * @rmtoll PLLSAI2CFGR PLLSAI2PEN LL_RCC_PLLSAI2_EnableDomain_SAI + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLSAI2_EnableDomain_SAI(void) +{ + SET_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PEN); +} + +/** + * @brief Disable PLLSAI2 output mapped on SAI domain clock + * @note In order to save power, when of the PLLSAI2 is + * not used, should be 0 + * @rmtoll PLLSAI2CFGR PLLSAI2PEN LL_RCC_PLLSAI2_DisableDomain_SAI + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_SAI(void) +{ + CLEAR_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PEN); +} + +/** + * @brief Check if PLLSAI2 output mapped on SAI domain clock is enabled + * @rmtoll PLLSAI2CFGR PLLSAI2PEN LL_RCC_PLLSAI2_IsEnabledDomain_SAI + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_IsEnabledDomain_SAI(void) +{ + return ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PEN) == (RCC_PLLSAI2CFGR_PLLSAI2PEN)) ? 1UL : 0UL); +} + +#if defined(DSI) +/** + * @brief Enable PLLSAI2 output mapped on DSI domain clock + * @rmtoll PLLSAI2CFGR PLLSAI2QEN LL_RCC_PLLSAI2_EnableDomain_DSI + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLSAI2_EnableDomain_DSI(void) +{ + SET_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2QEN); +} + +/** + * @brief Disable PLLSAI2 output mapped on DSI domain clock + * @note In order to save power, when of the PLLSAI2 is + * not used, Main PLLSAI2 should be 0 + * @rmtoll PLLSAI2CFGR PLLSAI2QEN LL_RCC_PLLSAI2_DisableDomain_DSI + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_DSI(void) +{ + CLEAR_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2QEN); +} + +/** + * @brief Check if PLLSAI2 output mapped on DSI domain clock is enabled + * @rmtoll PLLSAI2CFGR PLLSAI2QEN LL_RCC_PLLSAI2_IsEnabledDomain_DSI + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_IsEnabledDomain_DSI(void) +{ + return ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2QEN) == (RCC_PLLSAI2CFGR_PLLSAI2QEN)) ? 1UL : 0UL); +} +#endif /* DSI */ + +#if defined(LTDC) +/** + * @brief Enable PLLSAI2 output mapped on LTDC domain clock + * @rmtoll PLLSAI2CFGR PLLSAI2REN LL_RCC_PLLSAI2_EnableDomain_LTDC + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLSAI2_EnableDomain_LTDC(void) +{ + SET_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN); +} + +/** + * @brief Disable PLLSAI2 output mapped on LTDC domain clock + * @note In order to save power, when of the PLLSAI2 is + * not used, Main PLLSAI2 should be 0 + * @rmtoll PLLSAI2CFGR PLLSAI2REN LL_RCC_PLLSAI2_DisableDomain_LTDC + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_LTDC(void) +{ + CLEAR_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN); +} + +/** + * @brief Check if PLLSAI2 output mapped on LTDC domain clock is enabled + * @rmtoll PLLSAI2CFGR PLLSAI2REN LL_RCC_PLLSAI2_IsEnabledDomain_LTDC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_IsEnabledDomain_LTDC(void) +{ + return ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN) == (RCC_PLLSAI2CFGR_PLLSAI2REN)) ? 1UL : 0UL); +} +#else +/** + * @brief Enable PLLSAI2 output mapped on ADC domain clock + * @rmtoll PLLSAI2CFGR PLLSAI2REN LL_RCC_PLLSAI2_EnableDomain_ADC + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLSAI2_EnableDomain_ADC(void) +{ + SET_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN); +} + +/** + * @brief Disable PLLSAI2 output mapped on ADC domain clock + * @note In order to save power, when of the PLLSAI2 is + * not used, Main PLLSAI2 should be 0 + * @rmtoll PLLSAI2CFGR PLLSAI2REN LL_RCC_PLLSAI2_DisableDomain_ADC + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_ADC(void) +{ + CLEAR_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN); +} + +/** + * @brief Check if PLLSAI2 output mapped on ADC domain clock is enabled + * @rmtoll PLLSAI2CFGR PLLSAI2REN LL_RCC_PLLSAI2_IsEnabledDomain_ADC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_IsEnabledDomain_ADC(void) +{ + return ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN) == (RCC_PLLSAI2CFGR_PLLSAI2REN)) ? 1UL : 0UL); +} +#endif /* LTDC */ + +/** + * @} + */ +#endif /* RCC_PLLSAI2_SUPPORT */ + +#if defined(OCTOSPI1) +/** @defgroup RCC_LL_EF_OCTOSPI OCTOSPI + * @{ + */ + +/** + * @brief Configure OCTOSPI1 DQS delay + * @rmtoll DLYCFGR OCTOSPI1_DLY LL_RCC_OCTOSPI1_DelayConfig + * @param Delay OCTOSPI1 DQS delay between 0 and 15 + * @retval None + */ +__STATIC_INLINE void LL_RCC_OCTOSPI1_DelayConfig(uint32_t Delay) +{ + MODIFY_REG(RCC->DLYCFGR, RCC_DLYCFGR_OCTOSPI1_DLY, Delay); +} + +#if defined(OCTOSPI2) +/** + * @brief Configure OCTOSPI2 DQS delay + * @rmtoll DLYCFGR OCTOSPI2_DLY LL_RCC_OCTOSPI2_DelayConfig + * @param Delay OCTOSPI2 DQS delay between 0 and 15 + * @retval None + */ +__STATIC_INLINE void LL_RCC_OCTOSPI2_DelayConfig(uint32_t Delay) +{ + MODIFY_REG(RCC->DLYCFGR, RCC_DLYCFGR_OCTOSPI2_DLY, (Delay << RCC_DLYCFGR_OCTOSPI2_DLY_Pos)); +} +#endif /* OCTOSPI2 */ + +/** + * @} + */ +#endif /* OCTOSPI1 */ + +/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management + * @{ + */ + +/** + * @brief Clear LSI ready interrupt flag + * @rmtoll CICR LSIRDYC LL_RCC_ClearFlag_LSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC); +} + +/** + * @brief Clear LSE ready interrupt flag + * @rmtoll CICR LSERDYC LL_RCC_ClearFlag_LSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_LSERDYC); +} + +/** + * @brief Clear MSI ready interrupt flag + * @rmtoll CICR MSIRDYC LL_RCC_ClearFlag_MSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_MSIRDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_MSIRDYC); +} + +/** + * @brief Clear HSI ready interrupt flag + * @rmtoll CICR HSIRDYC LL_RCC_ClearFlag_HSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_HSIRDYC); +} + +/** + * @brief Clear HSE ready interrupt flag + * @rmtoll CICR HSERDYC LL_RCC_ClearFlag_HSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_HSERDYC); +} + +/** + * @brief Clear PLL ready interrupt flag + * @rmtoll CICR PLLRDYC LL_RCC_ClearFlag_PLLRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_PLLRDYC); +} + +#if defined(RCC_HSI48_SUPPORT) +/** + * @brief Clear HSI48 ready interrupt flag + * @rmtoll CICR HSI48RDYC LL_RCC_ClearFlag_HSI48RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_HSI48RDYC); +} +#endif /* RCC_HSI48_SUPPORT */ + +#if defined(RCC_PLLSAI1_SUPPORT) +/** + * @brief Clear PLLSAI1 ready interrupt flag + * @rmtoll CICR PLLSAI1RDYC LL_RCC_ClearFlag_PLLSAI1RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_PLLSAI1RDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_PLLSAI1RDYC); +} +#endif /* RCC_PLLSAI1_SUPPORT */ + +#if defined(RCC_PLLSAI2_SUPPORT) +/** + * @brief Clear PLLSAI1 ready interrupt flag + * @rmtoll CICR PLLSAI2RDYC LL_RCC_ClearFlag_PLLSAI2RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_PLLSAI2RDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_PLLSAI2RDYC); +} +#endif /* RCC_PLLSAI2_SUPPORT */ + +/** + * @brief Clear Clock security system interrupt flag + * @rmtoll CICR CSSC LL_RCC_ClearFlag_HSECSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_CSSC); +} + +/** + * @brief Clear LSE Clock security system interrupt flag + * @rmtoll CICR LSECSSC LL_RCC_ClearFlag_LSECSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_LSECSSC); +} + +/** + * @brief Check if LSI ready interrupt occurred or not + * @rmtoll CIFR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == RCC_CIFR_LSIRDYF) ? 1UL : 0UL); +} + +/** + * @brief Check if LSE ready interrupt occurred or not + * @rmtoll CIFR LSERDYF LL_RCC_IsActiveFlag_LSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == RCC_CIFR_LSERDYF) ? 1UL : 0UL); +} + +/** + * @brief Check if MSI ready interrupt occurred or not + * @rmtoll CIFR MSIRDYF LL_RCC_IsActiveFlag_MSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_MSIRDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_MSIRDYF) == RCC_CIFR_MSIRDYF) ? 1UL : 0UL); +} + +/** + * @brief Check if HSI ready interrupt occurred or not + * @rmtoll CIFR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == RCC_CIFR_HSIRDYF) ? 1UL : 0UL); +} + +/** + * @brief Check if HSE ready interrupt occurred or not + * @rmtoll CIFR HSERDYF LL_RCC_IsActiveFlag_HSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == RCC_CIFR_HSERDYF) ? 1UL : 0UL); +} + +/** + * @brief Check if PLL ready interrupt occurred or not + * @rmtoll CIFR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLLRDYF) == RCC_CIFR_PLLRDYF) ? 1UL : 0UL); +} + +#if defined(RCC_HSI48_SUPPORT) +/** + * @brief Check if HSI48 ready interrupt occurred or not + * @rmtoll CIR HSI48RDYF LL_RCC_IsActiveFlag_HSI48RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSI48RDYF) == RCC_CIFR_HSI48RDYF) ? 1UL : 0UL); +} +#endif /* RCC_HSI48_SUPPORT */ + +#if defined(RCC_PLLSAI1_SUPPORT) +/** + * @brief Check if PLLSAI1 ready interrupt occurred or not + * @rmtoll CIFR PLLSAI1RDYF LL_RCC_IsActiveFlag_PLLSAI1RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAI1RDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI1RDYF) == RCC_CIFR_PLLSAI1RDYF) ? 1UL : 0UL); +} +#endif /* RCC_PLLSAI1_SUPPORT */ + +#if defined(RCC_PLLSAI2_SUPPORT) +/** + * @brief Check if PLLSAI1 ready interrupt occurred or not + * @rmtoll CIFR PLLSAI2RDYF LL_RCC_IsActiveFlag_PLLSAI2RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAI2RDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI2RDYF) == RCC_CIFR_PLLSAI2RDYF) ? 1UL : 0UL); +} +#endif /* RCC_PLLSAI2_SUPPORT */ + +/** + * @brief Check if Clock security system interrupt occurred or not + * @rmtoll CIFR CSSF LL_RCC_IsActiveFlag_HSECSS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_CSSF) == RCC_CIFR_CSSF) ? 1UL : 0UL); +} + +/** + * @brief Check if LSE Clock security system interrupt occurred or not + * @rmtoll CIFR LSECSSF LL_RCC_IsActiveFlag_LSECSS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSECSSF) == RCC_CIFR_LSECSSF) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag FW reset is set or not. + * @rmtoll CSR FWRSTF LL_RCC_IsActiveFlag_FWRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_FWRST(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_FWRSTF) == RCC_CSR_FWRSTF) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag Independent Watchdog reset is set or not. + * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == RCC_CSR_IWDGRSTF) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag Low Power reset is set or not. + * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == RCC_CSR_LPWRRSTF) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag is set or not. + * @rmtoll CSR OBLRSTF LL_RCC_IsActiveFlag_OBLRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == RCC_CSR_OBLRSTF) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag Pin reset is set or not. + * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == RCC_CSR_PINRSTF) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag Software reset is set or not. + * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == RCC_CSR_SFTRSTF) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag Window Watchdog reset is set or not. + * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == RCC_CSR_WWDGRSTF) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag BOR reset is set or not. + * @rmtoll CSR BORRSTF LL_RCC_IsActiveFlag_BORRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == RCC_CSR_BORRSTF) ? 1UL : 0UL); +} + +/** + * @brief Set RMVF bit to clear the reset flags. + * @rmtoll CSR RMVF LL_RCC_ClearResetFlags + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearResetFlags(void) +{ + SET_BIT(RCC->CSR, RCC_CSR_RMVF); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_IT_Management IT Management + * @{ + */ + +/** + * @brief Enable LSI ready interrupt + * @rmtoll CIER LSIRDYIE LL_RCC_EnableIT_LSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_LSIRDYIE); +} + +/** + * @brief Enable LSE ready interrupt + * @rmtoll CIER LSERDYIE LL_RCC_EnableIT_LSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE); +} + +/** + * @brief Enable MSI ready interrupt + * @rmtoll CIER MSIRDYIE LL_RCC_EnableIT_MSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_MSIRDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_MSIRDYIE); +} + +/** + * @brief Enable HSI ready interrupt + * @rmtoll CIER HSIRDYIE LL_RCC_EnableIT_HSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE); +} + +/** + * @brief Enable HSE ready interrupt + * @rmtoll CIER HSERDYIE LL_RCC_EnableIT_HSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE); +} + +/** + * @brief Enable PLL ready interrupt + * @rmtoll CIER PLLRDYIE LL_RCC_EnableIT_PLLRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_PLLRDYIE); +} + +#if defined(RCC_HSI48_SUPPORT) +/** + * @brief Enable HSI48 ready interrupt + * @rmtoll CIER HSI48RDYIE LL_RCC_EnableIT_HSI48RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE); +} +#endif /* RCC_HSI48_SUPPORT */ + +#if defined(RCC_PLLSAI1_SUPPORT) +/** + * @brief Enable PLLSAI1 ready interrupt + * @rmtoll CIER PLLSAI1RDYIE LL_RCC_EnableIT_PLLSAI1RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_PLLSAI1RDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE); +} +#endif /* RCC_PLLSAI1_SUPPORT */ + +#if defined(RCC_PLLSAI2_SUPPORT) +/** + * @brief Enable PLLSAI2 ready interrupt + * @rmtoll CIER PLLSAI2RDYIE LL_RCC_EnableIT_PLLSAI2RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_PLLSAI2RDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE); +} +#endif /* RCC_PLLSAI2_SUPPORT */ + +/** + * @brief Enable LSE clock security system interrupt + * @rmtoll CIER LSECSSIE LL_RCC_EnableIT_LSECSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_LSECSS(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_LSECSSIE); +} + +/** + * @brief Disable LSI ready interrupt + * @rmtoll CIER LSIRDYIE LL_RCC_DisableIT_LSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_LSIRDYIE); +} + +/** + * @brief Disable LSE ready interrupt + * @rmtoll CIER LSERDYIE LL_RCC_DisableIT_LSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE); +} + +/** + * @brief Disable MSI ready interrupt + * @rmtoll CIER MSIRDYIE LL_RCC_DisableIT_MSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_MSIRDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_MSIRDYIE); +} + +/** + * @brief Disable HSI ready interrupt + * @rmtoll CIER HSIRDYIE LL_RCC_DisableIT_HSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE); +} + +/** + * @brief Disable HSE ready interrupt + * @rmtoll CIER HSERDYIE LL_RCC_DisableIT_HSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE); +} + +/** + * @brief Disable PLL ready interrupt + * @rmtoll CIER PLLRDYIE LL_RCC_DisableIT_PLLRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_PLLRDYIE); +} + +#if defined(RCC_HSI48_SUPPORT) +/** + * @brief Disable HSI48 ready interrupt + * @rmtoll CIER HSI48RDYIE LL_RCC_DisableIT_HSI48RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE); +} +#endif /* RCC_HSI48_SUPPORT */ + +#if defined(RCC_PLLSAI1_SUPPORT) +/** + * @brief Disable PLLSAI1 ready interrupt + * @rmtoll CIER PLLSAI1RDYIE LL_RCC_DisableIT_PLLSAI1RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_PLLSAI1RDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE); +} +#endif /* RCC_PLLSAI1_SUPPORT */ + +#if defined(RCC_PLLSAI2_SUPPORT) +/** + * @brief Disable PLLSAI2 ready interrupt + * @rmtoll CIER PLLSAI2RDYIE LL_RCC_DisableIT_PLLSAI2RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_PLLSAI2RDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE); +} +#endif /* RCC_PLLSAI2_SUPPORT */ + +/** + * @brief Disable LSE clock security system interrupt + * @rmtoll CIER LSECSSIE LL_RCC_DisableIT_LSECSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_LSECSS(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_LSECSSIE); +} + +/** + * @brief Checks if LSI ready interrupt source is enabled or disabled. + * @rmtoll CIER LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == RCC_CIER_LSIRDYIE) ? 1UL : 0UL); +} + +/** + * @brief Checks if LSE ready interrupt source is enabled or disabled. + * @rmtoll CIER LSERDYIE LL_RCC_IsEnabledIT_LSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == RCC_CIER_LSERDYIE) ? 1UL : 0UL); +} + +/** + * @brief Checks if MSI ready interrupt source is enabled or disabled. + * @rmtoll CIER MSIRDYIE LL_RCC_IsEnabledIT_MSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_MSIRDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_MSIRDYIE) == RCC_CIER_MSIRDYIE) ? 1UL : 0UL); +} + +/** + * @brief Checks if HSI ready interrupt source is enabled or disabled. + * @rmtoll CIER HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == RCC_CIER_HSIRDYIE) ? 1UL : 0UL); +} + +/** + * @brief Checks if HSE ready interrupt source is enabled or disabled. + * @rmtoll CIER HSERDYIE LL_RCC_IsEnabledIT_HSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == RCC_CIER_HSERDYIE) ? 1UL : 0UL); +} + +/** + * @brief Checks if PLL ready interrupt source is enabled or disabled. + * @rmtoll CIER PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_PLLRDYIE) == RCC_CIER_PLLRDYIE) ? 1UL : 0UL); +} + +#if defined(RCC_HSI48_SUPPORT) +/** + * @brief Checks if HSI48 ready interrupt source is enabled or disabled. + * @rmtoll CIER HSI48RDYIE LL_RCC_IsEnabledIT_HSI48RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSI48RDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE) == RCC_CIER_HSI48RDYIE) ? 1UL : 0UL); +} +#endif /* RCC_HSI48_SUPPORT */ + +#if defined(RCC_PLLSAI1_SUPPORT) +/** + * @brief Checks if PLLSAI1 ready interrupt source is enabled or disabled. + * @rmtoll CIER PLLSAI1RDYIE LL_RCC_IsEnabledIT_PLLSAI1RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAI1RDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE) == RCC_CIER_PLLSAI1RDYIE) ? 1UL : 0UL); +} +#endif /* RCC_PLLSAI1_SUPPORT */ + +#if defined(RCC_PLLSAI2_SUPPORT) +/** + * @brief Checks if PLLSAI2 ready interrupt source is enabled or disabled. + * @rmtoll CIER PLLSAI2RDYIE LL_RCC_IsEnabledIT_PLLSAI2RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAI2RDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE) == RCC_CIER_PLLSAI2RDYIE) ? 1UL : 0UL); +} +#endif /* RCC_PLLSAI2_SUPPORT */ + +/** + * @brief Checks if LSECSS interrupt source is enabled or disabled. + * @rmtoll CIER LSECSSIE LL_RCC_IsEnabledIT_LSECSS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSECSS(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_LSECSSIE) == RCC_CIER_LSECSSIE) ? 1UL : 0UL); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_EF_Init De-initialization function + * @{ + */ +ErrorStatus LL_RCC_DeInit(void); +/** + * @} + */ + +/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions + * @{ + */ +void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks); +uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource); +#if defined(UART4) || defined(UART5) +uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource); +#endif /* UART4 || UART5 */ +uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource); +uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource); +uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource); +#if defined(SAI1) +uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource); +#endif /* SAI1 */ +#if defined(SDMMC1) +#if defined(RCC_CCIPR2_SDMMCSEL) +uint32_t LL_RCC_GetSDMMCKernelClockFreq(uint32_t SDMMCxSource); +#endif +uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource); +#endif /* SDMMC1 */ +uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource); +#if defined(USB_OTG_FS) || defined(USB) +uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource); +#endif /* USB_OTG_FS || USB */ +uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource); +#if defined(SWPMI1) +uint32_t LL_RCC_GetSWPMIClockFreq(uint32_t SWPMIxSource); +#endif /* SWPMI1 */ +#if defined(DFSDM1_Channel0) +uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource); +#if defined(RCC_CCIPR2_DFSDM1SEL) +uint32_t LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource); +#endif /* RCC_CCIPR2_DFSDM1SEL */ +#endif /* DFSDM1_Channel0 */ +#if defined(LTDC) +uint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource); +#endif /* LTDC */ +#if defined(DSI) +uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource); +#endif /* DSI */ +#if defined(OCTOSPI1) +uint32_t LL_RCC_GetOCTOSPIClockFreq(uint32_t OCTOSPIxSource); +#endif /* OCTOSPI1 */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(RCC) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32L4xx_LL_RCC_H */ + diff --git a/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_system.h b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_system.h new file mode 100644 index 0000000..94b722b --- /dev/null +++ b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_system.h @@ -0,0 +1,1627 @@ +/** + ****************************************************************************** + * @file stm32l4xx_ll_system.h + * @author MCD Application Team + * @brief Header file of SYSTEM LL module. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The LL SYSTEM driver contains a set of generic APIs that can be + used by user: + (+) Some of the FLASH features need to be handled in the SYSTEM file. + (+) Access to DBGCMU registers + (+) Access to SYSCFG registers + (+) Access to VREFBUF registers + + @endverbatim + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32L4xx_LL_SYSTEM_H +#define STM32L4xx_LL_SYSTEM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx.h" + +/** @addtogroup STM32L4xx_LL_Driver + * @{ + */ + +#if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) || defined (VREFBUF) + +/** @defgroup SYSTEM_LL SYSTEM + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants + * @{ + */ + +/** + * @brief Power-down in Run mode Flash key + */ +#define FLASH_PDKEY1 0x04152637U /*!< Flash power down key1 */ +#define FLASH_PDKEY2 0xFAFBFCFDU /*!< Flash power down key2: used with FLASH_PDKEY1 + to unlock the RUN_PD bit in FLASH_ACR */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants + * @{ + */ + +/** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP +* @{ +*/ +#define LL_SYSCFG_REMAP_FLASH 0x00000000U /*!< Main Flash memory mapped at 0x00000000 */ +#define LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_MEMRMP_MEM_MODE_0 /*!< System Flash memory mapped at 0x00000000 */ +#define LL_SYSCFG_REMAP_SRAM (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0) /*!< SRAM1 mapped at 0x00000000 */ +#if defined(FMC_Bank1_R) +#define LL_SYSCFG_REMAP_FMC SYSCFG_MEMRMP_MEM_MODE_1 /*!< FMC bank 1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 */ +#endif /* FMC_Bank1_R */ +#define LL_SYSCFG_REMAP_QUADSPI (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_1) /*!< QUADSPI memory mapped at 0x00000000 */ +/** + * @} + */ + +#if defined(SYSCFG_MEMRMP_FB_MODE) +/** @defgroup SYSTEM_LL_EC_BANKMODE SYSCFG BANK MODE + * @{ + */ +#define LL_SYSCFG_BANKMODE_BANK1 0x00000000U /*!< Flash Bank1 mapped at 0x08000000 (and aliased @0x00000000) + and Flash Bank2 mapped at 0x08080000 (and aliased at 0x00080000) */ +#define LL_SYSCFG_BANKMODE_BANK2 SYSCFG_MEMRMP_FB_MODE /*!< Flash Bank2 mapped at 0x08000000 (and aliased @0x00000000) + and Flash Bank1 mapped at 0x08080000 (and aliased at 0x00080000) */ +/** + * @} + */ + +#endif /* SYSCFG_MEMRMP_FB_MODE */ +/** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS + * @{ + */ +#define LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */ +#define LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */ +#if defined(SYSCFG_CFGR1_I2C_PB8_FMP) +#define LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */ +#endif /* SYSCFG_CFGR1_I2C_PB8_FMP */ +#if defined(SYSCFG_CFGR1_I2C_PB9_FMP) +#define LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */ +#endif /* SYSCFG_CFGR1_I2C_PB9_FMP */ +#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */ +#if defined(I2C2) +#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */ +#endif /* I2C2 */ +#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */ +#if defined(I2C4) +#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 SYSCFG_CFGR1_I2C4_FMP /*!< Enable Fast Mode Plus on I2C4 pins */ +#endif /* I2C4 */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT + * @{ + */ +#define LL_SYSCFG_EXTI_PORTA 0U /*!< EXTI PORT A */ +#define LL_SYSCFG_EXTI_PORTB 1U /*!< EXTI PORT B */ +#define LL_SYSCFG_EXTI_PORTC 2U /*!< EXTI PORT C */ +#define LL_SYSCFG_EXTI_PORTD 3U /*!< EXTI PORT D */ +#define LL_SYSCFG_EXTI_PORTE 4U /*!< EXTI PORT E */ +#if defined(GPIOF) +#define LL_SYSCFG_EXTI_PORTF 5U /*!< EXTI PORT F */ +#endif /* GPIOF */ +#if defined(GPIOG) +#define LL_SYSCFG_EXTI_PORTG 6U /*!< EXTI PORT G */ +#endif /* GPIOG */ +#define LL_SYSCFG_EXTI_PORTH 7U /*!< EXTI PORT H */ +#if defined(GPIOI) +#define LL_SYSCFG_EXTI_PORTI 8U /*!< EXTI PORT I */ +#endif /* GPIOI */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE + * @{ + */ +#define LL_SYSCFG_EXTI_LINE0 (uint32_t)(0x000FU << 16U | 0U) /* !< EXTI_POSITION_0 | EXTICR[0] */ +#define LL_SYSCFG_EXTI_LINE1 (uint32_t)(0x00F0U << 16U | 0U) /* !< EXTI_POSITION_4 | EXTICR[0] */ +#define LL_SYSCFG_EXTI_LINE2 (uint32_t)(0x0F00U << 16U | 0U) /* !< EXTI_POSITION_8 | EXTICR[0] */ +#define LL_SYSCFG_EXTI_LINE3 (uint32_t)(0xF000U << 16U | 0U) /* !< EXTI_POSITION_12 | EXTICR[0] */ +#define LL_SYSCFG_EXTI_LINE4 (uint32_t)(0x000FU << 16U | 1U) /* !< EXTI_POSITION_0 | EXTICR[1] */ +#define LL_SYSCFG_EXTI_LINE5 (uint32_t)(0x00F0U << 16U | 1U) /* !< EXTI_POSITION_4 | EXTICR[1] */ +#define LL_SYSCFG_EXTI_LINE6 (uint32_t)(0x0F00U << 16U | 1U) /* !< EXTI_POSITION_8 | EXTICR[1] */ +#define LL_SYSCFG_EXTI_LINE7 (uint32_t)(0xF000U << 16U | 1U) /* !< EXTI_POSITION_12 | EXTICR[1] */ +#define LL_SYSCFG_EXTI_LINE8 (uint32_t)(0x000FU << 16U | 2U) /* !< EXTI_POSITION_0 | EXTICR[2] */ +#define LL_SYSCFG_EXTI_LINE9 (uint32_t)(0x00F0U << 16U | 2U) /* !< EXTI_POSITION_4 | EXTICR[2] */ +#define LL_SYSCFG_EXTI_LINE10 (uint32_t)(0x0F00U << 16U | 2U) /* !< EXTI_POSITION_8 | EXTICR[2] */ +#define LL_SYSCFG_EXTI_LINE11 (uint32_t)(0xF000U << 16U | 2U) /* !< EXTI_POSITION_12 | EXTICR[2] */ +#define LL_SYSCFG_EXTI_LINE12 (uint32_t)(0x000FU << 16U | 3U) /* !< EXTI_POSITION_0 | EXTICR[3] */ +#define LL_SYSCFG_EXTI_LINE13 (uint32_t)(0x00F0U << 16U | 3U) /* !< EXTI_POSITION_4 | EXTICR[3] */ +#define LL_SYSCFG_EXTI_LINE14 (uint32_t)(0x0F00U << 16U | 3U) /* !< EXTI_POSITION_8 | EXTICR[3] */ +#define LL_SYSCFG_EXTI_LINE15 (uint32_t)(0xF000U << 16U | 3U) /* !< EXTI_POSITION_12 | EXTICR[3] */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK + * @{ + */ +#define LL_SYSCFG_TIMBREAK_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC error signal + with Break Input of TIM1/8/15/16/17 */ +#define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection + with TIM1/8/15/16/17 Break Input + and also the PVDE and PLS bits of the Power Control Interface */ +#define LL_SYSCFG_TIMBREAK_SRAM2_PARITY SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM2_PARITY error signal + with Break Input of TIM1/8/15/16/17 */ +#define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM4 + with Break Input of TIM1/15/16/17 */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_SRAM2WRP SYSCFG SRAM2 WRP + * @{ + */ +#define LL_SYSCFG_SRAM2WRP_PAGE0 SYSCFG_SWPR_PAGE0 /*!< SRAM2 Write protection page 0 */ +#define LL_SYSCFG_SRAM2WRP_PAGE1 SYSCFG_SWPR_PAGE1 /*!< SRAM2 Write protection page 1 */ +#define LL_SYSCFG_SRAM2WRP_PAGE2 SYSCFG_SWPR_PAGE2 /*!< SRAM2 Write protection page 2 */ +#define LL_SYSCFG_SRAM2WRP_PAGE3 SYSCFG_SWPR_PAGE3 /*!< SRAM2 Write protection page 3 */ +#define LL_SYSCFG_SRAM2WRP_PAGE4 SYSCFG_SWPR_PAGE4 /*!< SRAM2 Write protection page 4 */ +#define LL_SYSCFG_SRAM2WRP_PAGE5 SYSCFG_SWPR_PAGE5 /*!< SRAM2 Write protection page 5 */ +#define LL_SYSCFG_SRAM2WRP_PAGE6 SYSCFG_SWPR_PAGE6 /*!< SRAM2 Write protection page 6 */ +#define LL_SYSCFG_SRAM2WRP_PAGE7 SYSCFG_SWPR_PAGE7 /*!< SRAM2 Write protection page 7 */ +#define LL_SYSCFG_SRAM2WRP_PAGE8 SYSCFG_SWPR_PAGE8 /*!< SRAM2 Write protection page 8 */ +#define LL_SYSCFG_SRAM2WRP_PAGE9 SYSCFG_SWPR_PAGE9 /*!< SRAM2 Write protection page 9 */ +#define LL_SYSCFG_SRAM2WRP_PAGE10 SYSCFG_SWPR_PAGE10 /*!< SRAM2 Write protection page 10 */ +#define LL_SYSCFG_SRAM2WRP_PAGE11 SYSCFG_SWPR_PAGE11 /*!< SRAM2 Write protection page 11 */ +#define LL_SYSCFG_SRAM2WRP_PAGE12 SYSCFG_SWPR_PAGE12 /*!< SRAM2 Write protection page 12 */ +#define LL_SYSCFG_SRAM2WRP_PAGE13 SYSCFG_SWPR_PAGE13 /*!< SRAM2 Write protection page 13 */ +#define LL_SYSCFG_SRAM2WRP_PAGE14 SYSCFG_SWPR_PAGE14 /*!< SRAM2 Write protection page 14 */ +#define LL_SYSCFG_SRAM2WRP_PAGE15 SYSCFG_SWPR_PAGE15 /*!< SRAM2 Write protection page 15 */ +#if defined(SYSCFG_SWPR_PAGE31) +#define LL_SYSCFG_SRAM2WRP_PAGE16 SYSCFG_SWPR_PAGE16 /*!< SRAM2 Write protection page 16 */ +#define LL_SYSCFG_SRAM2WRP_PAGE17 SYSCFG_SWPR_PAGE17 /*!< SRAM2 Write protection page 17 */ +#define LL_SYSCFG_SRAM2WRP_PAGE18 SYSCFG_SWPR_PAGE18 /*!< SRAM2 Write protection page 18 */ +#define LL_SYSCFG_SRAM2WRP_PAGE19 SYSCFG_SWPR_PAGE19 /*!< SRAM2 Write protection page 19 */ +#define LL_SYSCFG_SRAM2WRP_PAGE20 SYSCFG_SWPR_PAGE20 /*!< SRAM2 Write protection page 20 */ +#define LL_SYSCFG_SRAM2WRP_PAGE21 SYSCFG_SWPR_PAGE21 /*!< SRAM2 Write protection page 21 */ +#define LL_SYSCFG_SRAM2WRP_PAGE22 SYSCFG_SWPR_PAGE22 /*!< SRAM2 Write protection page 22 */ +#define LL_SYSCFG_SRAM2WRP_PAGE23 SYSCFG_SWPR_PAGE23 /*!< SRAM2 Write protection page 23 */ +#define LL_SYSCFG_SRAM2WRP_PAGE24 SYSCFG_SWPR_PAGE24 /*!< SRAM2 Write protection page 24 */ +#define LL_SYSCFG_SRAM2WRP_PAGE25 SYSCFG_SWPR_PAGE25 /*!< SRAM2 Write protection page 25 */ +#define LL_SYSCFG_SRAM2WRP_PAGE26 SYSCFG_SWPR_PAGE26 /*!< SRAM2 Write protection page 26 */ +#define LL_SYSCFG_SRAM2WRP_PAGE27 SYSCFG_SWPR_PAGE27 /*!< SRAM2 Write protection page 27 */ +#define LL_SYSCFG_SRAM2WRP_PAGE28 SYSCFG_SWPR_PAGE28 /*!< SRAM2 Write protection page 28 */ +#define LL_SYSCFG_SRAM2WRP_PAGE29 SYSCFG_SWPR_PAGE29 /*!< SRAM2 Write protection page 29 */ +#define LL_SYSCFG_SRAM2WRP_PAGE30 SYSCFG_SWPR_PAGE30 /*!< SRAM2 Write protection page 30 */ +#define LL_SYSCFG_SRAM2WRP_PAGE31 SYSCFG_SWPR_PAGE31 /*!< SRAM2 Write protection page 31 */ +#endif /* SYSCFG_SWPR_PAGE31 */ +#if defined(SYSCFG_SWPR2_PAGE63) +#define LL_SYSCFG_SRAM2WRP_PAGE32 SYSCFG_SWPR2_PAGE32 /*!< SRAM2 Write protection page 32 */ +#define LL_SYSCFG_SRAM2WRP_PAGE33 SYSCFG_SWPR2_PAGE33 /*!< SRAM2 Write protection page 33 */ +#define LL_SYSCFG_SRAM2WRP_PAGE34 SYSCFG_SWPR2_PAGE34 /*!< SRAM2 Write protection page 34 */ +#define LL_SYSCFG_SRAM2WRP_PAGE35 SYSCFG_SWPR2_PAGE35 /*!< SRAM2 Write protection page 35 */ +#define LL_SYSCFG_SRAM2WRP_PAGE36 SYSCFG_SWPR2_PAGE36 /*!< SRAM2 Write protection page 36 */ +#define LL_SYSCFG_SRAM2WRP_PAGE37 SYSCFG_SWPR2_PAGE37 /*!< SRAM2 Write protection page 37 */ +#define LL_SYSCFG_SRAM2WRP_PAGE38 SYSCFG_SWPR2_PAGE38 /*!< SRAM2 Write protection page 38 */ +#define LL_SYSCFG_SRAM2WRP_PAGE39 SYSCFG_SWPR2_PAGE39 /*!< SRAM2 Write protection page 39 */ +#define LL_SYSCFG_SRAM2WRP_PAGE40 SYSCFG_SWPR2_PAGE40 /*!< SRAM2 Write protection page 40 */ +#define LL_SYSCFG_SRAM2WRP_PAGE41 SYSCFG_SWPR2_PAGE41 /*!< SRAM2 Write protection page 41 */ +#define LL_SYSCFG_SRAM2WRP_PAGE42 SYSCFG_SWPR2_PAGE42 /*!< SRAM2 Write protection page 42 */ +#define LL_SYSCFG_SRAM2WRP_PAGE43 SYSCFG_SWPR2_PAGE43 /*!< SRAM2 Write protection page 43 */ +#define LL_SYSCFG_SRAM2WRP_PAGE44 SYSCFG_SWPR2_PAGE44 /*!< SRAM2 Write protection page 44 */ +#define LL_SYSCFG_SRAM2WRP_PAGE45 SYSCFG_SWPR2_PAGE45 /*!< SRAM2 Write protection page 45 */ +#define LL_SYSCFG_SRAM2WRP_PAGE46 SYSCFG_SWPR2_PAGE46 /*!< SRAM2 Write protection page 46 */ +#define LL_SYSCFG_SRAM2WRP_PAGE47 SYSCFG_SWPR2_PAGE47 /*!< SRAM2 Write protection page 47 */ +#define LL_SYSCFG_SRAM2WRP_PAGE48 SYSCFG_SWPR2_PAGE48 /*!< SRAM2 Write protection page 48 */ +#define LL_SYSCFG_SRAM2WRP_PAGE49 SYSCFG_SWPR2_PAGE49 /*!< SRAM2 Write protection page 49 */ +#define LL_SYSCFG_SRAM2WRP_PAGE50 SYSCFG_SWPR2_PAGE50 /*!< SRAM2 Write protection page 50 */ +#define LL_SYSCFG_SRAM2WRP_PAGE51 SYSCFG_SWPR2_PAGE51 /*!< SRAM2 Write protection page 51 */ +#define LL_SYSCFG_SRAM2WRP_PAGE52 SYSCFG_SWPR2_PAGE52 /*!< SRAM2 Write protection page 52 */ +#define LL_SYSCFG_SRAM2WRP_PAGE53 SYSCFG_SWPR2_PAGE53 /*!< SRAM2 Write protection page 53 */ +#define LL_SYSCFG_SRAM2WRP_PAGE54 SYSCFG_SWPR2_PAGE54 /*!< SRAM2 Write protection page 54 */ +#define LL_SYSCFG_SRAM2WRP_PAGE55 SYSCFG_SWPR2_PAGE55 /*!< SRAM2 Write protection page 55 */ +#define LL_SYSCFG_SRAM2WRP_PAGE56 SYSCFG_SWPR2_PAGE56 /*!< SRAM2 Write protection page 56 */ +#define LL_SYSCFG_SRAM2WRP_PAGE57 SYSCFG_SWPR2_PAGE57 /*!< SRAM2 Write protection page 57 */ +#define LL_SYSCFG_SRAM2WRP_PAGE58 SYSCFG_SWPR2_PAGE58 /*!< SRAM2 Write protection page 58 */ +#define LL_SYSCFG_SRAM2WRP_PAGE59 SYSCFG_SWPR2_PAGE59 /*!< SRAM2 Write protection page 59 */ +#define LL_SYSCFG_SRAM2WRP_PAGE60 SYSCFG_SWPR2_PAGE60 /*!< SRAM2 Write protection page 60 */ +#define LL_SYSCFG_SRAM2WRP_PAGE61 SYSCFG_SWPR2_PAGE61 /*!< SRAM2 Write protection page 61 */ +#define LL_SYSCFG_SRAM2WRP_PAGE62 SYSCFG_SWPR2_PAGE62 /*!< SRAM2 Write protection page 62 */ +#define LL_SYSCFG_SRAM2WRP_PAGE63 SYSCFG_SWPR2_PAGE63 /*!< SRAM2 Write protection page 63 */ +#endif /* SYSCFG_SWPR2_PAGE63 */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment + * @{ + */ +#define LL_DBGMCU_TRACE_NONE 0x00000000U /*!< TRACE pins not assigned (default state) */ +#define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /*!< TRACE pin assignment for Asynchronous Mode */ +#define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */ +#define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */ +#define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP + * @{ + */ +#define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1FZR1_DBG_TIM2_STOP /*!< The counter clock of TIM2 is stopped when the core is halted*/ +#if defined(TIM3) +#define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1FZR1_DBG_TIM3_STOP /*!< The counter clock of TIM3 is stopped when the core is halted*/ +#endif /* TIM3 */ +#if defined(TIM4) +#define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1FZR1_DBG_TIM4_STOP /*!< The counter clock of TIM4 is stopped when the core is halted*/ +#endif /* TIM4 */ +#if defined(TIM5) +#define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1FZR1_DBG_TIM5_STOP /*!< The counter clock of TIM5 is stopped when the core is halted*/ +#endif /* TIM5 */ +#define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1FZR1_DBG_TIM6_STOP /*!< The counter clock of TIM6 is stopped when the core is halted*/ +#if defined(TIM7) +#define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1FZR1_DBG_TIM7_STOP /*!< The counter clock of TIM7 is stopped when the core is halted*/ +#endif /* TIM7 */ +#define LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB1FZR1_DBG_RTC_STOP /*!< The clock of the RTC counter is stopped when the core is halted*/ +#define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1FZR1_DBG_WWDG_STOP /*!< The window watchdog counter clock is stopped when the core is halted*/ +#define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1FZR1_DBG_IWDG_STOP /*!< The independent watchdog counter clock is stopped when the core is halted*/ +#define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1FZR1_DBG_I2C1_STOP /*!< The I2C1 SMBus timeout is frozen*/ +#if defined(I2C2) +#define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1FZR1_DBG_I2C2_STOP /*!< The I2C2 SMBus timeout is frozen*/ +#endif /* I2C2 */ +#define LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1FZR1_DBG_I2C3_STOP /*!< The I2C3 SMBus timeout is frozen*/ +#define LL_DBGMCU_APB1_GRP1_CAN_STOP DBGMCU_APB1FZR1_DBG_CAN_STOP /*!< The bxCAN receive registers are frozen*/ +#if defined(CAN2) +#define LL_DBGMCU_APB1_GRP1_CAN2_STOP DBGMCU_APB1FZR1_DBG_CAN2_STOP /*!< The bxCAN2 receive registers are frozen*/ +#endif /* CAN2 */ +#define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP DBGMCU_APB1FZR1_DBG_LPTIM1_STOP /*!< The counter clock of LPTIM1 is stopped when the core is halted*/ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_APB1_GRP2_STOP_IP DBGMCU APB1 GRP2 STOP IP + * @{ + */ +#if defined(I2C4) +#define LL_DBGMCU_APB1_GRP2_I2C4_STOP DBGMCU_APB1FZR2_DBG_I2C4_STOP /*!< The I2C4 SMBus timeout is frozen*/ +#endif /* I2C4 */ +#define LL_DBGMCU_APB1_GRP2_LPTIM2_STOP DBGMCU_APB1FZR2_DBG_LPTIM2_STOP /*!< The counter clock of LPTIM2 is stopped when the core is halted*/ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP + * @{ + */ +#define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2FZ_DBG_TIM1_STOP /*!< The counter clock of TIM1 is stopped when the core is halted*/ +#if defined(TIM8) +#define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_APB2FZ_DBG_TIM8_STOP /*!< The counter clock of TIM8 is stopped when the core is halted*/ +#endif /* TIM8 */ +#define LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_APB2FZ_DBG_TIM15_STOP /*!< The counter clock of TIM15 is stopped when the core is halted*/ +#define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_APB2FZ_DBG_TIM16_STOP /*!< The counter clock of TIM16 is stopped when the core is halted*/ +#if defined(TIM17) +#define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_APB2FZ_DBG_TIM17_STOP /*!< The counter clock of TIM17 is stopped when the core is halted*/ +#endif /* TIM17 */ +/** + * @} + */ + +#if defined(VREFBUF) +/** @defgroup SYSTEM_LL_EC_VOLTAGE VREFBUF VOLTAGE + * @{ + */ +#define LL_VREFBUF_VOLTAGE_SCALE0 ((uint32_t)0x00000000) /*!< Voltage reference scale 0 (VREF_OUT1) */ +#define LL_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS /*!< Voltage reference scale 1 (VREF_OUT2) */ +/** + * @} + */ +#endif /* VREFBUF */ + +/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY + * @{ + */ +#define LL_FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero wait state */ +#define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One wait state */ +#define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two wait states */ +#define LL_FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three wait states */ +#define LL_FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four wait states */ +#if defined(FLASH_ACR_LATENCY_5WS) +#define LL_FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH five wait state */ +#define LL_FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH six wait state */ +#define LL_FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH seven wait states */ +#define LL_FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH eight wait states */ +#define LL_FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH nine wait states */ +#define LL_FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH ten wait states */ +#define LL_FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /*!< FLASH eleven wait states */ +#define LL_FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /*!< FLASH twelve wait states */ +#define LL_FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH thirteen wait states */ +#define LL_FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH fourteen wait states */ +#define LL_FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH fifteen wait states */ +#endif +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions + * @{ + */ + +/** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG + * @{ + */ + +/** + * @brief Set memory mapping at address 0x00000000 + * @rmtoll SYSCFG_MEMRMP MEM_MODE LL_SYSCFG_SetRemapMemory + * @param Memory This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_REMAP_FLASH + * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH + * @arg @ref LL_SYSCFG_REMAP_SRAM + * @arg @ref LL_SYSCFG_REMAP_FMC (*) + * @arg @ref LL_SYSCFG_REMAP_QUADSPI + * + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory) +{ + MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, Memory); +} + +/** + * @brief Get memory mapping at address 0x00000000 + * @rmtoll SYSCFG_MEMRMP MEM_MODE LL_SYSCFG_GetRemapMemory + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_REMAP_FLASH + * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH + * @arg @ref LL_SYSCFG_REMAP_SRAM + * @arg @ref LL_SYSCFG_REMAP_FMC (*) + * @arg @ref LL_SYSCFG_REMAP_QUADSPI + * + * (*) value not defined in all devices + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)); +} + +#if defined(SYSCFG_MEMRMP_FB_MODE) +/** + * @brief Select Flash bank mode (Bank flashed at 0x08000000) + * @rmtoll SYSCFG_MEMRMP FB_MODE LL_SYSCFG_SetFlashBankMode + * @param Bank This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_BANKMODE_BANK1 + * @arg @ref LL_SYSCFG_BANKMODE_BANK2 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetFlashBankMode(uint32_t Bank) +{ + MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE, Bank); +} + +/** + * @brief Get Flash bank mode (Bank flashed at 0x08000000) + * @rmtoll SYSCFG_MEMRMP FB_MODE LL_SYSCFG_GetFlashBankMode + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_BANKMODE_BANK1 + * @arg @ref LL_SYSCFG_BANKMODE_BANK2 + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashBankMode(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE)); +} +#endif /* SYSCFG_MEMRMP_FB_MODE */ + +/** + * @brief Firewall protection enabled + * @rmtoll SYSCFG_CFGR1 FWDIS LL_SYSCFG_EnableFirewall + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableFirewall(void) +{ + CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FWDIS); +} + +/** + * @brief Check if Firewall protection is enabled or not + * @rmtoll SYSCFG_CFGR1 FWDIS LL_SYSCFG_IsEnabledFirewall + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledFirewall(void) +{ + return !(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FWDIS) == SYSCFG_CFGR1_FWDIS); +} + +/** + * @brief Enable I/O analog switch voltage booster. + * @note When voltage booster is enabled, I/O analog switches are supplied + * by a dedicated voltage booster, from VDD power domain. This is + * the recommended configuration with low VDDA voltage operation. + * @note The I/O analog switch voltage booster is relevant for peripherals + * using I/O in analog input: ADC, COMP, OPAMP. + * However, COMP and OPAMP inputs have a high impedance and + * voltage booster do not impact performance significantly. + * Therefore, the voltage booster is mainly intended for + * usage with ADC. + * @rmtoll SYSCFG_CFGR1 BOOSTEN LL_SYSCFG_EnableAnalogBooster + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableAnalogBooster(void) +{ + SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN); +} + +/** + * @brief Disable I/O analog switch voltage booster. + * @note When voltage booster is enabled, I/O analog switches are supplied + * by a dedicated voltage booster, from VDD power domain. This is + * the recommended configuration with low VDDA voltage operation. + * @note The I/O analog switch voltage booster is relevant for peripherals + * using I/O in analog input: ADC, COMP, OPAMP. + * However, COMP and OPAMP inputs have a high impedance and + * voltage booster do not impact performance significantly. + * Therefore, the voltage booster is mainly intended for + * usage with ADC. + * @rmtoll SYSCFG_CFGR1 BOOSTEN LL_SYSCFG_DisableAnalogBooster + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableAnalogBooster(void) +{ + CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN); +} + +/** + * @brief Enable the I2C fast mode plus driving capability. + * @rmtoll SYSCFG_CFGR1 I2C_PBx_FMP LL_SYSCFG_EnableFastModePlus\n + * SYSCFG_CFGR1 I2Cx_FMP LL_SYSCFG_EnableFastModePlus + * @param ConfigFastModePlus This parameter can be a combination of the following values: + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*) + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*) + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*) + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 (*) + * + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus) +{ + SET_BIT(SYSCFG->CFGR1, ConfigFastModePlus); +} + +/** + * @brief Disable the I2C fast mode plus driving capability. + * @rmtoll SYSCFG_CFGR1 I2C_PBx_FMP LL_SYSCFG_DisableFastModePlus\n + * SYSCFG_CFGR1 I2Cx_FMP LL_SYSCFG_DisableFastModePlus + * @param ConfigFastModePlus This parameter can be a combination of the following values: + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*) + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*) + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*) + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 (*) + * + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus) +{ + CLEAR_BIT(SYSCFG->CFGR1, ConfigFastModePlus); +} + +/** + * @brief Enable Floating Point Unit Invalid operation Interrupt + * @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_EnableIT_FPU_IOC + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IOC(void) +{ + SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0); +} + +/** + * @brief Enable Floating Point Unit Divide-by-zero Interrupt + * @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_EnableIT_FPU_DZC + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_DZC(void) +{ + SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1); +} + +/** + * @brief Enable Floating Point Unit Underflow Interrupt + * @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_EnableIT_FPU_UFC + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_UFC(void) +{ + SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2); +} + +/** + * @brief Enable Floating Point Unit Overflow Interrupt + * @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_EnableIT_FPU_OFC + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_OFC(void) +{ + SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3); +} + +/** + * @brief Enable Floating Point Unit Input denormal Interrupt + * @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_EnableIT_FPU_IDC + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IDC(void) +{ + SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4); +} + +/** + * @brief Enable Floating Point Unit Inexact Interrupt + * @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_EnableIT_FPU_IXC + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IXC(void) +{ + SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5); +} + +/** + * @brief Disable Floating Point Unit Invalid operation Interrupt + * @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_DisableIT_FPU_IOC + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IOC(void) +{ + CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0); +} + +/** + * @brief Disable Floating Point Unit Divide-by-zero Interrupt + * @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_DisableIT_FPU_DZC + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_DZC(void) +{ + CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1); +} + +/** + * @brief Disable Floating Point Unit Underflow Interrupt + * @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_DisableIT_FPU_UFC + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_UFC(void) +{ + CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2); +} + +/** + * @brief Disable Floating Point Unit Overflow Interrupt + * @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_DisableIT_FPU_OFC + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_OFC(void) +{ + CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3); +} + +/** + * @brief Disable Floating Point Unit Input denormal Interrupt + * @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_DisableIT_FPU_IDC + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IDC(void) +{ + CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4); +} + +/** + * @brief Disable Floating Point Unit Inexact Interrupt + * @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_DisableIT_FPU_IXC + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IXC(void) +{ + CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5); +} + +/** + * @brief Check if Floating Point Unit Invalid operation Interrupt source is enabled or disabled. + * @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_IsEnabledIT_FPU_IOC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IOC(void) +{ + return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0) == (SYSCFG_CFGR1_FPU_IE_0)); +} + +/** + * @brief Check if Floating Point Unit Divide-by-zero Interrupt source is enabled or disabled. + * @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_IsEnabledIT_FPU_DZC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_DZC(void) +{ + return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1) == (SYSCFG_CFGR1_FPU_IE_1)); +} + +/** + * @brief Check if Floating Point Unit Underflow Interrupt source is enabled or disabled. + * @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_IsEnabledIT_FPU_UFC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_UFC(void) +{ + return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2) == (SYSCFG_CFGR1_FPU_IE_2)); +} + +/** + * @brief Check if Floating Point Unit Overflow Interrupt source is enabled or disabled. + * @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_IsEnabledIT_FPU_OFC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_OFC(void) +{ + return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3) == (SYSCFG_CFGR1_FPU_IE_3)); +} + +/** + * @brief Check if Floating Point Unit Input denormal Interrupt source is enabled or disabled. + * @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_IsEnabledIT_FPU_IDC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IDC(void) +{ + return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4) == (SYSCFG_CFGR1_FPU_IE_4)); +} + +/** + * @brief Check if Floating Point Unit Inexact Interrupt source is enabled or disabled. + * @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_IsEnabledIT_FPU_IXC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IXC(void) +{ + return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5) == (SYSCFG_CFGR1_FPU_IE_5)); +} + +/** + * @brief Configure source input for the EXTI external interrupt. + * @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR2 EXTIx LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR3 EXTIx LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR4 EXTIx LL_SYSCFG_SetEXTISource + * @param Port This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_EXTI_PORTA + * @arg @ref LL_SYSCFG_EXTI_PORTB + * @arg @ref LL_SYSCFG_EXTI_PORTC + * @arg @ref LL_SYSCFG_EXTI_PORTD + * @arg @ref LL_SYSCFG_EXTI_PORTE + * @arg @ref LL_SYSCFG_EXTI_PORTF (*) + * @arg @ref LL_SYSCFG_EXTI_PORTG (*) + * @arg @ref LL_SYSCFG_EXTI_PORTH + * @arg @ref LL_SYSCFG_EXTI_PORTI (*) + * + * (*) value not defined in all devices + * @param Line This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_EXTI_LINE0 + * @arg @ref LL_SYSCFG_EXTI_LINE1 + * @arg @ref LL_SYSCFG_EXTI_LINE2 + * @arg @ref LL_SYSCFG_EXTI_LINE3 + * @arg @ref LL_SYSCFG_EXTI_LINE4 + * @arg @ref LL_SYSCFG_EXTI_LINE5 + * @arg @ref LL_SYSCFG_EXTI_LINE6 + * @arg @ref LL_SYSCFG_EXTI_LINE7 + * @arg @ref LL_SYSCFG_EXTI_LINE8 + * @arg @ref LL_SYSCFG_EXTI_LINE9 + * @arg @ref LL_SYSCFG_EXTI_LINE10 + * @arg @ref LL_SYSCFG_EXTI_LINE11 + * @arg @ref LL_SYSCFG_EXTI_LINE12 + * @arg @ref LL_SYSCFG_EXTI_LINE13 + * @arg @ref LL_SYSCFG_EXTI_LINE14 + * @arg @ref LL_SYSCFG_EXTI_LINE15 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line) +{ + MODIFY_REG(SYSCFG->EXTICR[Line & 0xFFU], (Line >> 16U), Port << POSITION_VAL((Line >> 16U))); +} + +/** + * @brief Get the configured defined for specific EXTI Line + * @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR2 EXTIx LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR3 EXTIx LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR4 EXTIx LL_SYSCFG_GetEXTISource + * @param Line This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_EXTI_LINE0 + * @arg @ref LL_SYSCFG_EXTI_LINE1 + * @arg @ref LL_SYSCFG_EXTI_LINE2 + * @arg @ref LL_SYSCFG_EXTI_LINE3 + * @arg @ref LL_SYSCFG_EXTI_LINE4 + * @arg @ref LL_SYSCFG_EXTI_LINE5 + * @arg @ref LL_SYSCFG_EXTI_LINE6 + * @arg @ref LL_SYSCFG_EXTI_LINE7 + * @arg @ref LL_SYSCFG_EXTI_LINE8 + * @arg @ref LL_SYSCFG_EXTI_LINE9 + * @arg @ref LL_SYSCFG_EXTI_LINE10 + * @arg @ref LL_SYSCFG_EXTI_LINE11 + * @arg @ref LL_SYSCFG_EXTI_LINE12 + * @arg @ref LL_SYSCFG_EXTI_LINE13 + * @arg @ref LL_SYSCFG_EXTI_LINE14 + * @arg @ref LL_SYSCFG_EXTI_LINE15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_EXTI_PORTA + * @arg @ref LL_SYSCFG_EXTI_PORTB + * @arg @ref LL_SYSCFG_EXTI_PORTC + * @arg @ref LL_SYSCFG_EXTI_PORTD + * @arg @ref LL_SYSCFG_EXTI_PORTE + * @arg @ref LL_SYSCFG_EXTI_PORTF (*) + * @arg @ref LL_SYSCFG_EXTI_PORTG (*) + * @arg @ref LL_SYSCFG_EXTI_PORTH + * @arg @ref LL_SYSCFG_EXTI_PORTI (*) + * + * (*) value not defined in all devices + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line) +{ + return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0xFFU], (Line >> 16U)) >> POSITION_VAL(Line >> 16U)); +} + +/** + * @brief Enable SRAM2 Erase (starts a hardware SRAM2 erase operation. This bit is + * automatically cleared at the end of the SRAM2 erase operation.) + * @note This bit is write-protected: setting this bit is possible only after the + * correct key sequence is written in the SYSCFG_SKR register as described in + * the Reference Manual. + * @rmtoll SYSCFG_SCSR SRAM2ER LL_SYSCFG_EnableSRAM2Erase + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableSRAM2Erase(void) +{ + /* Starts a hardware SRAM2 erase operation*/ + SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_SRAM2ER); +} + +/** + * @brief Check if SRAM2 erase operation is on going + * @rmtoll SYSCFG_SCSR SRAM2BSY LL_SYSCFG_IsSRAM2EraseOngoing + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsSRAM2EraseOngoing(void) +{ + return (READ_BIT(SYSCFG->SCSR, SYSCFG_SCSR_SRAM2BSY) == (SYSCFG_SCSR_SRAM2BSY)); +} + +/** + * @brief Set connections to TIM1/8/15/16/17 Break inputs + * @rmtoll SYSCFG_CFGR2 CLL LL_SYSCFG_SetTIMBreakInputs\n + * SYSCFG_CFGR2 SPL LL_SYSCFG_SetTIMBreakInputs\n + * SYSCFG_CFGR2 PVDL LL_SYSCFG_SetTIMBreakInputs\n + * SYSCFG_CFGR2 ECCL LL_SYSCFG_SetTIMBreakInputs + * @param Break This parameter can be a combination of the following values: + * @arg @ref LL_SYSCFG_TIMBREAK_ECC + * @arg @ref LL_SYSCFG_TIMBREAK_PVD + * @arg @ref LL_SYSCFG_TIMBREAK_SRAM2_PARITY + * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break) +{ + MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_PVDL | SYSCFG_CFGR2_ECCL, Break); +} + +/** + * @brief Get connections to TIM1/8/15/16/17 Break inputs + * @rmtoll SYSCFG_CFGR2 CLL LL_SYSCFG_GetTIMBreakInputs\n + * SYSCFG_CFGR2 SPL LL_SYSCFG_GetTIMBreakInputs\n + * SYSCFG_CFGR2 PVDL LL_SYSCFG_GetTIMBreakInputs\n + * SYSCFG_CFGR2 ECCL LL_SYSCFG_GetTIMBreakInputs + * @retval Returned value can be can be a combination of the following values: + * @arg @ref LL_SYSCFG_TIMBREAK_ECC + * @arg @ref LL_SYSCFG_TIMBREAK_PVD + * @arg @ref LL_SYSCFG_TIMBREAK_SRAM2_PARITY + * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_PVDL | SYSCFG_CFGR2_ECCL)); +} + +/** + * @brief Check if SRAM2 parity error detected + * @rmtoll SYSCFG_CFGR2 SPF LL_SYSCFG_IsActiveFlag_SP + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SP(void) +{ + return (READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF) == (SYSCFG_CFGR2_SPF)); +} + +/** + * @brief Clear SRAM2 parity error flag + * @rmtoll SYSCFG_CFGR2 SPF LL_SYSCFG_ClearFlag_SP + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_ClearFlag_SP(void) +{ + SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF); +} + +/** + * @brief Enable SRAM2 page write protection for Pages in range 0 to 31 + * @note Write protection is cleared only by a system reset + * @rmtoll SYSCFG_SWPR PxWP LL_SYSCFG_EnableSRAM2PageWRP_0_31 + * @param SRAM2WRP This parameter can be a combination of the following values: + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE0 + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE1 + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE2 + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE3 + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE4 + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE5 + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE6 + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE7 + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE8 + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE9 + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE10 + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE11 + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE12 + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE13 + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE14 + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE15 + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE16 (*) + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE17 (*) + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE18 (*) + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE19 (*) + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE20 (*) + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE21 (*) + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE22 (*) + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE23 (*) + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE24 (*) + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE25 (*) + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE26 (*) + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE27 (*) + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE28 (*) + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE29 (*) + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE30 (*) + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE31 (*) + * + * (*) value not defined in all devices + * @retval None + */ +/* Legacy define */ +#define LL_SYSCFG_EnableSRAM2PageWRP LL_SYSCFG_EnableSRAM2PageWRP_0_31 +__STATIC_INLINE void LL_SYSCFG_EnableSRAM2PageWRP_0_31(uint32_t SRAM2WRP) +{ + SET_BIT(SYSCFG->SWPR, SRAM2WRP); +} + +#if defined(SYSCFG_SWPR2_PAGE63) +/** + * @brief Enable SRAM2 page write protection for Pages in range 32 to 63 + * @note Write protection is cleared only by a system reset + * @rmtoll SYSCFG_SWPR2 PxWP LL_SYSCFG_EnableSRAM2PageWRP_32_63 + * @param SRAM2WRP This parameter can be a combination of the following values: + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE32 (*) + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE33 (*) + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE34 (*) + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE35 (*) + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE36 (*) + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE37 (*) + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE38 (*) + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE39 (*) + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE40 (*) + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE41 (*) + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE42 (*) + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE43 (*) + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE44 (*) + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE45 (*) + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE46 (*) + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE47 (*) + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE48 (*) + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE49 (*) + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE50 (*) + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE51 (*) + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE52 (*) + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE53 (*) + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE54 (*) + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE55 (*) + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE56 (*) + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE57 (*) + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE58 (*) + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE59 (*) + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE60 (*) + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE61 (*) + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE62 (*) + * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE63 (*) + * + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableSRAM2PageWRP_32_63(uint32_t SRAM2WRP) +{ + SET_BIT(SYSCFG->SWPR2, SRAM2WRP); +} +#endif /* SYSCFG_SWPR2_PAGE63 */ + +/** + * @brief SRAM2 page write protection lock prior to erase + * @rmtoll SYSCFG_SKR KEY LL_SYSCFG_LockSRAM2WRP + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_LockSRAM2WRP(void) +{ + /* Writing a wrong key reactivates the write protection */ + WRITE_REG(SYSCFG->SKR, 0x00); +} + +/** + * @brief SRAM2 page write protection unlock prior to erase + * @rmtoll SYSCFG_SKR KEY LL_SYSCFG_UnlockSRAM2WRP + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_UnlockSRAM2WRP(void) +{ + /* unlock the write protection of the SRAM2ER bit */ + WRITE_REG(SYSCFG->SKR, 0xCA); + WRITE_REG(SYSCFG->SKR, 0x53); +} + +/** + * @} + */ + + +/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU + * @{ + */ + +/** + * @brief Return the device identifier + * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID + * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF (ex: device ID is 0x6415) + */ +__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void) +{ + return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID)); +} + +/** + * @brief Return the device revision identifier + * @note This field indicates the revision of the device. + * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID + * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF + */ +__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void) +{ + return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos); +} + +/** + * @brief Enable the Debug Module during SLEEP mode + * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); +} + +/** + * @brief Disable the Debug Module during SLEEP mode + * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); +} + +/** + * @brief Enable the Debug Module during STOP mode + * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +} + +/** + * @brief Disable the Debug Module during STOP mode + * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +} + +/** + * @brief Enable the Debug Module during STANDBY mode + * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +} + +/** + * @brief Disable the Debug Module during STANDBY mode + * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +} + +/** + * @brief Set Trace pin assignment control + * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n + * DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment + * @param PinAssignment This parameter can be one of the following values: + * @arg @ref LL_DBGMCU_TRACE_NONE + * @arg @ref LL_DBGMCU_TRACE_ASYNCH + * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1 + * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2 + * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4 + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment) +{ + MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment); +} + +/** + * @brief Get Trace pin assignment control + * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n + * DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment + * @retval Returned value can be one of the following values: + * @arg @ref LL_DBGMCU_TRACE_NONE + * @arg @ref LL_DBGMCU_TRACE_ASYNCH + * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1 + * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2 + * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4 + */ +__STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void) +{ + return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE)); +} + +/** + * @brief Freeze APB1 peripherals (group1 peripherals) + * @rmtoll DBGMCU_APB1FZR1 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_CAN_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->APB1FZR1, Periphs); +} + +/** + * @brief Freeze APB1 peripherals (group2 peripherals) + * @rmtoll DBGMCU_APB1FZR2 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP2_I2C4_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP2_LPTIM2_STOP + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->APB1FZR2, Periphs); +} + +/** + * @brief Unfreeze APB1 peripherals (group1 peripherals) + * @rmtoll DBGMCU_APB1FZR1 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_CAN_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs) +{ + CLEAR_BIT(DBGMCU->APB1FZR1, Periphs); +} + +/** + * @brief Unfreeze APB1 peripherals (group2 peripherals) + * @rmtoll DBGMCU_APB1FZR2 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP2_I2C4_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP2_LPTIM2_STOP + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs) +{ + CLEAR_BIT(DBGMCU->APB1FZR2, Periphs); +} + +/** + * @brief Freeze APB2 peripherals + * @rmtoll DBGMCU_APB2FZ DBG_TIMx_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*) + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->APB2FZ, Periphs); +} + +/** + * @brief Unfreeze APB2 peripherals + * @rmtoll DBGMCU_APB2FZ DBG_TIMx_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*) + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs) +{ + CLEAR_BIT(DBGMCU->APB2FZ, Periphs); +} + +/** + * @} + */ + +#if defined(VREFBUF) +/** @defgroup SYSTEM_LL_EF_VREFBUF VREFBUF + * @{ + */ + +/** + * @brief Enable Internal voltage reference + * @rmtoll VREFBUF_CSR ENVR LL_VREFBUF_Enable + * @retval None + */ +__STATIC_INLINE void LL_VREFBUF_Enable(void) +{ + SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR); +} + +/** + * @brief Disable Internal voltage reference + * @rmtoll VREFBUF_CSR ENVR LL_VREFBUF_Disable + * @retval None + */ +__STATIC_INLINE void LL_VREFBUF_Disable(void) +{ + CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR); +} + +/** + * @brief Enable high impedance (VREF+pin is high impedance) + * @rmtoll VREFBUF_CSR HIZ LL_VREFBUF_EnableHIZ + * @retval None + */ +__STATIC_INLINE void LL_VREFBUF_EnableHIZ(void) +{ + SET_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ); +} + +/** + * @brief Disable high impedance (VREF+pin is internally connected to the voltage reference buffer output) + * @rmtoll VREFBUF_CSR HIZ LL_VREFBUF_DisableHIZ + * @retval None + */ +__STATIC_INLINE void LL_VREFBUF_DisableHIZ(void) +{ + CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ); +} + +/** + * @brief Set the Voltage reference scale + * @rmtoll VREFBUF_CSR VRS LL_VREFBUF_SetVoltageScaling + * @param Scale This parameter can be one of the following values: + * @arg @ref LL_VREFBUF_VOLTAGE_SCALE0 + * @arg @ref LL_VREFBUF_VOLTAGE_SCALE1 + * @retval None + */ +__STATIC_INLINE void LL_VREFBUF_SetVoltageScaling(uint32_t Scale) +{ + MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, Scale); +} + +/** + * @brief Get the Voltage reference scale + * @rmtoll VREFBUF_CSR VRS LL_VREFBUF_GetVoltageScaling + * @retval Returned value can be one of the following values: + * @arg @ref LL_VREFBUF_VOLTAGE_SCALE0 + * @arg @ref LL_VREFBUF_VOLTAGE_SCALE1 + */ +__STATIC_INLINE uint32_t LL_VREFBUF_GetVoltageScaling(void) +{ + return (uint32_t)(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRS)); +} + +/** + * @brief Check if Voltage reference buffer is ready + * @rmtoll VREFBUF_CSR VRR LL_VREFBUF_IsVREFReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_VREFBUF_IsVREFReady(void) +{ + return (READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == (VREFBUF_CSR_VRR)); +} + +/** + * @brief Get the trimming code for VREFBUF calibration + * @rmtoll VREFBUF_CCR TRIM LL_VREFBUF_GetTrimming + * @retval Between 0 and 0x3F + */ +__STATIC_INLINE uint32_t LL_VREFBUF_GetTrimming(void) +{ + return (uint32_t)(READ_BIT(VREFBUF->CCR, VREFBUF_CCR_TRIM)); +} + +/** + * @brief Set the trimming code for VREFBUF calibration (Tune the internal reference buffer voltage) + * @rmtoll VREFBUF_CCR TRIM LL_VREFBUF_SetTrimming + * @param Value Between 0 and 0x3F + * @retval None + */ +__STATIC_INLINE void LL_VREFBUF_SetTrimming(uint32_t Value) +{ + WRITE_REG(VREFBUF->CCR, Value); +} + +/** + * @} + */ +#endif /* VREFBUF */ + +/** @defgroup SYSTEM_LL_EF_FLASH FLASH + * @{ + */ + +/** + * @brief Set FLASH Latency + * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency + * @param Latency This parameter can be one of the following values: + * @arg @ref LL_FLASH_LATENCY_0 + * @arg @ref LL_FLASH_LATENCY_1 + * @arg @ref LL_FLASH_LATENCY_2 + * @arg @ref LL_FLASH_LATENCY_3 + * @arg @ref LL_FLASH_LATENCY_4 + * @arg @ref LL_FLASH_LATENCY_5 (*) + * @arg @ref LL_FLASH_LATENCY_6 (*) + * @arg @ref LL_FLASH_LATENCY_7 (*) + * @arg @ref LL_FLASH_LATENCY_8 (*) + * @arg @ref LL_FLASH_LATENCY_9 (*) + * @arg @ref LL_FLASH_LATENCY_10 (*) + * @arg @ref LL_FLASH_LATENCY_11 (*) + * @arg @ref LL_FLASH_LATENCY_12 (*) + * @arg @ref LL_FLASH_LATENCY_13 (*) + * @arg @ref LL_FLASH_LATENCY_14 (*) + * @arg @ref LL_FLASH_LATENCY_15 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency) +{ + MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency); +} + +/** + * @brief Get FLASH Latency + * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency + * @retval Returned value can be one of the following values: + * @arg @ref LL_FLASH_LATENCY_0 + * @arg @ref LL_FLASH_LATENCY_1 + * @arg @ref LL_FLASH_LATENCY_2 + * @arg @ref LL_FLASH_LATENCY_3 + * @arg @ref LL_FLASH_LATENCY_4 + * @arg @ref LL_FLASH_LATENCY_5 (*) + * @arg @ref LL_FLASH_LATENCY_6 (*) + * @arg @ref LL_FLASH_LATENCY_7 (*) + * @arg @ref LL_FLASH_LATENCY_8 (*) + * @arg @ref LL_FLASH_LATENCY_9 (*) + * @arg @ref LL_FLASH_LATENCY_10 (*) + * @arg @ref LL_FLASH_LATENCY_11 (*) + * @arg @ref LL_FLASH_LATENCY_12 (*) + * @arg @ref LL_FLASH_LATENCY_13 (*) + * @arg @ref LL_FLASH_LATENCY_14 (*) + * @arg @ref LL_FLASH_LATENCY_15 (*) + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void) +{ + return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)); +} + +/** + * @brief Enable Prefetch + * @rmtoll FLASH_ACR PRFTEN LL_FLASH_EnablePrefetch + * @retval None + */ +__STATIC_INLINE void LL_FLASH_EnablePrefetch(void) +{ + SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN); +} + +/** + * @brief Disable Prefetch + * @rmtoll FLASH_ACR PRFTEN LL_FLASH_DisablePrefetch + * @retval None + */ +__STATIC_INLINE void LL_FLASH_DisablePrefetch(void) +{ + CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN); +} + +/** + * @brief Check if Prefetch buffer is enabled + * @rmtoll FLASH_ACR PRFTEN LL_FLASH_IsPrefetchEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void) +{ + return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) == (FLASH_ACR_PRFTEN)); +} + +/** + * @brief Enable Instruction cache + * @rmtoll FLASH_ACR ICEN LL_FLASH_EnableInstCache + * @retval None + */ +__STATIC_INLINE void LL_FLASH_EnableInstCache(void) +{ + SET_BIT(FLASH->ACR, FLASH_ACR_ICEN); +} + +/** + * @brief Disable Instruction cache + * @rmtoll FLASH_ACR ICEN LL_FLASH_DisableInstCache + * @retval None + */ +__STATIC_INLINE void LL_FLASH_DisableInstCache(void) +{ + CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN); +} + +/** + * @brief Enable Data cache + * @rmtoll FLASH_ACR DCEN LL_FLASH_EnableDataCache + * @retval None + */ +__STATIC_INLINE void LL_FLASH_EnableDataCache(void) +{ + SET_BIT(FLASH->ACR, FLASH_ACR_DCEN); +} + +/** + * @brief Disable Data cache + * @rmtoll FLASH_ACR DCEN LL_FLASH_DisableDataCache + * @retval None + */ +__STATIC_INLINE void LL_FLASH_DisableDataCache(void) +{ + CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN); +} + +/** + * @brief Enable Instruction cache reset + * @note bit can be written only when the instruction cache is disabled + * @rmtoll FLASH_ACR ICRST LL_FLASH_EnableInstCacheReset + * @retval None + */ +__STATIC_INLINE void LL_FLASH_EnableInstCacheReset(void) +{ + SET_BIT(FLASH->ACR, FLASH_ACR_ICRST); +} + +/** + * @brief Disable Instruction cache reset + * @rmtoll FLASH_ACR ICRST LL_FLASH_DisableInstCacheReset + * @retval None + */ +__STATIC_INLINE void LL_FLASH_DisableInstCacheReset(void) +{ + CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST); +} + +/** + * @brief Enable Data cache reset + * @note bit can be written only when the data cache is disabled + * @rmtoll FLASH_ACR DCRST LL_FLASH_EnableDataCacheReset + * @retval None + */ +__STATIC_INLINE void LL_FLASH_EnableDataCacheReset(void) +{ + SET_BIT(FLASH->ACR, FLASH_ACR_DCRST); +} + +/** + * @brief Disable Data cache reset + * @rmtoll FLASH_ACR DCRST LL_FLASH_DisableDataCacheReset + * @retval None + */ +__STATIC_INLINE void LL_FLASH_DisableDataCacheReset(void) +{ + CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST); +} + +/** + * @brief Enable Flash Power-down mode during run mode or Low-power run mode + * @note Flash memory can be put in power-down mode only when the code is executed + * from RAM + * @note Flash must not be accessed when power down is enabled + * @note Flash must not be put in power-down while a program or an erase operation + * is on-going + * @rmtoll FLASH_ACR RUN_PD LL_FLASH_EnableRunPowerDown\n + * FLASH_PDKEYR PDKEY1 LL_FLASH_EnableRunPowerDown\n + * FLASH_PDKEYR PDKEY2 LL_FLASH_EnableRunPowerDown + * @retval None + */ +__STATIC_INLINE void LL_FLASH_EnableRunPowerDown(void) +{ + /* Following values must be written consecutively to unlock the RUN_PD bit in + FLASH_ACR */ + WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); + WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); + SET_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); +} + +/** + * @brief Disable Flash Power-down mode during run mode or Low-power run mode + * @rmtoll FLASH_ACR RUN_PD LL_FLASH_DisableRunPowerDown\n + * FLASH_PDKEYR PDKEY1 LL_FLASH_DisableRunPowerDown\n + * FLASH_PDKEYR PDKEY2 LL_FLASH_DisableRunPowerDown + * @retval None + */ +__STATIC_INLINE void LL_FLASH_DisableRunPowerDown(void) +{ + /* Following values must be written consecutively to unlock the RUN_PD bit in + FLASH_ACR */ + WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); + WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); + CLEAR_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); +} + +/** + * @brief Enable Flash Power-down mode during Sleep or Low-power sleep mode + * @note Flash must not be put in power-down while a program or an erase operation + * is on-going + * @rmtoll FLASH_ACR SLEEP_PD LL_FLASH_EnableSleepPowerDown + * @retval None + */ +__STATIC_INLINE void LL_FLASH_EnableSleepPowerDown(void) +{ + SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD); +} + +/** + * @brief Disable Flash Power-down mode during Sleep or Low-power sleep mode + * @rmtoll FLASH_ACR SLEEP_PD LL_FLASH_DisableSleepPowerDown + * @retval None + */ +__STATIC_INLINE void LL_FLASH_DisableSleepPowerDown(void) +{ + CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) || defined (VREFBUF) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32L4xx_LL_SYSTEM_H */ diff --git a/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_utils.h b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_utils.h new file mode 100644 index 0000000..d465c0d --- /dev/null +++ b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_utils.h @@ -0,0 +1,329 @@ +/** + ****************************************************************************** + * @file stm32l4xx_ll_utils.h + * @author MCD Application Team + * @brief Header file of UTILS LL module. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The LL UTILS driver contains a set of generic APIs that can be + used by user: + (+) Device electronic signature + (+) Timing functions + (+) PLL configuration functions + + @endverbatim + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32L4xx_LL_UTILS_H +#define STM32L4xx_LL_UTILS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx.h" + +/** @addtogroup STM32L4xx_LL_Driver + * @{ + */ + +/** @defgroup UTILS_LL UTILS + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants + * @{ + */ + +/* Max delay can be used in LL_mDelay */ +#define LL_MAX_DELAY 0xFFFFFFFFU + +/** + * @brief Unique device ID register base address + */ +#define UID_BASE_ADDRESS UID_BASE + +/** + * @brief Flash size data register base address + */ +#define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE + +/** + * @brief Package data register base address + */ +#define PACKAGE_BASE_ADDRESS PACKAGE_BASE + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup UTILS_LL_Private_Macros UTILS Private Macros + * @{ + */ +/** + * @} + */ +/* Exported types ------------------------------------------------------------*/ +/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures + * @{ + */ +/** + * @brief UTILS PLL structure definition + */ +typedef struct +{ + uint32_t PLLM; /*!< Division factor for PLL VCO input clock. + This parameter can be a value of @ref RCC_LL_EC_PLLM_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_PLL_ConfigDomain_SYS(). */ + + uint32_t PLLN; /*!< Multiplication factor for PLL VCO output clock. + This parameter must be a number between Min_Data = 8 and Max_Data = 86 + + This feature can be modified afterwards using unitary function + @ref LL_RCC_PLL_ConfigDomain_SYS(). */ + + uint32_t PLLR; /*!< Division for the main system clock. + This parameter can be a value of @ref RCC_LL_EC_PLLR_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_PLL_ConfigDomain_SYS(). */ +} LL_UTILS_PLLInitTypeDef; + +/** + * @brief UTILS System, AHB and APB buses clock configuration structure definition + */ +typedef struct +{ + uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). + This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_SetAHBPrescaler(). */ + + uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_LL_EC_APB1_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_SetAPB1Prescaler(). */ + + uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_LL_EC_APB2_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_SetAPB2Prescaler(). */ + +} LL_UTILS_ClkInitTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants + * @{ + */ + +/** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation + * @{ + */ +#define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */ +#define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled */ +/** + * @} + */ + +/** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE + * @{ + */ +#define LL_UTILS_PACKAGETYPE_LQFP64 0x00000000U /*!< LQFP64 package type */ +#define LL_UTILS_PACKAGETYPE_WLCSP64 0x00000001U /*!< WLCSP64 package type */ +#define LL_UTILS_PACKAGETYPE_LQFP100 0x00000002U /*!< LQFP100 package type */ +#define LL_UTILS_PACKAGETYPE_BGA132 0x00000003U /*!< BGA132 package type */ +#define LL_UTILS_PACKAGETYPE_LQFP144_CSP72 0x00000004U /*!< LQFP144, WLCSP81 or WLCSP72 package type */ +#define LL_UTILS_PACKAGETYPE_UFQFPN32 0x00000008U /*!< UFQFPN32 package type */ +#define LL_UTILS_PACKAGETYPE_UFQFPN48 0x0000000AU /*!< UFQFPN48 package type */ +#define LL_UTILS_PACKAGETYPE_LQFP48 0x0000000BU /*!< LQFP48 package type */ +#define LL_UTILS_PACKAGETYPE_WLCSP49 0x0000000CU /*!< WLCSP49 package type */ +#define LL_UTILS_PACKAGETYPE_UFBGA64 0x0000000DU /*!< UFBGA64 package type */ +#define LL_UTILS_PACKAGETYPE_UFBGA100 0x0000000EU /*!< UFBGA100 package type */ +#define LL_UTILS_PACKAGETYPE_UFBGA169_CSP115 0x00000010U /*!< UFBGA169 or WLCSP115 package type */ +#define LL_UTILS_PACKAGETYPE_LQFP100_DSI 0x00000012U /*!< LQFP100 with DSI package type */ +#define LL_UTILS_PACKAGETYPE_WLCSP144_DSI 0x00000013U /*!< WLCSP144 with DSI package type */ +#define LL_UTILS_PACKAGETYPE_UFBGA144_DSI 0x00000013U /*!< UFBGA144 with DSI package type */ +#define LL_UTILS_PACKAGETYPE_UFBGA169_DSI 0x00000014U /*!< UFBGA169 with DSI package type */ +#define LL_UTILS_PACKAGETYPE_LQFP144_DSI 0x00000015U /*!< LQFP144 with DSI package type */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions + * @{ + */ + +/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE + * @{ + */ + +/** + * @brief Get Word0 of the unique device identifier (UID based on 96 bits) + * @retval UID[31:0]: X and Y coordinates on the wafer expressed in BCD format + */ +__STATIC_INLINE uint32_t LL_GetUID_Word0(void) +{ + return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS))); +} + +/** + * @brief Get Word1 of the unique device identifier (UID based on 96 bits) + * @retval UID[63:32]: Wafer number (UID[39:32]) & LOT_NUM[23:0] (UID[63:40]) + */ +__STATIC_INLINE uint32_t LL_GetUID_Word1(void) +{ + return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U)))); +} + +/** + * @brief Get Word2 of the unique device identifier (UID based on 96 bits) + * @retval UID[95:64]: Lot number (ASCII encoded) - LOT_NUM[55:24] + */ +__STATIC_INLINE uint32_t LL_GetUID_Word2(void) +{ + return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U)))); +} + +/** + * @brief Get Flash memory size + * @note This bitfield indicates the size of the device Flash memory expressed in + * Kbytes. As an example, 0x040 corresponds to 64 Kbytes. + * @retval FLASH_SIZE[15:0]: Flash memory size + */ +__STATIC_INLINE uint32_t LL_GetFlashSize(void) +{ + return (uint32_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)) & 0xFFFFU); +} + +/** + * @brief Get Package type + * @retval Returned value can be one of the following values: + * @arg @ref LL_UTILS_PACKAGETYPE_LQFP64 (*) + * @arg @ref LL_UTILS_PACKAGETYPE_LQFP100 (*) + * @arg @ref LL_UTILS_PACKAGETYPE_BGA132 (*) + * @arg @ref LL_UTILS_PACKAGETYPE_LQFP144_CSP72 (*) + * @arg @ref LL_UTILS_PACKAGETYPE_UFQFPN32 (*) + * @arg @ref LL_UTILS_PACKAGETYPE_UFQFPN48 (*) + * @arg @ref LL_UTILS_PACKAGETYPE_LQFP48 (*) + * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP49 (*) + * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA64 (*) + * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA100 (*) + * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA169 (*) + * @arg @ref LL_UTILS_PACKAGETYPE_LQFP100_DSI (*) + * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP144_DSI (*) + * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA144_DSI (*) + * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA169_DSI (*) + * @arg @ref LL_UTILS_PACKAGETYPE_LQFP144_DSI (*) + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_GetPackageType(void) +{ + return (uint32_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)) & 0x1FU); +} + +/** + * @} + */ + +/** @defgroup UTILS_LL_EF_DELAY DELAY + * @{ + */ + +/** + * @brief This function configures the Cortex-M SysTick source of the time base. + * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro) + * @note When a RTOS is used, it is recommended to avoid changing the SysTick + * configuration by calling this function, for a delay use rather osDelay RTOS service. + * @param Ticks Number of ticks + * @retval None + */ +__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks) +{ + /* Configure the SysTick to have interrupt in 1ms time base */ + SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */ +} + +void LL_Init1msTick(uint32_t HCLKFrequency); +void LL_mDelay(uint32_t Delay); + +/** + * @} + */ + +/** @defgroup UTILS_EF_SYSTEM SYSTEM + * @{ + */ + +void LL_SetSystemCoreClock(uint32_t HCLKFrequency); +ErrorStatus LL_SetFlashLatency(uint32_t HCLKFrequency); +ErrorStatus LL_PLL_ConfigSystemClock_MSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, + LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); +ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, + LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); +ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass, + LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32L4xx_LL_UTILS_H */ diff --git a/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_crc.c b/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_crc.c new file mode 100644 index 0000000..8e14df5 --- /dev/null +++ b/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_crc.c @@ -0,0 +1,516 @@ +/** + ****************************************************************************** + * @file stm32l4xx_hal_crc.c + * @author MCD Application Team + * @brief CRC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Cyclic Redundancy Check (CRC) peripheral: + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + Peripheral State functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + (+) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE(); + (+) Initialize CRC calculator + (++) specify generating polynomial (peripheral default or non-default one) + (++) specify initialization value (peripheral default or non-default one) + (++) specify input data format + (++) specify input or output data inversion mode if any + (+) Use HAL_CRC_Accumulate() function to compute the CRC value of the + input data buffer starting with the previously computed CRC as + initialization value + (+) Use HAL_CRC_Calculate() function to compute the CRC value of the + input data buffer starting with the defined initialization value + (default or non-default) to initiate CRC calculation + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx_hal.h" + +/** @addtogroup STM32L4xx_HAL_Driver + * @{ + */ + +/** @defgroup CRC CRC + * @brief CRC HAL module driver. + * @{ + */ + +#ifdef HAL_CRC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup CRC_Private_Functions CRC Private Functions + * @{ + */ +static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength); +static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup CRC_Exported_Functions CRC Exported Functions + * @{ + */ + +/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions. + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initialize the CRC according to the specified parameters + in the CRC_InitTypeDef and create the associated handle + (+) DeInitialize the CRC peripheral + (+) Initialize the CRC MSP (MCU Specific Package) + (+) DeInitialize the CRC MSP + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the CRC according to the specified + * parameters in the CRC_InitTypeDef and create the associated handle. + * @param hcrc CRC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc) +{ + /* Check the CRC handle allocation */ + if (hcrc == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance)); + + if (hcrc->State == HAL_CRC_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hcrc->Lock = HAL_UNLOCKED; + /* Init the low level hardware */ + HAL_CRC_MspInit(hcrc); + } + + hcrc->State = HAL_CRC_STATE_BUSY; + + /* check whether or not non-default generating polynomial has been + * picked up by user */ + assert_param(IS_DEFAULT_POLYNOMIAL(hcrc->Init.DefaultPolynomialUse)); + if (hcrc->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_ENABLE) + { + /* initialize peripheral with default generating polynomial */ + WRITE_REG(hcrc->Instance->POL, DEFAULT_CRC32_POLY); + MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, CRC_POLYLENGTH_32B); + } + else + { + /* initialize CRC peripheral with generating polynomial defined by user */ + if (HAL_CRCEx_Polynomial_Set(hcrc, hcrc->Init.GeneratingPolynomial, hcrc->Init.CRCLength) != HAL_OK) + { + return HAL_ERROR; + } + } + + /* check whether or not non-default CRC initial value has been + * picked up by user */ + assert_param(IS_DEFAULT_INIT_VALUE(hcrc->Init.DefaultInitValueUse)); + if (hcrc->Init.DefaultInitValueUse == DEFAULT_INIT_VALUE_ENABLE) + { + WRITE_REG(hcrc->Instance->INIT, DEFAULT_CRC_INITVALUE); + } + else + { + WRITE_REG(hcrc->Instance->INIT, hcrc->Init.InitValue); + } + + + /* set input data inversion mode */ + assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(hcrc->Init.InputDataInversionMode)); + MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, hcrc->Init.InputDataInversionMode); + + /* set output data inversion mode */ + assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(hcrc->Init.OutputDataInversionMode)); + MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, hcrc->Init.OutputDataInversionMode); + + /* makes sure the input data format (bytes, halfwords or words stream) + * is properly specified by user */ + assert_param(IS_CRC_INPUTDATA_FORMAT(hcrc->InputDataFormat)); + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief DeInitialize the CRC peripheral. + * @param hcrc CRC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc) +{ + /* Check the CRC handle allocation */ + if (hcrc == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance)); + + /* Check the CRC peripheral state */ + if (hcrc->State == HAL_CRC_STATE_BUSY) + { + return HAL_BUSY; + } + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_BUSY; + + /* Reset CRC calculation unit */ + __HAL_CRC_DR_RESET(hcrc); + + /* Reset IDR register content */ + CLEAR_BIT(hcrc->Instance->IDR, CRC_IDR_IDR); + + /* DeInit the low level hardware */ + HAL_CRC_MspDeInit(hcrc); + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_RESET; + + /* Process unlocked */ + __HAL_UNLOCK(hcrc); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initializes the CRC MSP. + * @param hcrc CRC handle + * @retval None + */ +__weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcrc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_CRC_MspInit can be implemented in the user file + */ +} + +/** + * @brief DeInitialize the CRC MSP. + * @param hcrc CRC handle + * @retval None + */ +__weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcrc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_CRC_MspDeInit can be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions + * @brief management functions. + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer + using combination of the previous CRC value and the new one. + + [..] or + + (+) compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer + independently of the previous CRC value. + +@endverbatim + * @{ + */ + +/** + * @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer + * starting with the previously computed CRC as initialization value. + * @param hcrc CRC handle + * @param pBuffer pointer to the input data buffer, exact input data format is + * provided by hcrc->InputDataFormat. + * @param BufferLength input data buffer length (number of bytes if pBuffer + * type is * uint8_t, number of half-words if pBuffer type is * uint16_t, + * number of words if pBuffer type is * uint32_t). + * @note By default, the API expects a uint32_t pointer as input buffer parameter. + * Input buffer pointers with other types simply need to be cast in uint32_t + * and the API will internally adjust its input data processing based on the + * handle field hcrc->InputDataFormat. + * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) + */ +uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength) +{ + uint32_t index; /* CRC input data buffer index */ + uint32_t temp = 0U; /* CRC output (read from hcrc->Instance->DR register) */ + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_BUSY; + + switch (hcrc->InputDataFormat) + { + case CRC_INPUTDATA_FORMAT_WORDS: + /* Enter Data to the CRC calculator */ + for (index = 0U; index < BufferLength; index++) + { + hcrc->Instance->DR = pBuffer[index]; + } + temp = hcrc->Instance->DR; + break; + + case CRC_INPUTDATA_FORMAT_BYTES: + temp = CRC_Handle_8(hcrc, (uint8_t *)pBuffer, BufferLength); + break; + + case CRC_INPUTDATA_FORMAT_HALFWORDS: + temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength); /* Derogation MisraC2012 R.11.5 */ + break; + default: + break; + } + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_READY; + + /* Return the CRC computed value */ + return temp; +} + +/** + * @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer + * starting with hcrc->Instance->INIT as initialization value. + * @param hcrc CRC handle + * @param pBuffer pointer to the input data buffer, exact input data format is + * provided by hcrc->InputDataFormat. + * @param BufferLength input data buffer length (number of bytes if pBuffer + * type is * uint8_t, number of half-words if pBuffer type is * uint16_t, + * number of words if pBuffer type is * uint32_t). + * @note By default, the API expects a uint32_t pointer as input buffer parameter. + * Input buffer pointers with other types simply need to be cast in uint32_t + * and the API will internally adjust its input data processing based on the + * handle field hcrc->InputDataFormat. + * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) + */ +uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength) +{ + uint32_t index; /* CRC input data buffer index */ + uint32_t temp = 0U; /* CRC output (read from hcrc->Instance->DR register) */ + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_BUSY; + + /* Reset CRC Calculation Unit (hcrc->Instance->INIT is + * written in hcrc->Instance->DR) */ + __HAL_CRC_DR_RESET(hcrc); + + switch (hcrc->InputDataFormat) + { + case CRC_INPUTDATA_FORMAT_WORDS: + /* Enter 32-bit input data to the CRC calculator */ + for (index = 0U; index < BufferLength; index++) + { + hcrc->Instance->DR = pBuffer[index]; + } + temp = hcrc->Instance->DR; + break; + + case CRC_INPUTDATA_FORMAT_BYTES: + /* Specific 8-bit input data handling */ + temp = CRC_Handle_8(hcrc, (uint8_t *)pBuffer, BufferLength); + break; + + case CRC_INPUTDATA_FORMAT_HALFWORDS: + /* Specific 16-bit input data handling */ + temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength); /* Derogation MisraC2012 R.11.5 */ + break; + + default: + break; + } + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_READY; + + /* Return the CRC computed value */ + return temp; +} + +/** + * @} + */ + +/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions + * @brief Peripheral State functions. + * +@verbatim + =============================================================================== + ##### Peripheral State functions ##### + =============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Return the CRC handle state. + * @param hcrc CRC handle + * @retval HAL state + */ +HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc) +{ + /* Return CRC handle state */ + return hcrc->State; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup CRC_Private_Functions + * @{ + */ + +/** + * @brief Enter 8-bit input data to the CRC calculator. + * Specific data handling to optimize processing time. + * @param hcrc CRC handle + * @param pBuffer pointer to the input data buffer + * @param BufferLength input data buffer length + * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) + */ +static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength) +{ + uint32_t i; /* input data buffer index */ + uint16_t data; + __IO uint16_t *pReg; + + /* Processing time optimization: 4 bytes are entered in a row with a single word write, + * last bytes must be carefully fed to the CRC calculator to ensure a correct type + * handling by the peripheral */ + for (i = 0U; i < (BufferLength / 4U); i++) + { + hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \ + ((uint32_t)pBuffer[(4U * i) + 1U] << 16U) | \ + ((uint32_t)pBuffer[(4U * i) + 2U] << 8U) | \ + (uint32_t)pBuffer[(4U * i) + 3U]; + } + /* last bytes specific handling */ + if ((BufferLength % 4U) != 0U) + { + if ((BufferLength % 4U) == 1U) + { + *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[4U * i]; /* Derogation MisraC2012 R.11.5 */ + } + if ((BufferLength % 4U) == 2U) + { + data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U]; + pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */ + *pReg = data; + } + if ((BufferLength % 4U) == 3U) + { + data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U]; + pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */ + *pReg = data; + + *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[(4U * i) + 2U]; /* Derogation MisraC2012 R.11.5 */ + } + } + + /* Return the CRC computed value */ + return hcrc->Instance->DR; +} + +/** + * @brief Enter 16-bit input data to the CRC calculator. + * Specific data handling to optimize processing time. + * @param hcrc CRC handle + * @param pBuffer pointer to the input data buffer + * @param BufferLength input data buffer length + * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) + */ +static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength) +{ + uint32_t i; /* input data buffer index */ + __IO uint16_t *pReg; + + /* Processing time optimization: 2 HalfWords are entered in a row with a single word write, + * in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure + * a correct type handling by the peripheral */ + for (i = 0U; i < (BufferLength / 2U); i++) + { + hcrc->Instance->DR = ((uint32_t)pBuffer[2U * i] << 16U) | (uint32_t)pBuffer[(2U * i) + 1U]; + } + if ((BufferLength % 2U) != 0U) + { + pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */ + *pReg = pBuffer[2U * i]; + } + + /* Return the CRC computed value */ + return hcrc->Instance->DR; +} + +/** + * @} + */ + +#endif /* HAL_CRC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_crc_ex.c b/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_crc_ex.c new file mode 100644 index 0000000..6f66833 --- /dev/null +++ b/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_crc_ex.c @@ -0,0 +1,223 @@ +/** + ****************************************************************************** + * @file stm32l4xx_hal_crc_ex.c + * @author MCD Application Team + * @brief Extended CRC HAL module driver. + * This file provides firmware functions to manage the extended + * functionalities of the CRC peripheral. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim +================================================================================ + ##### How to use this driver ##### +================================================================================ + [..] + (+) Set user-defined generating polynomial through HAL_CRCEx_Polynomial_Set() + (+) Configure Input or Output data inversion + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx_hal.h" + +/** @addtogroup STM32L4xx_HAL_Driver + * @{ + */ + +/** @defgroup CRCEx CRCEx + * @brief CRC Extended HAL module driver + * @{ + */ + +#ifdef HAL_CRC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup CRCEx_Exported_Functions CRC Extended Exported Functions + * @{ + */ + +/** @defgroup CRCEx_Exported_Functions_Group1 Extended Initialization/de-initialization functions + * @brief Extended Initialization and Configuration functions. + * +@verbatim + =============================================================================== + ##### Extended configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure the generating polynomial + (+) Configure the input data inversion + (+) Configure the output data inversion + +@endverbatim + * @{ + */ + + +/** + * @brief Initialize the CRC polynomial if different from default one. + * @param hcrc CRC handle + * @param Pol CRC generating polynomial (7, 8, 16 or 32-bit long). + * This parameter is written in normal representation, e.g. + * @arg for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65 + * @arg for a polynomial of degree 16, X^16 + X^12 + X^5 + 1 is written 0x1021 + * @param PolyLength CRC polynomial length. + * This parameter can be one of the following values: + * @arg @ref CRC_POLYLENGTH_7B 7-bit long CRC (generating polynomial of degree 7) + * @arg @ref CRC_POLYLENGTH_8B 8-bit long CRC (generating polynomial of degree 8) + * @arg @ref CRC_POLYLENGTH_16B 16-bit long CRC (generating polynomial of degree 16) + * @arg @ref CRC_POLYLENGTH_32B 32-bit long CRC (generating polynomial of degree 32) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t msb = 31U; /* polynomial degree is 32 at most, so msb is initialized to max value */ + + /* Check the parameters */ + assert_param(IS_CRC_POL_LENGTH(PolyLength)); + + /* check polynomial definition vs polynomial size: + * polynomial length must be aligned with polynomial + * definition. HAL_ERROR is reported if Pol degree is + * larger than that indicated by PolyLength. + * Look for MSB position: msb will contain the degree of + * the second to the largest polynomial member. E.g., for + * X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */ + while ((msb-- > 0U) && ((Pol & ((uint32_t)(0x1U) << (msb & 0x1FU))) == 0U)) + { + } + + switch (PolyLength) + { + case CRC_POLYLENGTH_7B: + if (msb >= HAL_CRC_LENGTH_7B) + { + status = HAL_ERROR; + } + break; + case CRC_POLYLENGTH_8B: + if (msb >= HAL_CRC_LENGTH_8B) + { + status = HAL_ERROR; + } + break; + case CRC_POLYLENGTH_16B: + if (msb >= HAL_CRC_LENGTH_16B) + { + status = HAL_ERROR; + } + break; + + case CRC_POLYLENGTH_32B: + /* no polynomial definition vs. polynomial length issue possible */ + break; + default: + status = HAL_ERROR; + break; + } + if (status == HAL_OK) + { + /* set generating polynomial */ + WRITE_REG(hcrc->Instance->POL, Pol); + + /* set generating polynomial size */ + MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, PolyLength); + } + /* Return function status */ + return status; +} + +/** + * @brief Set the Reverse Input data mode. + * @param hcrc CRC handle + * @param InputReverseMode Input Data inversion mode. + * This parameter can be one of the following values: + * @arg @ref CRC_INPUTDATA_INVERSION_NONE no change in bit order (default value) + * @arg @ref CRC_INPUTDATA_INVERSION_BYTE Byte-wise bit reversal + * @arg @ref CRC_INPUTDATA_INVERSION_HALFWORD HalfWord-wise bit reversal + * @arg @ref CRC_INPUTDATA_INVERSION_WORD Word-wise bit reversal + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode) +{ + /* Check the parameters */ + assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(InputReverseMode)); + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_BUSY; + + /* set input data inversion mode */ + MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, InputReverseMode); + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Set the Reverse Output data mode. + * @param hcrc CRC handle + * @param OutputReverseMode Output Data inversion mode. + * This parameter can be one of the following values: + * @arg @ref CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion (default value) + * @arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE bit-level inversion (e.g. for a 8-bit CRC: 0xB5 becomes 0xAD) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode) +{ + /* Check the parameters */ + assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(OutputReverseMode)); + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_BUSY; + + /* set output data inversion mode */ + MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, OutputReverseMode); + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + + + + +/** + * @} + */ + + +/** + * @} + */ + + +#endif /* HAL_CRC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/Makefile b/Makefile index 1506fd4..d03e6a8 100644 --- a/Makefile +++ b/Makefile @@ -1,5 +1,5 @@ ########################################################################################################################## -# File automatically-generated by tool: [projectgenerator] version: [3.17.1] date: [Tue Sep 27 08:33:11 CEST 2022] +# File automatically-generated by tool: [projectgenerator] version: [3.17.1] date: [Fri Dec 09 08:47:57 CET 2022] ########################################################################################################################## # ------------------------------------------------ @@ -75,7 +75,9 @@ Middlewares/Third_Party/FreeRTOS/Source/timers.c \ Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c \ Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c \ Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c \ -Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_iwdg.c +Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_iwdg.c \ +Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_crc.c \ +Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_crc_ex.c # ASM sources ASM_SOURCES = \ diff --git a/Middlewares/ST/EEPROM_Emul/Core/eeprom_emul.c b/Middlewares/ST/EEPROM_Emul/Core/eeprom_emul.c new file mode 100644 index 0000000..29bc03c --- /dev/null +++ b/Middlewares/ST/EEPROM_Emul/Core/eeprom_emul.c @@ -0,0 +1,2071 @@ +/** + ****************************************************************************** + * @file EEPROM_Emul/Core/eeprom_emul.c + * @author MCD Application Team + * @brief This file provides all the EEPROM emulation firmware functions. + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + This driver provides functions to initialize EEPROM emulation, to read and + write EEPROM variables, and to cleanup FLASH pages used by EEPROM emulation. + + (#) EEPROM emulation initialization functions: + (++) Format the FLASH pages used by EEPROM emulation using EE_Format(). + This function is optionally used, it can be called the very first + time EEPROM emulation is used, to prepare FLASH pages for EEPROM + emulation with empty EEPROM variables. It can also be called at + any time, to flush all EEPROM variables. + (++) Initialize EEPROM emulation, and restore the FLASH pages used by + EEPROM emulation to a known good state in case of power loss + using EE_Init(). It must be performed at system start up. + + (#) EEPROM variables access functions: + (++) Write EEPROM variable using EE_WriteVariableXbits() functions + A Clean Up request can be raised as return parameter in case + FLASH pages used by EEPROM emulation, are full. + (++) Read EEPROM variable using EE_ReadVariableXbits() functions + + (#) Clean up functions of FLASH pages, used by EEPROM emulation: + (++) There Two modes of erasing: + (+++) Polling mode using EE_CleanUp() function + (+++) Interrupt mode using EE_CleanUp_IT() function + (++) Callback function called when the clean up operation in interrupt + mode, is finished: EE_EndOfCleanup_UserCallback() + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "eeprom_emul.h" + +/** @defgroup EEPROM_Emulation EEPROM_Emulation + * @{ + */ + +/* Private define -----------------------------------------------------------*/ +#ifdef DUALCORE_FLASH_SHARING +#define HSEM_PROCESS_1 12U /* Number taken randomly to identify the process locking a semaphore in the driver context */ +#endif +/* Private typedef -----------------------------------------------------------*/ +/** @defgroup EEPROM_Private_Structures EEPROM Private Structures + * @{ + */ + +/** + * @brief EE Find Type structure definition. + */ +/* Type of find requested : + READ --> page in active state + WRITE --> page in receive state or active state + ERASE --> page in erased state */ +typedef enum { + FIND_READ_PAGE, + FIND_WRITE_PAGE, + FIND_ERASE_PAGE +} EE_Find_type; + +/** + * @brief EE State Type structure definition. + */ +/* Type of state requested : + ERASED --> page is erased + RECEIVE --> page used during data transfer when no more space available in the system + ACTIVE --> page contains valid data and is not full + VALID --> page contains valid data and is full + ERASING --> page used during transfer, should be erased after transfer + INVALID --> page invalid state */ +typedef enum { + STATE_PAGE_ERASED, + STATE_PAGE_RECEIVE, + STATE_PAGE_ACTIVE, + STATE_PAGE_VALID, + STATE_PAGE_ERASING, + STATE_PAGE_INVALID +} EE_State_type; + +/** + * @brief EE Transfer Type structure definition. + */ +/* Definition of the different type of page transfer + NORMAL -> copy data page source to page destination + RECOVER -> resume page transfer that has been interrupted */ +typedef enum { + EE_TRANSFER_NORMAL, + EE_TRANSFER_RECOVER +} EE_Transfer_type; + +/** + * @brief EE State Reliability structure definition. + */ +/* Reliability of page state: + RELIABLE -> header of page is not corrupted, state is reliable + CORRUPTED -> header of page is corrupted, state is corrupted */ +typedef enum { + STATE_RELIABLE, + STATE_CORRUPTED +} EE_State_Reliability; + + + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup EEPROM_Private_Variables EEPROM Private Variables + * @{ + */ + +/* Global variables used to store eeprom status */ +uint16_t uhNbWrittenElements = 0U; /*!< Nb of elements written in valid and active pages */ +uint8_t ubCurrentActivePage = 0U; /*!< Current active page (can be active or receive state) */ +uint32_t uwAddressNextWrite = PAGE_HEADER_SIZE; /*!< Initialize write position just after page header */ + +/* During the cleanup phase in EE_Init, AddressRead is the address being read */ +__IO uint32_t AddressRead = 0; +/* Flag equal to 1 when the cleanup phase is in progress, 0 if not */ +__IO uint8_t CleanupPhase = 0; + +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup EEPROM_Private_Functions EEPROM Private Functions + * @{ + */ + +#ifndef FLASH_LINES_128B +static EE_Status ReadVariable(uint16_t VirtAddress, EE_DATA_TYPE* pData); +static EE_Status WriteVariable(uint16_t VirtAddress, EE_DATA_TYPE Data); +static EE_Status PagesTransfer(uint16_t VirtAddress, EE_DATA_TYPE Data, EE_Transfer_type type); +uint16_t CalculateCrc(EE_DATA_TYPE Data, uint16_t VirtAddress); +#else +static EE_Status ReadVariable(uint16_t VirtAddress, EE_DATA_TYPE* pData); +static EE_Status WriteVariable(uint16_t VirtAddress, EE_DATA_TYPE* Data); +static EE_Status PagesTransfer(uint16_t VirtAddress, EE_DATA_TYPE* Data, EE_Transfer_type type); +uint16_t CalculateCrc(EE_DATA_TYPE Data1, EE_DATA_TYPE Data2); +#endif +static EE_Status VerifyPageFullyErased(uint32_t Address, uint32_t PageSize); +static uint32_t FindPage(EE_Find_type Operation); +#if defined (DUALCORE_FLASH_SHARING) +static EE_Status VerifyPagesFullWriteVariable(uint16_t VirtAddress, EE_DATA_TYPE Data, EE_Write_type Write_type); +#elif defined (FLASH_LINES_128B) +static EE_Status VerifyPagesFullWriteVariable(uint16_t VirtAddress, EE_DATA_TYPE* Data, EE_Write_type Write_type); +#else +static EE_Status VerifyPagesFullWriteVariable(uint16_t VirtAddress, EE_DATA_TYPE Data); +#endif +static EE_Status SetPageState(uint32_t Page, EE_State_type State); +static EE_State_type GetPageState(uint32_t Address); +void ConfigureCrc(void); + +/** + * @} + */ + +/* Exported functions -------------------------------------------------------*/ +/** @addtogroup EEPROM_Exported_Functions + * @{ + */ + +/** + * @brief Restore the pages to a known good state in case of power loss. + * If a page is in RECEIVE state, resume transfer. + * Then if some pages are ERASING state, erase these pages. + * @param EraseType: Type of erase to apply on page requiring to be erased. + * This parameter can be one of the following values: + * @arg @ref EE_FORCED_ERASE pages to erase are erased unconditionnally + * @arg @ref EE_CONDITIONAL_ERASE pages to erase are erased only if not fully erased + * @retval EE_Status + * - EE_OK in case of success + * - EE error code in case of error + */ +EE_Status EE_Init(EE_Erase_type EraseType) +{ + EE_State_type pagestatus = STATE_PAGE_INVALID; + uint32_t page = 0U, pageaddress = 0U, varidx = 0U, + nbactivepage = 0U, nbactivereceivepage = 0U, nbvalidpage = 0U, + lastvalidpage = 0U, firstvalidpage = 0U, + recoverytransfer = 0U; + EE_ELEMENT_TYPE addressvalue = 0U; +#ifdef FLASH_LINES_128B + uint32_t Address = 0U; + EE_ELEMENT_TYPE addressvalue2 = 0U; + EE_DATA_TYPE dummy_data[2] = {0, 0}; +#endif + EE_State_Reliability pagestate = STATE_RELIABLE; + + EE_Status status = EE_OK; + + /* Check if the configuration is 128-bits bank or 2*64-bits bank */ + if (FI_CheckBankConfig() != EE_OK) + { + return EE_INVALID_BANK_CFG; + } + + /***************************************************************************/ + /* Step 0: Perform initial configuration */ + /***************************************************************************/ + /* Configure CRC peripheral for eeprom emulation usage */ + + ConfigureCrc(); + + /***************************************************************************/ + /* Step 1: Read all lines of the flash pages of eeprom emulation to */ + /* delete corrupted lines detectable through NMI */ + /***************************************************************************/ + /* We set the flag indicating the cleanup phase is operating to 1 */ + + CleanupPhase = 1; + for (page = START_PAGE; page < (START_PAGE + PAGES_NUMBER); page++) + { + pageaddress = PAGE_ADDRESS(page); + for (varidx = 0U; varidx < PAGE_SIZE; varidx += EE_ELEMENT_SIZE) + { + /* + During the cleanup phase and only during it, + we save the address read to set its content to 0 in case it triggered an NMI (see NMI_Handler in stm32lxxx_it.c). + In the rest of the program, we do nothing in case a NMI is triggers by a reading because no NMI should be triggered + since we have cleanup the EEPROM emulated. By the way, there is still the CRC code associated to each EEPROM line + that allows to verify its valid state. + */ + AddressRead = pageaddress + varidx; + addressvalue = (*(__IO EE_ELEMENT_TYPE*)(pageaddress + varidx)); + +#ifdef FLASH_LINES_128B + AddressRead = pageaddress + varidx + 8; + addressvalue = (*(__IO EE_ELEMENT_TYPE*)(pageaddress + varidx + 8)); +#endif + + } + } +#ifdef FLASH_LINES_128B + //If a reset occured when an ECCC was detected but not corrected + if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_ECCC)) + { + Address=(0x8000000|(FLASH->ECCR & 0x000FFFFF)); //Recovery of address where ECC error occured + EE_DeleteCorruptedFlashAddress(Address); //Delete corrupted address + } +#endif + /* We set the flag indicating the cleanup phase is operating to 0 because it just ended */ + CleanupPhase = 0; + + /***************************************************************************/ + /* Step 2: Handle case of reset during transfer with no receive page */ + /* present, by setting missing receive page state */ + /***************************************************************************/ + /* Check if no active page and no receive page present */ + /* Browse all pages */ + + for (page = START_PAGE; page < (START_PAGE + PAGES_NUMBER); page++) + { + pageaddress = PAGE_ADDRESS(page); + pagestatus = GetPageState(pageaddress); + + /* Search for active and receive page */ + if ((pagestatus == STATE_PAGE_ACTIVE) || (pagestatus == STATE_PAGE_RECEIVE)) + { + nbactivereceivepage++; + } + /* Keep index of first valid page, and last valid page */ + else if (pagestatus == STATE_PAGE_VALID) + { + if (nbvalidpage == 0U) + { + firstvalidpage = page; + } + lastvalidpage = page; + nbvalidpage++; + } + } + + /* Check if no active and no receive page have been detected */ + if (nbactivereceivepage == 0U) + { + /* Check if valid pages have been detected */ + if (nbvalidpage > 0U) + { + /* Check state of page just before first valid page. + If it is erasing page, then page after last valid page shall be set + to receiving state */ + if (GetPageState(PAGE_ADDRESS(PREVIOUS_PAGE(firstvalidpage))) == STATE_PAGE_ERASING) + { + if (SetPageState(FOLLOWING_PAGE(lastvalidpage), STATE_PAGE_RECEIVE) != EE_OK) + { + return EE_WRITE_ERROR; + } + } + } + /* Format flash pages used for eeprom emulation in case no active, no receive, no valid pages are found */ + else + { + return EE_Format(EE_FORCED_ERASE); + } + } + + /*********************************************************************/ + /* Step 3: Handle case of reset during transfer, by performing */ + /* transfer recovery */ + /*********************************************************************/ + + /* Browse all pages */ + for (page = START_PAGE; page < (START_PAGE + PAGES_NUMBER); page++) + { + pageaddress = PAGE_ADDRESS(page); + pagestatus = GetPageState(pageaddress); + + /* Check if there is receive page, meaning transfer has been interrupted */ + if (pagestatus == STATE_PAGE_RECEIVE) + { + /* Verify that receive page is a true one, not a corrupted page state */ + /* Check if page is not the first page of a bloc */ + if ((page != START_PAGE) && (page != (uint32_t)(START_PAGE + (PAGES_NUMBER / 2U)))) + { + /* Check that previous page is valid state */ + if (GetPageState(PAGE_ADDRESS(PREVIOUS_PAGE(page))) == STATE_PAGE_VALID) + { + /* The receive page is a true receive page */ + pagestate = STATE_RELIABLE; + } + else /* Previous page is not valid state */ + { + /* The receive page is false receive page due to header corruption */ + pagestate = STATE_CORRUPTED; + } + } + else /* The receive page is the first page of a bloc */ + { + /* Check that following page is erased state */ + if (GetPageState(PAGE_ADDRESS(FOLLOWING_PAGE(page))) == STATE_PAGE_ERASED) + { + /* The receive page is a true receive page */ + pagestate = STATE_RELIABLE; + } + else /* Following page is not erased state */ + { + /* The receive page is false receive page due to header corruption */ + pagestate = STATE_CORRUPTED; + } + } + + /* If the receive page is a true receive page, resume pages transfer */ + if (pagestate == STATE_RELIABLE) + { + /* Initialize current active page */ + ubCurrentActivePage = page; + + /* Resume the interrupted page transfer, using dummy new data */ +#ifndef FLASH_LINES_128B + if (PagesTransfer(0U, 0U, EE_TRANSFER_RECOVER) != EE_CLEANUP_REQUIRED) + { + return EE_TRANSFER_ERROR; + } +#else + if (PagesTransfer(0U, dummy_data, EE_TRANSFER_RECOVER) != EE_CLEANUP_REQUIRED) + { + return EE_TRANSFER_ERROR; + } +#endif + /* Memorize transfer recovery occured */ + recoverytransfer = 1U; + + /* transfer recovery is done, then stop searching receive page */ + break; + } + } + } + + /*********************************************************************/ + /* Step 4: Verify presence of one unique active page */ + /* If more than one active page, raise error */ + /* If no active page present, set missing active page */ + /*********************************************************************/ + + /* Browse all pages to search for active pages */ + nbactivepage = 0U; + for (page = START_PAGE; page < (START_PAGE + PAGES_NUMBER); page++) + { + pageaddress = PAGE_ADDRESS(page); + pagestatus = GetPageState(pageaddress); + + /* Search for active page */ + if (pagestatus == STATE_PAGE_ACTIVE) + { + /* Verify that active page is a true one, not a corrupted page state */ + /* Check if page is not the first page of a bloc */ + if ((page != START_PAGE) && (page != (uint32_t)(START_PAGE + (PAGES_NUMBER / 2U)))) + { + /* Check that previous page is valid state */ + if (GetPageState(PAGE_ADDRESS(PREVIOUS_PAGE(page))) == STATE_PAGE_VALID) + { + /* The active page is a true active page */ + pagestate = STATE_RELIABLE; + } + else /* Previous page is not valid state */ + { + /* The active page is false active page due to header corruption */ + pagestate = STATE_CORRUPTED; + } + } + else /* The active page is the first page of a bloc */ + { + /* Check that following page is erased state */ + if (GetPageState(PAGE_ADDRESS(FOLLOWING_PAGE(page))) == STATE_PAGE_ERASED) + { + /* The active page is a true active page */ + pagestate = STATE_RELIABLE; + } + else /* Following page is not erased state */ + { + /* The active page is false active page due to header corruption */ + pagestate = STATE_CORRUPTED; + } + } + + /* If the active page is a true active page, initialize global variables */ + if (pagestate == STATE_RELIABLE) + { + if (nbactivepage == 0U) + { + ubCurrentActivePage = page; + nbactivepage++; + } + else + { + /* Error: More than one reliable active page is present */ + return EE_INVALID_PAGE_SEQUENCE; + } + } + } + /* Keep index of last valid page, will be required in case no active page is found */ + else if (pagestatus == STATE_PAGE_VALID) + { + lastvalidpage = page; + } + } + + /* In case no active page is found, set page after last valid page to active state */ + if (nbactivepage == 0U) + { + ubCurrentActivePage = FOLLOWING_PAGE(lastvalidpage); + if (SetPageState(ubCurrentActivePage, STATE_PAGE_ACTIVE) != EE_OK) + { + return EE_WRITE_ERROR; + } + } + + /*********************************************************************/ + /* Step 5: Initialize eeprom emulation global variables relative */ + /* to active page */ + /*********************************************************************/ + + /* Initialize global variables, with elements detected in active page */ + uhNbWrittenElements = 0U; + uwAddressNextWrite = PAGE_HEADER_SIZE; + + for (varidx = PAGE_HEADER_SIZE; varidx < PAGE_SIZE; varidx += EE_ELEMENT_SIZE) + { + /* Check elements present in active page */ + addressvalue = (*(__IO EE_ELEMENT_TYPE*)(PAGE_ADDRESS(ubCurrentActivePage) + varidx)); +#ifdef FLASH_LINES_128B + addressvalue2 = (*(__IO EE_ELEMENT_TYPE*)(PAGE_ADDRESS(ubCurrentActivePage) + varidx + 8)); + if ((addressvalue != EE_MASK_FULL) && (addressvalue2 != EE_MASK_FULL)) +#else + if (addressvalue != EE_MASK_FULL) +#endif + { + /* Then increment uhNbWrittenElements and uwAddressNextWrite */ + uhNbWrittenElements++; + uwAddressNextWrite += EE_ELEMENT_SIZE; + } + else /* no more element in the page */ + { + break; + } + } + + /*********************************************************************/ + /* Step 6: Finalize eeprom emulation global variables relative */ + /* to valid pages, and check consistency of pages sequence */ + /*********************************************************************/ + + /* Check consistency of pages sequence: one active page, optionnally some valid pages before */ + /* Update global variable uhNbWrittenElements if valid pages are found */ + page = ubCurrentActivePage; + firstvalidpage = ubCurrentActivePage; + while ((page != START_PAGE) && (page != (uint32_t)(START_PAGE + (PAGES_NUMBER / 2U)))) + { + /* Decrement page index among circular pages list */ + page = PREVIOUS_PAGE(page); + pagestatus = GetPageState(PAGE_ADDRESS(page)); + + /* Check if page is valid state */ + if (pagestatus == STATE_PAGE_VALID) + { + /* Update uhNbWrittenElements with number of elements in full page */ + uhNbWrittenElements += NB_MAX_ELEMENTS_BY_PAGE; + + /* Keep index of first valid page */ + firstvalidpage = page; + } + else + { + /* Error: Pages sequence is not consistent */ + return EE_INVALID_PAGE_SEQUENCE; + } + } + + /*********************************************************************/ + /* Step 7: Ensure empty pages are erased */ + /*********************************************************************/ + + /* Ensure all pages after active page, until first valid page, are erased */ + page = FOLLOWING_PAGE(ubCurrentActivePage); + pageaddress = PAGE_ADDRESS(page); + + while (page != firstvalidpage) + { + /* Check if page erase has to be forced unconditionally (default case) */ + if (EraseType == EE_FORCED_ERASE) + { + /* Force page erase independently of its content */ + if (FI_PageErase(page, 1U) != EE_OK) + { + return EE_ERASE_ERROR; + } + } + else /* EraseType == EE_CONDITIONAL_ERASE */ + { + /* Check if page is fully erased */ + if (VerifyPageFullyErased(pageaddress, PAGE_SIZE) == EE_PAGE_NOTERASED) + { + /* Erase pages if not fully erased */ + if (FI_PageErase(page, 1U) != EE_OK) + { + return EE_ERASE_ERROR; + } + } + } + + /* Increment page index among circular pages list, to get first page to erased */ + page = FOLLOWING_PAGE(page); + pageaddress = PAGE_ADDRESS(page); + } + + /* To keep their coherency, flush the caches if needed depending on the product */ + FI_CacheFlush(); + + /*********************************************************************/ + /* Step 8: Perform dummy write '0' to get rid of potential */ + /* instability of line value 0xFFFFFFFF consecutive to a */ + /* reset during write here */ + /* Only needed if recovery transfer did not occured */ + /*********************************************************************/ + +if (recoverytransfer == 0U) + { + +#ifdef DUALCORE_FLASH_SHARING + status = VerifyPagesFullWriteVariable(0U, 0U, EE_INIT_WRITE); + + // The dummy write can be skipped in case pages are full + // because in this case potential instability can not happen + if ((status != EE_OK) && (status != EE_PAGE_FULL)) + { + return EE_WRITE_ERROR; + } +#else +#ifdef FLASH_LINES_128B + uint64_t to_write[2] = {0}; + status = VerifyPagesFullWriteVariable(0U, to_write, EE_INIT_WRITE); +#else + status = VerifyPagesFullWriteVariable(0U, 0U); +#endif + // The dummy write can be skipped in case pages are full + // because in this case potential instability can not happen + if ((status != EE_OK) && (status != EE_PAGE_FULL)) + { + return EE_WRITE_ERROR; + } +#endif + } + + return EE_OK; +} + +/** + * @brief Erases all flash pages of eeprom emulation, and set first page + * header as ACTIVE. + * @note This function can be called the very first time eeprom emulation is + * used, to prepare flash pages for eeprom emulation with empty eeprom + variables. It can also be called at any time, to flush all eeprom + * variables. + * @param EraseType: Type of erase to apply on page requiring to be erased. + * This parameter can be one of the following values: + * @arg @ref EE_FORCED_ERASE pages to erase are erased unconditionnally + * @arg @ref EE_CONDITIONAL_ERASE pages to erase are erased only if not fully erased + * @retval EE_Status + * - EE_OK: on success + * - EE error code: if an error occurs + */ +EE_Status EE_Format(EE_Erase_type EraseType) +{ + uint32_t page = 0U; + + /* Check if the configuration is 128-bits bank or 2*64-bits bank */ + if (FI_CheckBankConfig() != EE_OK) + { + return EE_INVALID_BANK_CFG; + } + +#ifdef DUALCORE_FLASH_SHARING + /* Inform CPU2 about Erase Activity */ + SHCI_C2_FLASH_EraseActivity(ERASE_ACTIVITY_ON); +#endif + + /* Erase All Pages */ + for (page = START_PAGE; page < (START_PAGE + PAGES_NUMBER); page++) + { + /* Check if page erase has to be forced unconditionally (default case) */ + if (EraseType == EE_FORCED_ERASE) + { + /* Force page erase independently of its content */ + if (FI_PageErase(page, 1U) != EE_OK) + { +#ifdef DUALCORE_FLASH_SHARING + /* Inform CPU2 about end of Erase Activity */ + SHCI_C2_FLASH_EraseActivity(ERASE_ACTIVITY_OFF); +#endif + return EE_ERASE_ERROR; + } + } + else /* EraseType == EE_CONDITIONAL_ERASE */ + { + /* Check if Page is not yet fully erased */ + if (VerifyPageFullyErased(PAGE_ADDRESS(page), PAGE_SIZE) == EE_PAGE_NOTERASED) + { + /* Erase the page */ + /* If Erase operation was failed, a Flash error code is returned */ + if (FI_PageErase(page, 1U) != EE_OK) + { +#ifdef DUALCORE_FLASH_SHARING + /* Inform CPU2 about end of Erase Activity */ + SHCI_C2_FLASH_EraseActivity(ERASE_ACTIVITY_OFF); +#endif + return EE_ERASE_ERROR; + } + } + } + } + + /* To keep their coherency, flush the caches if needed depending on the product */ + FI_CacheFlush(); + +#ifdef DUALCORE_FLASH_SHARING + /* Inform CPU2 about end of Erase Activity */ + SHCI_C2_FLASH_EraseActivity(ERASE_ACTIVITY_OFF); +#endif + + /* Set first Page in Active State */ + /* If program operation was failed, a Flash error code is returned */ + if (SetPageState(START_PAGE, STATE_PAGE_ACTIVE) != EE_OK) + { + return EE_WRITE_ERROR; + } + + /* Reset global variables */ + uhNbWrittenElements = (uint16_t)0U; + ubCurrentActivePage = START_PAGE; + uwAddressNextWrite = PAGE_HEADER_SIZE; /* Initialize write position just after page header */ + + return EE_OK; +} + +#if defined(FLASH_LINES_128B) +/** + * @brief Returns the last stored variable data, if found, which correspond to + * the passed virtual address + * @param VirtAddress Variable virtual address on 16 bits (can't be 0x0000 or 0xFFFF) + * @param Data 96bits data to be written pointed by a uin64_t pointer + * @retval EE_Status + * - EE_OK: if variable was found + * - EE error code: if an error occurs + */ +EE_Status EE_ReadVariable96bits(uint16_t VirtAddress, uint64_t* pData) +{ + if((VirtAddress != 0x0000) && (VirtAddress != 0xFFFF)) + { + EE_Status status = EE_OK; + + /* Read variable of size EE_DATA_TYPE */ + status = ReadVariable(VirtAddress, pData); + + return status; + } + else + { + return EE_INVALID_VIRTUALADDRESS; + } +} +#endif + +#if defined(EE_ACCESS_32BITS) +/** + * @brief Returns the last stored variable data, if found, which correspond to + * the passed virtual address + * @param VirtAddress Variable virtual address on 16 bits (can't be 0x0000 or 0xFFFF) + * @param pData Variable containing the 32bits read variable value + * @retval EE_Status + * - EE_OK: if variable was found + * - EE error code: if an error occurs + */ +EE_Status EE_ReadVariable32bits(uint16_t VirtAddress, uint32_t* pData) +{ + if((VirtAddress != 0x0000) && (VirtAddress != 0xFFFF)) + { + EE_DATA_TYPE datatmp = 0U; + EE_Status status = EE_OK; + + /* Read variable of size EE_DATA_TYPE, then cast it to 32bits */ + status = ReadVariable(VirtAddress, &datatmp); + *pData = (uint32_t) datatmp; + + return status; + } + else + { + return EE_INVALID_VIRTUALADDRESS; + } +} +#endif + +/** + * @brief Returns the last stored variable data, if found, which correspond to + * the passed virtual address + * @param VirtAddress Variable virtual address on 16 bits (can't be 0x0000 or 0xFFFF) + * @param pData Variable containing the 16bits read variable value + * @retval EE_Status + * - EE_OK: if variable was found + * - EE error code: if an error occurs + */ +EE_Status EE_ReadVariable16bits(uint16_t VirtAddress, uint16_t* pData) +{ + if((VirtAddress != 0x0000) && (VirtAddress != 0xFFFF)) + { + EE_DATA_TYPE datatmp = 0U; + EE_Status status = EE_OK; + + /* Read variable of size EE_DATA_TYPE, then cast it to 16bits */ + status = ReadVariable(VirtAddress, &datatmp); + *pData = (uint16_t) datatmp; + + return status; + } + else + { + return EE_INVALID_VIRTUALADDRESS; + } +} + +/** + * @brief Returns the last stored variable data, if found, which correspond to + * the passed virtual address + * @param VirtAddress Variable virtual address on 16 bits (can't be 0x0000 or 0xFFFF) + * @param pData Variable containing the 8bits read variable value + * @retval EE_Status + * - EE_OK: if variable was found + * - EE error code: if an error occurs + */ +EE_Status EE_ReadVariable8bits(uint16_t VirtAddress, uint8_t* pData) +{ + if((VirtAddress != 0x0000) && (VirtAddress != 0xFFFF)) + { + EE_DATA_TYPE datatmp = 0U; + EE_Status status = EE_OK; + + /* Read variable of size EE_DATA_TYPE, then cast it to 8bits */ + status = ReadVariable(VirtAddress, &datatmp); + *pData = (uint8_t) datatmp; + + return status; + } + else + { + return EE_INVALID_VIRTUALADDRESS; + } +} + +#if defined(FLASH_LINES_128B) +/** + * @brief Writes/updates variable data in EEPROM. + * Trig internal Pages transfer if half of the pages are full. + * @warning This function is not reentrant + * @param VirtAddress Variable virtual address on 16 bits (can't be 0x0000 or 0xFFFF) + * @param Data 96bits data to be written pointed by a uin64_t pointer + * @retval EE_Status + * - EE_OK: on success + * - EE_CLEANUP_REQUIRED: success and user has to trig flash pages cleanup + * - EE error code: if an error occurs + */ +EE_Status EE_WriteVariable96bits(uint16_t VirtAddress, uint64_t* Data) +{ + if((VirtAddress != 0x0000) && (VirtAddress != 0xFFFF)) + { + return WriteVariable(VirtAddress, (EE_DATA_TYPE*)Data); + } + else + { + return EE_INVALID_VIRTUALADDRESS; + } +} +#endif + +#if defined(EE_ACCESS_32BITS) +/** + * @brief Writes/updates variable data in EEPROM. + * Trig internal Pages transfer if half of the pages are full. + * @warning This function is not reentrant + * @param VirtAddress Variable virtual address on 16 bits (can't be 0x0000 or 0xFFFF) + * @param Data 32bits data to be written + * @retval EE_Status + * - EE_OK: on success + * - EE_CLEANUP_REQUIRED: success and user has to trig flash pages cleanup + * - EE error code: if an error occurs + */ +EE_Status EE_WriteVariable32bits(uint16_t VirtAddress, uint32_t Data) +{ + if((VirtAddress != 0x0000) && (VirtAddress != 0xFFFF)) + { +#ifndef FLASH_LINES_128B + return WriteVariable(VirtAddress, (EE_DATA_TYPE) Data); +#else + return WriteVariable(VirtAddress, (EE_DATA_TYPE*) &Data); +#endif + } + else + { + return EE_INVALID_VIRTUALADDRESS; + } +} +#endif + +/** + * @brief Writes/updates variable data in EEPROM. + * Trig internal Pages transfer if half of the pages are full. + * @warning This function is not reentrant + * @param VirtAddress Variable virtual address on 16 bits (can't be 0x0000 or 0xFFFF) + * @param Data 16bits data to be written + * @retval EE_Status + * - EE_OK: on success + * - EE_CLEANUP_REQUIRED: success and user has to trig flash pages cleanup + * - EE error code: if an error occurs + */ +EE_Status EE_WriteVariable16bits(uint16_t VirtAddress, uint16_t Data) +{ + if((VirtAddress != 0x0000) && (VirtAddress != 0xFFFF)) + { +#ifndef FLASH_LINES_128B + return WriteVariable(VirtAddress, (EE_DATA_TYPE) Data); +#else + return WriteVariable(VirtAddress, (EE_DATA_TYPE*) &Data); +#endif + } + else + { + return EE_INVALID_VIRTUALADDRESS; + } +} + +/** + * @brief Writes/updates variable data in EEPROM. + * Trig internal Pages transfer if half of the pages are full. + * @warning This function is not reentrant + * @param VirtAddress Variable virtual address on 16 bits (can't be 0x0000 or 0xFFFF) + * @param Data 8bits data to be written + * @retval EE_Status + * - EE_OK: on success + * - EE_CLEANUP_REQUIRED: success and user has to trig flash pages cleanup + * - EE error code: if an error occurs + */ +EE_Status EE_WriteVariable8bits(uint16_t VirtAddress, uint8_t Data) +{ + if((VirtAddress != 0x0000) && (VirtAddress != 0xFFFF)) + { +#ifndef FLASH_LINES_128B + return WriteVariable(VirtAddress, (EE_DATA_TYPE) Data); +#else + return WriteVariable(VirtAddress, (EE_DATA_TYPE*) &Data); +#endif + } + else + { + return EE_INVALID_VIRTUALADDRESS; + } +} + +/** + * @brief Erase group of pages which are erasing state, in polling mode. + * Could be either first half or second half of total pages number. + * @note This function should be called when EE_WriteVariableXXbits has + * returned EE_CLEANUP_REQUIRED status (and only in that case) + * @retval EE_Status + * - EE_OK: in case of success + * - EE error code: if an error occurs + */ +EE_Status EE_CleanUp(void) +{ + uint32_t firstpage = 0U, page = 0U; + uint32_t firstpageaddress = 0U, pageaddress = 0U; + EE_State_type firstpagestatus = STATE_PAGE_INVALID, pagestatus = STATE_PAGE_INVALID; + + /* Check first half and second half page group */ + for (firstpage = START_PAGE; firstpage < (START_PAGE + PAGES_NUMBER); firstpage += (PAGES_NUMBER / 2U)) + { + /* Check status of first page of the group */ + firstpageaddress = PAGE_ADDRESS(firstpage); + firstpagestatus = GetPageState(firstpageaddress); + + /* If first page of the group is erasing state, check that all other pages + of the group are also erasing state */ + if (firstpagestatus == STATE_PAGE_ERASING) + { + for (page = (firstpage + 1U); page < (firstpage + (PAGES_NUMBER / 2U)); page++) + { + pageaddress = PAGE_ADDRESS(page); + pagestatus = GetPageState(pageaddress); + + /* If page is not erasing, return error */ + if (pagestatus != STATE_PAGE_ERASING) + { + return EE_ERROR_NOERASING_PAGE; + } + } + +#ifdef DUALCORE_FLASH_SHARING + /* Inform CPU2 about Erase Activity */ + SHCI_C2_FLASH_EraseActivity(ERASE_ACTIVITY_ON); +#endif + + /* Erase all the pages of the group */ + /* If erase operation fails, a Flash error code is returned */ + if (FI_PageErase(firstpage, PAGES_NUMBER / 2U) != EE_OK) + { +#ifdef DUALCORE_FLASH_SHARING + /* Inform CPU2 about end of Erase Activity */ + SHCI_C2_FLASH_EraseActivity(ERASE_ACTIVITY_OFF); +#endif + return EE_ERASE_ERROR; + } + else + { +#ifdef DUALCORE_FLASH_SHARING + /* Inform CPU2 about end of Erase Activity */ + SHCI_C2_FLASH_EraseActivity(ERASE_ACTIVITY_OFF); +#endif + + /* To keep their coherency, flush the caches if needed depending on the product */ + FI_CacheFlush(); + + return EE_OK; + } + } + } + + /* Error if no erasing pages group is found */ + return EE_ERROR_NOERASING_PAGE; +} + +/** + * @brief Erase group of pages which are erasing state, in IT mode. + * Could be either first half or second half of total pages number. + * @note This function should be called when EE_WriteVariableXXbits has + * returned EE_CLEANUP_REQUIRED status (and only in that case) + * @retval EE_Status + * - EE_OK: in case of success + * - EE error code: if an error occurs + */ +EE_Status EE_CleanUp_IT(void) +{ + uint32_t firstpage = 0U, page = 0U; + uint32_t firstpageaddress = 0U, pageaddress = 0U; + EE_State_type firstpagestatus = STATE_PAGE_INVALID, pagestatus = STATE_PAGE_INVALID; + + /* Check first half and second half page group */ + for (firstpage = START_PAGE; firstpage < (START_PAGE + PAGES_NUMBER); firstpage += (PAGES_NUMBER / 2U)) + { + /* Check status of first page of the group */ + firstpageaddress = PAGE_ADDRESS(firstpage); + firstpagestatus = GetPageState(firstpageaddress); + + /* If first page of the group is erasing state, check that all other pages + of the group are also erasing state */ + if (firstpagestatus == STATE_PAGE_ERASING) + { + for (page = (firstpage + 1U); page < (firstpage + (PAGES_NUMBER / 2U)); page++) + { + pageaddress = PAGE_ADDRESS(page); + pagestatus = GetPageState(pageaddress); + + /* If page is not erasing, return error */ + if (pagestatus != STATE_PAGE_ERASING) + { + return EE_ERROR_NOERASING_PAGE; + } + } + +#ifdef DUALCORE_FLASH_SHARING + /* Inform CPU2 about Erase Activity */ + SHCI_C2_FLASH_EraseActivity(ERASE_ACTIVITY_ON); +#endif + + /* Erase all the pages of the group */ + /* If erase operation fails, a Flash error code is returned */ + if (FI_PageErase_IT(firstpage, PAGES_NUMBER / 2U) != EE_OK) + { + return EE_ERASE_ERROR; + } + else + { + /* To keep their coherency, flush the caches if needed depending on the product */ + FI_CacheFlush(); + return EE_OK; + } + } + } + + /* Error if no erasing pages group is found */ + return EE_ERROR_NOERASING_PAGE; +} + +/** + * @brief Delete corrupted Flash address, can be called under NMI. + * @param Address Address of the FLASH Memory to delete + * @retval EE_Status + * - EE_OK: on success + * - EE error code: if an error occurs + */ +EE_Status EE_DeleteCorruptedFlashAddress(uint32_t Address) +{ + return FI_DeleteCorruptedFlashAddress(Address); +} + +/** + * @brief Clean Up end of operation interrupt callback. + * @retval None + */ +__weak void EE_EndOfCleanup_UserCallback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the EE_EndOfCleanup_UserCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @addtogroup EEPROM_Private_Functions + * @{ + */ + +/** + * @brief Returns the last stored variable data, if found, which correspond to + * the passed virtual address + * @param VirtAddress Variable virtual address on 16 bits (can't be 0x0000 or 0xFFFF) + * @param pData Variable containing the EE_DATA_TYPE read variable value + * @retval EE_Status + * - EE_OK: if variable was found + * - EE error code: if an error occurs + */ +#ifndef FLASH_LINES_128B +static EE_Status ReadVariable(uint16_t VirtAddress, EE_DATA_TYPE* pData) +#else +static EE_Status ReadVariable(uint16_t VirtAddress, EE_DATA_TYPE* pData) +#endif +{ + EE_ELEMENT_TYPE addressvalue = 0U; +#ifdef FLASH_LINES_128B + EE_ELEMENT_TYPE addressvalue2 = 0U; +#endif + uint32_t page = 0U, pageaddress = 0U, counter = 0U, crc = 0U; + EE_State_type pagestate = STATE_PAGE_INVALID; + + /* Get active Page for read operation */ + page = FindPage(FIND_READ_PAGE); + + /* Check if there is no active page */ + if (page == EE_NO_PAGE_FOUND) + { + return EE_ERROR_NOACTIVE_PAGE; + } + pageaddress = PAGE_ADDRESS(page); + pagestate = GetPageState(pageaddress); + + /* Search variable in active page and valid pages until erased page is found + or in erasing pages until erased page is found */ + while ((pagestate == STATE_PAGE_ACTIVE) || (pagestate == STATE_PAGE_VALID) || (pagestate == STATE_PAGE_ERASING)) + { + /* Set counter index to last element position in the page */ + counter = PAGE_SIZE - EE_ELEMENT_SIZE; + + /* Check each page address starting from end */ + while (counter >= PAGE_HEADER_SIZE) + { + /* Get the current location content to be compared with virtual address */ + addressvalue = (*(__IO EE_ELEMENT_TYPE*)(pageaddress + counter)); +#ifndef FLASH_LINES_128B + if (addressvalue != EE_PAGESTAT_ERASED) + { + /* Compare the read address with the virtual address */ + if (EE_VIRTUALADDRESS_VALUE(addressvalue) == VirtAddress) + { + /* Calculate crc of variable data and virtual address */ + crc = CalculateCrc(EE_DATA_VALUE(addressvalue), EE_VIRTUALADDRESS_VALUE(addressvalue)); + + /* if crc verification pass, data is correct and is returned. + if crc verification fails, data is corrupted and has to be skip */ + if (crc == EE_CRC_VALUE(addressvalue)) + { + /* Get content of variable value */ + *pData = EE_DATA_VALUE(addressvalue); + + return EE_OK; + } + } + } +#else + addressvalue2 = (*(__IO EE_ELEMENT_TYPE*)(pageaddress + counter+8U)); + if ((addressvalue != EE_PAGESTAT_ERASED) && (addressvalue2 != EE_PAGESTAT_ERASED)) + { + /* Compare the read address with the virtual address */ + if (EE_VIRTUALADDRESS_VALUE(addressvalue) == VirtAddress) + { + /* Calculate crc of variable data and virtual address */ + crc = CalculateCrc((uint64_t)addressvalue2,(uint64_t)addressvalue); + + /* if crc verification pass, data is correct and is returned. + if crc verification fails, data is corrupted and has to be skip */ + if (crc == EE_CRC_VALUE(addressvalue)) + { + /* Get content of variable value */ + pData[0] = (uint64_t)addressvalue2; + pData[1] = (uint64_t)(addressvalue >> EE_DATA_SHIFT); + + return EE_OK; + } + } + } +#endif + /* Next address location */ + counter -= EE_ELEMENT_SIZE; + } + + /* Decrement page index circularly, among pages allocated to eeprom emulation */ + page = PREVIOUS_PAGE(page); + pageaddress = PAGE_ADDRESS(page); + pagestate = GetPageState(pageaddress); + } + + /* Variable is not found */ + return EE_NO_DATA; +} + +/** + * @brief Writes/updates variable data in EEPROM + * Trig internal Pages transfer if half of the pages are full + * @param VirtAddress Variable virtual address on 16 bits (can't be 0x0000 or 0xFFFF) + * @param Data EE_DATA_TYPE data to be written + * @retval EE_Status + * - EE_OK: on success, without page transfer + * - EE_CLEANUP_REQUIRED: on success, with page transfer occured + * - EE_FLASH_USED: flash currently used by CPU2 + * - EE error code: if an error occurs + */ +#ifndef FLASH_LINES_128B +static EE_Status WriteVariable(uint16_t VirtAddress, EE_DATA_TYPE Data) +#else +static EE_Status WriteVariable(uint16_t VirtAddress, EE_DATA_TYPE* Data) +#endif +{ + EE_Status status = EE_OK; + + /* Write the variable virtual address and value in the EEPROM, if not full */ +#if defined (DUALCORE_FLASH_SHARING) || defined (FLASH_LINES_128B) + status = VerifyPagesFullWriteVariable(VirtAddress, Data, EE_SIMPLE_WRITE); +#else + status = VerifyPagesFullWriteVariable(VirtAddress, Data); +#endif + if (status == EE_PAGE_FULL) + { + /* In case the EEPROM pages are full, perform Pages transfer */ + return PagesTransfer(VirtAddress, Data, EE_TRANSFER_NORMAL); + } + + /* Return last operation status */ + return status; +} + +/** + * @brief Verify if specified page is fully erased. + * @param Address page address + * @param PageSize page size + * @retval EE_Status + * - EE_PAGE_NOTERASED : if Page not erased + * - EE_PAGE_ERASED : if Page erased + */ +static EE_Status VerifyPageFullyErased(uint32_t Address, uint32_t PageSize) +{ + EE_Status readstatus = EE_PAGE_ERASED; + uint32_t counter = 0U; + + /* Check each element in the page */ + while (counter < PageSize) + { + /* Compare the read address with the virtual address */ +#ifndef FLASH_LINES_128B + if ((*(__IO EE_ELEMENT_TYPE*)(Address+counter)) != EE_PAGESTAT_ERASED) +#else + if ( ((*(__IO EE_ELEMENT_TYPE*)(Address+counter)) != EE_PAGESTAT_ERASED) && ((*(__IO EE_ELEMENT_TYPE*)(Address+counter+8U)) != EE_PAGESTAT_ERASED) ) +#endif + { + /* In case one element is not erased, reset readstatus flag */ + readstatus = EE_PAGE_NOTERASED; + } + /* Next address location */ + counter = counter + EE_ELEMENT_SIZE; + } + + /* Return readstatus value */ + return readstatus; +} + +/** + * @brief Find suitable page for read/write/erase operation. + * It also update pages state if current page is full. + * And it force cleanup if all pages are full. + * @param Operation Type of page to be requested. + * This parameter can be one of the following values: + * @arg @ref FIND_READ_PAGE return the active page index + * @arg @ref FIND_WRITE_PAGE return the write page index + * @arg @ref FIND_ERASE_PAGE return the erase page index + * @retval Page_Index + * - Page Index: on success + * - @ref EE_NO_PAGE_FOUND : if an error occurs + */ +static uint32_t FindPage(EE_Find_type Operation) +{ + EE_State_type currentpagestatus = STATE_PAGE_INVALID, followingpagestatus = STATE_PAGE_INVALID; + uint32_t currentpage = 0U, followingpage = 0U, previouspage = 0U; + + /* Get currentpage status */ + currentpage = ubCurrentActivePage; + currentpagestatus = GetPageState(PAGE_ADDRESS(currentpage)); + + /* Get followingpage status */ + followingpage = FOLLOWING_PAGE(currentpage); + followingpagestatus = GetPageState(PAGE_ADDRESS(followingpage)); + + /* Get previouspage status */ + previouspage = PREVIOUS_PAGE(currentpage); + + /* Write, read or erase operation */ + switch (Operation) + { + case FIND_WRITE_PAGE: /* ---- Write operation ---- */ + /* Normal operation, no page transfer on going */ + if (currentpagestatus == STATE_PAGE_ACTIVE) + { + /* Check if active page is not full */ + if (uwAddressNextWrite < PAGE_SIZE) + { + /* Return current Active page */ + return currentpage; + } + else + /* No more space in current active page */ + { + /* Check if following page is erasing state */ + if (followingpagestatus == STATE_PAGE_ERASING) + { + /* Force Cleanup, as not yet performed by user */ + if (EE_CleanUp() != EE_OK) + { + return EE_NO_PAGE_FOUND; + } + } + + /* Set current active page in valid state */ + if (SetPageState(currentpage, STATE_PAGE_VALID) != EE_OK) + { + return EE_NO_PAGE_FOUND; + } + + /* Set following page as active */ + if (SetPageState(followingpage, STATE_PAGE_ACTIVE) != EE_OK) + { + return EE_NO_PAGE_FOUND; + } + uwAddressNextWrite = PAGE_HEADER_SIZE; /* Skip page header */ + return followingpage; /* Following page is now active one */ + } + } + /* Transfer is on going, page receiving data */ + else + { + if (currentpagestatus == STATE_PAGE_RECEIVE) + { + /* Check if receive page is not full */ + if (uwAddressNextWrite < PAGE_SIZE) + { + /* Return current receive page */ + return currentpage; + } + else + /* No more space in current receive page */ + { + /* Check if following page is erasing state */ + if (followingpagestatus == STATE_PAGE_ERASING) + { + /* Force Cleanup, as not yet performed by user */ + if (EE_CleanUp() != EE_OK) + { + return EE_NO_PAGE_FOUND; + } + } + + /* Set current receive page in valid state */ + if (SetPageState(currentpage, STATE_PAGE_VALID) != EE_OK) + { + return EE_NO_PAGE_FOUND; + } + + /* Set following page as receive */ + if (SetPageState(followingpage, STATE_PAGE_RECEIVE) != EE_OK) + { + return EE_NO_PAGE_FOUND; + } + uwAddressNextWrite = PAGE_HEADER_SIZE; /* Skip page header */ + return followingpage; /* Following page is now active one */ + } + } + else + { + return EE_NO_PAGE_FOUND; /* No active Page */ + } + } + + case FIND_READ_PAGE: /* ---- Read operation ---- */ + if (currentpagestatus == STATE_PAGE_ACTIVE) + { + return currentpage; + } + else + { + if (currentpagestatus == STATE_PAGE_RECEIVE) + { + return previouspage; + } + else + { + return EE_NO_PAGE_FOUND; /* No active Page */ + } + } + + case FIND_ERASE_PAGE: /* ---- Return the erased page */ + if (followingpagestatus == STATE_PAGE_ERASED) + { + return followingpage; + } + else + { + return EE_NO_PAGE_FOUND; /* No erased Page */ + } + + default: + ; + } + + return EE_NO_PAGE_FOUND; +} + +/** + * @brief Writes a new variable data in fresh new page in case of normal + * transfer, and transfers last updated elements from full pages to + * empty pages in any cases. + * @param VirtAddress 16 bit virtual address of the new variable data + * @param Data @ref EE_DATA_TYPE data value of the new variable data + * @param Type Type of transfer. + * This parameter can be one of the EE_Transfer_type enum values. + * @arg @ref EE_TRANSFER_NORMAL Pages transfer during normal processing + * @arg @ref EE_TRANSFER_RECOVER Recovering pages transfer at Init + * @retval EE_Status + * - EE_CLEANUP_REQUIRED: on success + * - EE error code: if an error occurs + */ +#ifndef FLASH_LINES_128B +static EE_Status PagesTransfer(uint16_t VirtAddress, EE_DATA_TYPE Data, EE_Transfer_type Type) +#else +static EE_Status PagesTransfer(uint16_t VirtAddress, EE_DATA_TYPE* Data, EE_Transfer_type Type) +#endif +{ + EE_State_type pagestatus = STATE_PAGE_INVALID; + uint32_t pageaddress = 0U; + uint32_t page = 0U; + uint32_t varidx = 0U; + EE_ELEMENT_TYPE addressvalue = 0U; +#ifdef FLASH_LINES_128B + EE_ELEMENT_TYPE addressvalue2 = 0U; + uint16_t nb_dummy_lines=0U; +#endif + EE_Status status = EE_OK; + EE_DATA_TYPE DataValue = 0U; + + + /* Get receive Page for transfer operation */ + page = FindPage((Type == EE_TRANSFER_NORMAL?FIND_ERASE_PAGE:FIND_WRITE_PAGE)); + if (page == EE_NO_PAGE_FOUND) + { + return EE_ERROR_NOERASE_PAGE; + } + + /* Reinitialize number of data written in the pages, and current active page */ + uhNbWrittenElements = 0U; + ubCurrentActivePage = page; + uwAddressNextWrite = PAGE_HEADER_SIZE; + + /* Mark the erased page at receive state in case of normal transfer */ + /* It is already the case in recover transfer case */ + /* If program operation was failed, a Flash error code is returned */ + if (Type == EE_TRANSFER_NORMAL) + { + if (SetPageState(page, STATE_PAGE_RECEIVE) != EE_OK) + { + return EE_WRITE_ERROR; + } + } + + /* Set the previous active page and all previous valid pages to erasing state */ + /* In case of recover transfer, some of these pages may already be marked erasing */ + page = PREVIOUS_PAGE(page); + pageaddress = PAGE_ADDRESS(page); + pagestatus = GetPageState(pageaddress); + + if ((pagestatus == STATE_PAGE_ACTIVE) || (pagestatus == STATE_PAGE_ERASING)) + { + /* Set active page to erasing */ + if (pagestatus == STATE_PAGE_ACTIVE) + { + if (SetPageState(page, STATE_PAGE_ERASING) != EE_OK) + { + return EE_WRITE_ERROR; + } + } + + /* Inspect the previous pages to set all valid pages to erasing state */ + /* In case of recover, some valid pages may be already erasing state */ + page = PREVIOUS_PAGE(page); + pageaddress = PAGE_ADDRESS(page); + pagestatus = GetPageState(pageaddress); + + while ((pagestatus == STATE_PAGE_VALID) || (pagestatus == STATE_PAGE_ERASING)) + { + /* Set valid page to erasing */ + if (pagestatus == STATE_PAGE_VALID) + { + if (SetPageState(page, STATE_PAGE_ERASING) != EE_OK) + { + return EE_WRITE_ERROR; + } + } + + /* decrement page index */ + page = PREVIOUS_PAGE(page); + pageaddress = PAGE_ADDRESS(page); + pagestatus = GetPageState(pageaddress); + } + } + else + { + if ((Type == EE_TRANSFER_RECOVER) && (pagestatus == STATE_PAGE_VALID)) + { + /* This can happen in case of recover transfer. It indicates that previous */ + /* transfer goes far enough to fill a complete receive page at least */ + /* (valid state). Then erasing state marking was already completed */ + } + else + { + /* Inconsistent previous page state */ + return EE_INVALID_PAGE_SEQUENCE; + } + } + + /* In case of recover transfer, transfer must be resumed where it has been stopped */ + /* Update global variables to reflect current transfer status */ + if (Type == EE_TRANSFER_RECOVER) + { +#ifdef FLASH_LINES_128B + nb_dummy_lines=0; +#endif + /* Count number of elements already transferred in current receive page */ + for (varidx = PAGE_HEADER_SIZE; varidx < PAGE_SIZE; varidx += EE_ELEMENT_SIZE) + { + /* Get next element in receive page */ + addressvalue = (*(__IO EE_ELEMENT_TYPE*)(PAGE_ADDRESS(ubCurrentActivePage) + varidx)); + +#ifdef FLASH_LINES_128B + addressvalue2 = (*(__IO EE_ELEMENT_TYPE*)(PAGE_ADDRESS(ubCurrentActivePage) + varidx + 8)); + + /* Check if element is valid */ + if((addressvalue == 0x0000000000000000U)&& (addressvalue2 == 0x0000000000000000U)) + { + nb_dummy_lines++; + uhNbWrittenElements++; + uwAddressNextWrite += EE_ELEMENT_SIZE; + } + else if ((addressvalue != EE_PAGESTAT_ERASED) && (addressvalue2 != EE_PAGESTAT_ERASED)&&(addressvalue != 0x0000000000000000U)&& (addressvalue2 != 0x0000000000000000U)) +#else + if (addressvalue != EE_PAGESTAT_ERASED) +#endif + { + /* Update global variables accordingly */ + uhNbWrittenElements++; + uwAddressNextWrite += EE_ELEMENT_SIZE; + } + else + { + break; + } + } + + /* Count number of elements already transferred in previous valid pages */ + page = ubCurrentActivePage; + for (varidx = 0U; varidx < PAGES_NUMBER; varidx++) + { + /* Decrement page index among circular pages list */ + page = PREVIOUS_PAGE(page); + pagestatus = GetPageState(PAGE_ADDRESS(page)); + + /* Check if page is valid state */ + if (pagestatus == STATE_PAGE_VALID) + { + /* Update uhNbWrittenElements with number of elements in page */ + uhNbWrittenElements += NB_MAX_ELEMENTS_BY_PAGE; +#ifdef FLASH_LINES_128B + nb_dummy_lines=nb_dummy_lines+2; +#endif + } + else + { + break; + } + } + } + +#if defined (DUALCORE_FLASH_SHARING) || defined (FLASH_LINES_128B) + if (VerifyPagesFullWriteVariable(VirtAddress, Data, EE_TRANSFER) != EE_OK) + { + return EE_WRITE_ERROR; + } + #ifdef FLASH_LINES_128B + else + { + if ((Data[0]==0)&&(Data[1]==0)) + { + nb_dummy_lines++; //One 128bit line of zeros has been written + } + } + #endif +#else + + // Write the variable passed as parameter in the new active page + // If program operation was failed, a Flash error code is returned + if (VerifyPagesFullWriteVariable(VirtAddress, Data) != EE_OK) + { + return EE_WRITE_ERROR; + } + +#endif + + + /* Transfer process: transfer variables from old to the new active page */ + /* First element in receive page can be any one, the following elements are */ + /* ordered from the beginning. */ + /* In case of recovery, Pre-Last element in receive page could be */ + /* corrupted if reset occured during write of this element, */ + /* and last element is dummy value that we have just written. */ + /* Transfer shall then resume from (uhNbWrittenElements-3) variable index */ + + +#ifdef FLASH_LINES_128B + varidx = (uhNbWrittenElements >= 3U?(uhNbWrittenElements-3U+1U):1U); + for (varidx = (varidx >= nb_dummy_lines?(varidx-nb_dummy_lines):1U); varidx < NB_OF_VARIABLES+1; varidx++) +#else + for (varidx = (uhNbWrittenElements >= 3U?(uhNbWrittenElements-3U+1U):1U); varidx < NB_OF_VARIABLES+1; varidx++) +#endif + { + /* Check each variable except the one passed as parameter */ + if (varidx != VirtAddress) + { + /* Read the last variable updates */ + status = ReadVariable(varidx, &DataValue); + if (status == EE_OK) + { + /* In case variable corresponding to the virtual address was found */ + /* Transfer the variable to the new active page */ + /* If program operation was failed, a Flash error code is returned */ + #if defined (DUALCORE_FLASH_SHARING) + status = VerifyPagesFullWriteVariable(varidx, DataValue, EE_TRANSFER); + #elif defined (FLASH_LINES_128B) + status = VerifyPagesFullWriteVariable(varidx, &DataValue, EE_TRANSFER); + #else + status = VerifyPagesFullWriteVariable(varidx, DataValue); + #endif + if (status != EE_OK) + { + return status; + } + } + else + { + if (status != EE_NO_DATA) + { + /* In case variable is not found , do nothing */ + /* Any other status is error code occurs during variable read */ + return status; + } + } + } + } + + /* Transfer is now done, mark the receive state page as active */ + if (SetPageState(ubCurrentActivePage, STATE_PAGE_ACTIVE) != EE_OK) + { + return EE_WRITE_ERROR; + } + + /* Return last operation flash status */ + return EE_CLEANUP_REQUIRED; +} + +/** + * @brief Verify if pages are full + * then if not the case, writes variable in EEPROM. + * @param VirtAddress 16 bit virtual address of the variable + * @param Data @ref EE_DATA_TYPE data to be written as variable value + * @param Write_type Type of writing on going (see EE_Write_type) + * @retval EE_Status + * - EE_OK: on success + * - EE_FULL: if half pages are full + * - EE_FLASH_USED: flash currently used by CPU2 + * - EE error code: if an error occurs + */ +#if defined (DUALCORE_FLASH_SHARING) +static EE_Status VerifyPagesFullWriteVariable(uint16_t VirtAddress, EE_DATA_TYPE Data, EE_Write_type Write_type) +#elif defined (FLASH_LINES_128B) +static EE_Status VerifyPagesFullWriteVariable(uint16_t VirtAddress, EE_DATA_TYPE* Data, EE_Write_type Write_type) +#else +static EE_Status VerifyPagesFullWriteVariable(uint16_t VirtAddress, EE_DATA_TYPE Data) +#endif +{ +#ifndef FLASH_LINES_128B + uint32_t crc = 0U; +#else + uint64_t pData64[2] = {0,0}; + uint64_t crc = 0U; +#endif + + /* Check if pages are full, i.e. max number of written elements achieved */ + if (uhNbWrittenElements >= NB_MAX_WRITTEN_ELEMENTS) + { + return EE_PAGE_FULL; + } + + /* Get active Page for write operation */ + uint32_t activepage = FindPage(FIND_WRITE_PAGE); + uint32_t activepageaddress = 0U; + + /* Check if there is no active page */ + if (activepage == EE_NO_PAGE_FOUND) + { + return EE_ERROR_NOACTIVE_PAGE; + } + + activepageaddress = PAGE_ADDRESS(activepage); + + /* Force crc to 0 in case of Data/VirtAddress are 0*/ +#ifndef FLASH_LINES_128B + if ((Data == 0U) && (VirtAddress == 0U)) +#else + if ((Data[0] == 0U) && (Data[1] == 0U) && (VirtAddress == 0U)) + +#endif + { + crc = 0U; + } + else + { +#ifndef FLASH_LINES_128B + /* Calculate crc of variable data and virtual address */ + crc = CalculateCrc(Data, VirtAddress); +#else + pData64[0] = (uint64_t)((Data[1] << EE_DATA_SHIFT) | VirtAddress); + /* Calculate crc of variable data and virtual address */ + crc = CalculateCrc(Data[0], pData64[0]); +#endif + } + + +#if defined (DUALCORE_FLASH_SHARING) + /* Program variable data + virtual address + crc */ + /* If program operation was failed, a Flash error code or the information + about the semaphore monitoring flash being taken is returned */ + EE_Status ee_status = FI_WriteDoubleWord(activepageaddress+uwAddressNextWrite, EE_ELEMENT_VALUE(VirtAddress,Data,crc), Write_type); + if (ee_status != EE_OK) return ee_status; +#elif defined (FLASH_LINES_128B) + pData64[0] = 0; + pData64[1] = 0; + pData64[0] = (uint64_t)((Data[1]<< EE_DATA_SHIFT) | (crc << EE_CRC_SHIFT) | VirtAddress); + pData64[1] = (uint64_t)Data[0]; + + EE_Status ee_status = FI_WriteDoubleWord(activepageaddress+uwAddressNextWrite, pData64, Write_type); + if (ee_status != EE_OK) return ee_status; +#else + /* Program variable data + virtual address + crc */ + /* If program operation was failed, a Flash error code is returned */ + if (FI_WriteDoubleWord(activepageaddress+uwAddressNextWrite, EE_ELEMENT_VALUE(VirtAddress,Data,crc)) != HAL_OK) + { + return EE_WRITE_ERROR; + } +#endif + + /* Increment global variables relative to write operation done*/ + uwAddressNextWrite += EE_ELEMENT_SIZE; + uhNbWrittenElements++; + + return EE_OK; +} + +/** + * @brief Set page state in page header + * @param Page Index of the page + * @param State State of the page + * @retval EE_Status + * - EE_OK: on success + * - EE error code: if an error occurs + */ +static EE_Status SetPageState(uint32_t Page, EE_State_type State) +{ + uint32_t header1 = 0U, header2 = 0U, header3 = 0U, header4 = 0U; + + header1 = PAGE_ADDRESS(Page); + header2 = PAGE_ADDRESS(Page) + EE_ELEMENT_SIZE; + header3 = PAGE_ADDRESS(Page) + (EE_ELEMENT_SIZE*2U); + header4 = PAGE_ADDRESS(Page) + (EE_ELEMENT_SIZE*3U); + +#if defined (DUALCORE_FLASH_SHARING) + EE_Status ee_status; + switch(State) + { + case STATE_PAGE_RECEIVE: + { + /* Set new Page status to STATE_PAGE_RECEIVE status */ + ee_status = FI_WriteDoubleWord(header1, EE_PAGESTAT_RECEIVE, EE_SET_PAGE); + if (ee_status != EE_OK) return ee_status; + ubCurrentActivePage = Page; + } + break; + case STATE_PAGE_ACTIVE: + { + /* Set new Page status to STATE_PAGE_ACTIVE status */ + ee_status = FI_WriteDoubleWord(header2, EE_PAGESTAT_ACTIVE, EE_SET_PAGE); + if (ee_status != EE_OK) return ee_status; + ubCurrentActivePage = Page; + } + break; + case STATE_PAGE_VALID: + { + /* Set new Page status to STATE_PAGE_VALID status */ + ee_status = FI_WriteDoubleWord(header3, EE_PAGESTAT_VALID, EE_SET_PAGE); + if (ee_status != EE_OK) return ee_status; + } + break; + case STATE_PAGE_ERASING: + { + /* Set new Page status to STATE_PAGE_ERASING status */ + ee_status = FI_WriteDoubleWord(header4, EE_PAGESTAT_ERASING, EE_SET_PAGE); + if (ee_status != EE_OK) return ee_status; + } + break; + default: + break; + } +#elif defined (FLASH_LINES_128B) + EE_Status ee_status; + uint64_t pagestat = 0; + switch(State) + { + case STATE_PAGE_RECEIVE: + { + /* Set new Page status to STATE_PAGE_RECEIVE status */ + pagestat = EE_PAGESTAT_RECEIVE; + ee_status = FI_WriteDoubleWord(header1, &pagestat, EE_SET_PAGE); + if (ee_status != EE_OK) return ee_status; + ubCurrentActivePage = Page; + } + break; + case STATE_PAGE_ACTIVE: + { + /* Set new Page status to STATE_PAGE_ACTIVE status */ + pagestat = EE_PAGESTAT_ACTIVE; + ee_status = FI_WriteDoubleWord(header2, &pagestat, EE_SET_PAGE); + if (ee_status != EE_OK) return ee_status; + ubCurrentActivePage = Page; + } + break; + case STATE_PAGE_VALID: + { + /* Set new Page status to STATE_PAGE_VALID status */ + pagestat = EE_PAGESTAT_VALID; + ee_status = FI_WriteDoubleWord(header3, &pagestat, EE_SET_PAGE); + if (ee_status != EE_OK) return ee_status; + } + break; + case STATE_PAGE_ERASING: + { + /* Set new Page status to STATE_PAGE_ERASING status */ + pagestat = EE_PAGESTAT_ERASING; + ee_status = FI_WriteDoubleWord(header4, &pagestat, EE_SET_PAGE); + if (ee_status != EE_OK) return ee_status; + } + break; + default: + break; + } +#else + switch(State) + { + case STATE_PAGE_RECEIVE: + { + /* Set new Page status to STATE_PAGE_RECEIVE status */ + if (FI_WriteDoubleWord(header1, EE_PAGESTAT_RECEIVE) != HAL_OK) + { + return EE_WRITE_ERROR; + } + ubCurrentActivePage = Page; + } + break; + case STATE_PAGE_ACTIVE: + { + /* Set new Page status to STATE_PAGE_ACTIVE status */ + if (FI_WriteDoubleWord(header2, EE_PAGESTAT_ACTIVE) != HAL_OK) + { + return EE_WRITE_ERROR; + } + ubCurrentActivePage = Page; + } + break; + case STATE_PAGE_VALID: + { + /* Set new Page status to STATE_PAGE_VALID status */ + if (FI_WriteDoubleWord(header3, EE_PAGESTAT_VALID) != HAL_OK) + { + return EE_WRITE_ERROR; + } + } + break; + case STATE_PAGE_ERASING: + { + /* Set new Page status to STATE_PAGE_ERASING status */ + if (FI_WriteDoubleWord(header4, EE_PAGESTAT_ERASING) != HAL_OK) + { + return EE_WRITE_ERROR; + } + } + break; + default: + break; + } +#endif + + /* Return last operation flash status */ + return EE_OK; +} + +/** + * @brief Get page state in page header + * @param Address Address of the FLASH Memory page + * @retval State State of the page + */ +#ifndef FLASH_LINES_128B +static EE_State_type GetPageState(uint32_t Address) +{ + EE_ELEMENT_TYPE status1 = 0U, status2 = 0U, status3 = 0U, status4 = 0U; + + /* Get page state information from page header (3 first elements) */ + status1 = (*(__IO EE_ELEMENT_TYPE*)Address); + status2 = (*(__IO EE_ELEMENT_TYPE*)(Address + EE_ELEMENT_SIZE)); + status3 = (*(__IO EE_ELEMENT_TYPE*)(Address + (EE_ELEMENT_SIZE*2U))); + status4 = (*(__IO EE_ELEMENT_TYPE*)(Address + (EE_ELEMENT_SIZE*3U))); + + /* Return erasing status, if element4 is not EE_PAGESTAT_ERASED value */ + if (status4 != EE_PAGESTAT_ERASED) + { + return STATE_PAGE_ERASING; + } + + /* Return valid status, if element3 is not EE_PAGESTAT_ERASED value */ + if (status3 != EE_PAGESTAT_ERASED) + { + return STATE_PAGE_VALID; + } + + /* Return active status, if element2 is not EE_PAGESTAT_ERASED value */ + if (status2 != EE_PAGESTAT_ERASED) + { + return STATE_PAGE_ACTIVE; + } + + /* Return receive status, if element1 is not EE_PAGESTAT_ERASED value */ + if (status1 != EE_PAGESTAT_ERASED) + { + return STATE_PAGE_RECEIVE; + } + + /* Return erased status, if 4 first elements are EE_PAGESTAT_ERASED value */ + return STATE_PAGE_ERASED; +} +#else +static EE_State_type GetPageState(uint32_t Address) +{ + EE_ELEMENT_TYPE status1 = 0U, status2 = 0U, status3 = 0U, status4 = 0U; + EE_ELEMENT_TYPE status1bis = 0U, status2bis = 0U, status3bis = 0U, status4bis = 0U; + + /* Get page state information from page header (3 first elements) */ + status1 = (*(__IO EE_ELEMENT_TYPE*)Address); + status2 = (*(__IO EE_ELEMENT_TYPE*)(Address + EE_ELEMENT_SIZE)); + status3 = (*(__IO EE_ELEMENT_TYPE*)(Address + (EE_ELEMENT_SIZE*2U))); + status4 = (*(__IO EE_ELEMENT_TYPE*)(Address + (EE_ELEMENT_SIZE*3U))); + status1bis = (*(__IO EE_ELEMENT_TYPE*)(Address + 8)); + status2bis = (*(__IO EE_ELEMENT_TYPE*)(Address + EE_ELEMENT_SIZE + 8)); + status3bis = (*(__IO EE_ELEMENT_TYPE*)(Address + (EE_ELEMENT_SIZE*2U) + 8)); + status4bis = (*(__IO EE_ELEMENT_TYPE*)(Address + (EE_ELEMENT_SIZE*3U) + 8)); + + /* Return erasing status, if element4 is not EE_PAGESTAT_ERASED value */ + if ((status4 != EE_PAGESTAT_ERASED) && (status4bis != EE_PAGESTAT_ERASED)) + { + return STATE_PAGE_ERASING; + } + + /* Return valid status, if element3 is not EE_PAGESTAT_ERASED value */ + if ((status3 != EE_PAGESTAT_ERASED) && (status3bis != EE_PAGESTAT_ERASED)) + { + return STATE_PAGE_VALID; + } + + /* Return active status, if element2 is not EE_PAGESTAT_ERASED value */ + if ((status2 != EE_PAGESTAT_ERASED) && (status2bis != EE_PAGESTAT_ERASED)) + { + return STATE_PAGE_ACTIVE; + } + + /* Return receive status, if element1 is not EE_PAGESTAT_ERASED value */ + if ((status1 != EE_PAGESTAT_ERASED) && (status1bis != EE_PAGESTAT_ERASED)) + { + return STATE_PAGE_RECEIVE; + } + + /* Return erased status, if 4 first elements are EE_PAGESTAT_ERASED value */ + return STATE_PAGE_ERASED; +} +#endif + +/** + * @brief This function configures CRC Instance. + * @note This function is used to : + * -1- Enable peripheral clock for CRC. + * -2- Configure CRC functional parameters. + * @note Peripheral configuration is minimal configuration from reset values. + * Thus, some useless LL unitary functions calls below are provided as + * commented examples - setting is default configuration from reset. + * @param None + * @retval None + */ +void ConfigureCrc(void) +{ + /* (1) Enable peripheral clock for CRC */ + LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_CRC); + + /* (2) Configure CRC functional parameters */ + + /* Configure CRC calculation unit with user defined polynomial */ + LL_CRC_SetPolynomialCoef(CRC, CRC_POLYNOMIAL_VALUE); + LL_CRC_SetPolynomialSize(CRC, CRC_POLYNOMIAL_LENGTH); + + /* Initialize default CRC initial value */ + /* Reset value is LL_CRC_DEFAULT_CRC_INITVALUE */ + /* LL_CRC_SetInitialData(CRC, LL_CRC_DEFAULT_CRC_INITVALUE);*/ + + /* Set input data inversion mode : No inversion*/ + /* Reset value is LL_CRC_INDATA_REVERSE_NONE */ + /* LL_CRC_SetInputDataReverseMode(CRC, LL_CRC_INDATA_REVERSE_NONE); */ + + /* Set output data inversion mode : No inversion */ + /* Reset value is LL_CRC_OUTDATA_REVERSE_NONE */ + /* LL_CRC_SetOutputDataReverseMode(CRC, LL_CRC_OUTDATA_REVERSE_NONE); */ +} + +/** + * @brief This function performs CRC calculation on Data and Virtual Address. + * @param Data value of the eeprom variable. + * @param VirtAddress address of the eeprom variable. + * @retval 16-bit CRC value computed on Data and Virtual Address. + */ +#ifndef FLASH_LINES_128B +uint16_t CalculateCrc(EE_DATA_TYPE Data, uint16_t VirtAddress) +#else +uint16_t CalculateCrc(EE_DATA_TYPE Data1, EE_DATA_TYPE Data2) +#endif +{ + /* Reset CRC calculation unit */ + LL_CRC_ResetCRCCalculationUnit(CRC); + + /* Feed Data and Virtual Address */ +#ifndef FLASH_LINES_128B + LL_CRC_FeedData32(CRC, Data); + LL_CRC_FeedData16(CRC, VirtAddress); +#else + LL_CRC_FeedData32(CRC, ((uint32_t)Data1)); + LL_CRC_FeedData32(CRC, ((uint32_t)(Data1>>32))); + LL_CRC_FeedData32(CRC, ((uint32_t)((Data2 & 0xFFFFFFFF00000000)>>32))); + LL_CRC_FeedData16(CRC, ((uint16_t)Data2)); + +#endif + + /* Return computed CRC value */ + return(LL_CRC_ReadData16(CRC)); +} + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Middlewares/ST/EEPROM_Emul/Core/eeprom_emul.h b/Middlewares/ST/EEPROM_Emul/Core/eeprom_emul.h new file mode 100644 index 0000000..d94e6b2 --- /dev/null +++ b/Middlewares/ST/EEPROM_Emul/Core/eeprom_emul.h @@ -0,0 +1,142 @@ +/** + ****************************************************************************** + * @file EEPROM_Emul/Core/eeprom_emul.h + * @author MCD Application Team + * @brief This file contains all the functions prototypes for the EEPROM + * emulation firmware library. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __EEPROM_EMUL_H +#define __EEPROM_EMUL_H + +/* Includes ------------------------------------------------------------------*/ +#include "eeprom_emul_conf.h" +#include "eeprom_emul_types.h" +#include "flash_interface.h" + +/** @addtogroup EEPROM_Emulation + * @{ + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup EEPROM_Private_Constants EEPROM Private Constants + * @{ + */ + +/** @defgroup Private_Other_Constants Private Other Constants + * @{ + */ + +/* Page definitions */ +#define PAGE_SIZE FLASH_PAGE_SIZE /*!< Page size */ +#define PAGE_HEADER_SIZE EE_ELEMENT_SIZE * 4U /*!< Page Header is 4 elements to save page state */ +#define NB_MAX_ELEMENTS_BY_PAGE ((PAGE_SIZE - PAGE_HEADER_SIZE) / EE_ELEMENT_SIZE) /*!< Max number of elements by page */ +#define PAGES_NUMBER (((((NB_OF_VARIABLES + NB_MAX_ELEMENTS_BY_PAGE) / NB_MAX_ELEMENTS_BY_PAGE) * 2U) * CYCLES_NUMBER) + GUARD_PAGES_NUMBER) + /*!< Number of consecutives pages used by the application */ +#define NB_MAX_WRITTEN_ELEMENTS ((NB_MAX_ELEMENTS_BY_PAGE * PAGES_NUMBER) / 2U) /*!< Max number of elements written before triggering pages transfer */ +#define START_PAGE PAGE(START_PAGE_ADDRESS) /*!< Page index of the 1st page used for EEPROM emul, in the bank */ +#define END_EEPROM_ADDRESS (START_PAGE_ADDRESS + (PAGES_NUMBER * FLASH_PAGE_SIZE) - 1) /*!< Last address of EEPROM emulation flash pages */ + +/* No page define */ +#define EE_NO_PAGE_FOUND ((uint32_t)0xFFFFFFFFU) + +/** + * @} + */ + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/** @defgroup EEPROM_Private_Macros EEPROM Private Macros + * @{ + */ + +/** @defgroup Macros_Pages Macros to manipulate pages + * @{ + */ + +/* Macros to manipulate pages */ +#ifdef SECURE_FEATURES + #define PAGE_ADDRESS(__PAGE__) (uint32_t)(FLASH_BASE_NS + (__PAGE__) * PAGE_SIZE + ((START_PAGE_ADDRESS - FLASH_BASE_NS) / BANK_SIZE) * BANK_SIZE) /*!< Get page address from page index */ + #define PAGE(__ADDRESS__) (uint32_t)((((__ADDRESS__) - FLASH_BASE_NS) % BANK_SIZE) / FLASH_PAGE_SIZE) /*!< Get page index from page address */ +#else + #define PAGE_ADDRESS(__PAGE__) (uint32_t)(FLASH_BASE + (__PAGE__) * PAGE_SIZE + ((START_PAGE_ADDRESS - FLASH_BASE) / BANK_SIZE) * BANK_SIZE) /*!< Get page address from page index */ + #define PAGE(__ADDRESS__) (uint32_t)((((__ADDRESS__) - FLASH_BASE) % BANK_SIZE) / FLASH_PAGE_SIZE) /*!< Get page index from page address */ +#endif +#define PREVIOUS_PAGE(__PAGE__) (uint32_t)((((__PAGE__) - START_PAGE - 1U + PAGES_NUMBER) % PAGES_NUMBER) + START_PAGE) /*!< Get page index of previous page, among circular page list */ +#define FOLLOWING_PAGE(__PAGE__) (uint32_t)((((__PAGE__) - START_PAGE + 1U) % PAGES_NUMBER) + START_PAGE) /*!< Get page index of following page, among circular page list */ + +/** + * @} + */ + +/** @defgroup Macros_Elements Macros to manipulate elements + * @{ + */ + +/* Macros to manipulate elements */ +#define EE_VIRTUALADDRESS_VALUE(__ELEMENT__) (EE_VIRTUALADDRESS_TYPE)((__ELEMENT__) & EE_MASK_VIRTUALADDRESS) /*!< Get virtual address value from element value */ +#define EE_DATA_VALUE(__ELEMENT__) (EE_DATA_TYPE)(((__ELEMENT__) & EE_MASK_DATA) >> EE_DATA_SHIFT) /*!< Get Data value from element value */ +#define EE_CRC_VALUE(__ELEMENT__) (EE_CRC_TYPE)(((__ELEMENT__) & EE_MASK_CRC) >> EE_CRC_SHIFT) /*!< Get Crc value from element value */ +#define EE_ELEMENT_VALUE(__VIRTADDR__,__DATA__,__CRC__) (((EE_ELEMENT_TYPE)(__DATA__) << EE_DATA_SHIFT) | (__CRC__) << EE_CRC_SHIFT | (__VIRTADDR__)) /*!< Get element value from virtual addr, data and crc values */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +/** @defgroup EEPROM_Exported_Functions EEPROM Exported Functions + * @{ + */ +EE_Status EE_Format(EE_Erase_type EraseType); +EE_Status EE_Init(EE_Erase_type EraseType); +#if defined(EE_ACCESS_32BITS) +EE_Status EE_ReadVariable32bits(uint16_t VirtAddress, uint32_t* pData); +EE_Status EE_WriteVariable32bits(uint16_t VirtAddress, uint32_t Data); +#endif +#if defined(FLASH_LINES_128B) +EE_Status EE_ReadVariable96bits(uint16_t VirtAddress, uint64_t* pData); +EE_Status EE_WriteVariable96bits(uint16_t VirtAddress, uint64_t* Data); +#endif +EE_Status EE_ReadVariable16bits(uint16_t VirtAddress, uint16_t* pData); +EE_Status EE_WriteVariable16bits(uint16_t VirtAddress, uint16_t Data); +EE_Status EE_ReadVariable8bits(uint16_t VirtAddress, uint8_t* pData); +EE_Status EE_WriteVariable8bits(uint16_t VirtAddress, uint8_t Data); +EE_Status EE_CleanUp(void); +EE_Status EE_CleanUp_IT(void); +EE_Status EE_DeleteCorruptedFlashAddress(uint32_t Address); +void EE_EndOfCleanup_UserCallback(void); + +/** + * @} + */ + +/** + * @} + */ + +#endif /* __EEPROM_EMUL_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Middlewares/ST/EEPROM_Emul/Core/eeprom_emul_conf.h b/Middlewares/ST/EEPROM_Emul/Core/eeprom_emul_conf.h new file mode 100644 index 0000000..c8c74ba --- /dev/null +++ b/Middlewares/ST/EEPROM_Emul/Core/eeprom_emul_conf.h @@ -0,0 +1,90 @@ +/** + ****************************************************************************** + * @file eeprom_emul_conf.h + * @author MCD Application Team + * @brief EEPROM emulation configuration file. + * This file should be copied to the application folder and renamed + * to eeprom_emul_conf.h. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup EEPROM_Emulation + * @{ + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __EEPROM_EMUL_CONF_H +#define __EEPROM_EMUL_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Private constants ---------------------------------------------------------*/ +/** @addtogroup EEPROM_Private_Constants + * @{ + */ + +/** @defgroup Private_Configuration_Constants Private Configuration Constants + * @{ + */ + +/* Configuration of eeprom emulation in flash, can be custom */ +#define START_PAGE_ADDRESS 0x0801F000U /*!< Start address of the second last page in flash, for EEPROM emulation */ +#define CYCLES_NUMBER 1U /*!< Number of 10Kcycles requested, minimum 1 for 10Kcycles (default), for instance 10 to reach 100Kcycles. This factor will increase pages number */ +#define GUARD_PAGES_NUMBER 0U /*!< Number of guard pages avoiding frequent transfers (must be multiple of 2): 0,2,4.. */ + +/* Configuration of crc calculation for eeprom emulation in flash */ +#define CRC_POLYNOMIAL_LENGTH LL_CRC_POLYLENGTH_16B /* CRC polynomial lenght 16 bits */ +#define CRC_POLYNOMIAL_VALUE 0x8005U /* Polynomial to use for CRC calculation */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup EEPROM_Exported_Constants EEPROM Exported Constants + * @{ + */ + +/** @defgroup Exported_Configuration_Constants Exported Configuration Constants + * @{ + */ +#define NB_OF_VARIABLES 6U /*!< Number of variables to handle in eeprom */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +#endif /* __EEPROM_EMUL_CONF_H */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Middlewares/ST/EEPROM_Emul/Core/eeprom_emul_types.h b/Middlewares/ST/EEPROM_Emul/Core/eeprom_emul_types.h new file mode 100644 index 0000000..f5fee32 --- /dev/null +++ b/Middlewares/ST/EEPROM_Emul/Core/eeprom_emul_types.h @@ -0,0 +1,118 @@ +/** + ****************************************************************************** + * @file EEPROM_Emul/Core/eeprom_emul_types.h + * @author MCD Application Team + * @brief This file contains all the functions prototypes for the EEPROM + * emulation firmware library. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __EEPROM_EMUL_TYPES_H +#define __EEPROM_EMUL_TYPES_H + +/** @addtogroup EEPROM_Emulation + * @{ + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup EEPROM_Exported_Constants EEPROM Exported Constants + * @{ + */ + +/** @defgroup Exported_Other_Constants Exported Other Constants + * @{ + */ + +/** + * @brief EE Status enum definition. + */ +/* Define of the return value */ +typedef enum { + /* External return codes : ok */ + EE_OK = 0U, + + /* External return codes : errors */ + EE_ERASE_ERROR, + EE_WRITE_ERROR, + EE_ERROR_NOACTIVE_PAGE, + EE_ERROR_NOERASE_PAGE, + EE_ERROR_NOERASING_PAGE, + EE_ERROR_NOACTIVE_NORECEIVE_NOVALID_PAGE, + EE_NO_DATA, + EE_INVALID_VIRTUALADDRESS, + EE_INVALID_PAGE, + EE_INVALID_PAGE_SEQUENCE, + EE_INVALID_ELEMENT, + EE_TRANSFER_ERROR, + EE_DELETE_ERROR, + EE_INVALID_BANK_CFG, + + /* Internal return code */ + EE_NO_PAGE_FOUND, + EE_PAGE_NOTERASED, + EE_PAGE_ERASED, + EE_PAGE_FULL, + + /* External return code : action required */ + EE_CLEANUP_REQUIRED = 0x100U, + +#ifdef DUALCORE_FLASH_SHARING + /* Value returned when a program or erase operation is requested but + * the flash is already used by CPU2 */ + EE_FLASH_USED, + EE_SEM_TIMEOUT, +#endif + +} EE_Status; + +/* Type of page erasing: + EE_FORCED_ERASE --> pages to erase are erased unconditionnally + EE_CONDITONAL_ERASE --> pages to erase are erased only if not fully erased */ +typedef enum { + EE_FORCED_ERASE, + EE_CONDITIONAL_ERASE +} EE_Erase_type; + +#if (defined DUALCORE_FLASH_SHARING) || (defined FLASH_LINES_128B) +/* Type of write operations: + EE_TRANSFER --> Used by WriteDoubleWord to know when the operation ongoing is a transfer + EE_SIMPLE_WRITE --> Used by WriteDoubleWord to know when the operation ongoing is a simple writing */ +typedef enum { + EE_TRANSFER, + EE_SIMPLE_WRITE, + EE_SET_PAGE, + EE_INIT_WRITE +} EE_Write_type; +#endif + +/* Masks of EE_Status return codes */ +#define EE_STATUSMASK_ERROR (uint16_t)0x00FFU /*!< Mask on EE_Status return code, selecting error codes */ +#define EE_STATUSMASK_CLEANUP (uint16_t)0x0100U /*!< Mask on EE_Status return code, selecting cleanup request codes */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* __EEPROM_EMUL_TYPES_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Middlewares/ST/EEPROM_Emul/Porting/STM32L4/flash_interface.c b/Middlewares/ST/EEPROM_Emul/Porting/STM32L4/flash_interface.c new file mode 100644 index 0000000..8b04f80 --- /dev/null +++ b/Middlewares/ST/EEPROM_Emul/Porting/STM32L4/flash_interface.c @@ -0,0 +1,279 @@ +/** + ****************************************************************************** + * @file EEPROM_Emul/Porting/STM32L4/flash_interface.c + * @author MCD Application Team + * @brief This file provides all the EEPROM emulation flash interface functions. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "eeprom_emul.h" +#include "flash_interface.h" + +/** @addtogroup EEPROM_Emulation + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +#if defined(FLASH_BANK_2) +static uint32_t GetBankNumber(uint32_t Address); +#endif + +/* Exported functions --------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/** @addtogroup EEPROM_Private_Functions + * @{ + */ + +/** + * @brief Write a double word at the given address in Flash + * @param Address Where to write + * @param Data What to write + * @retval EE_Status + * - EE_OK: on success + * - EE_WRITE_ERROR: if an error occurs + */ +HAL_StatusTypeDef FI_WriteDoubleWord(uint32_t Address, uint64_t Data) +{ + return HAL_FLASH_Program(FLASH_TYPEPROGRAM_DOUBLEWORD, Address, Data); +} + +/** + * @brief Erase a page in polling mode + * @param Page Page number + * @param NbPages Number of pages to erase + * @retval EE_Status + * - EE_OK: on success + * - EE error code: if an error occurs + */ +EE_Status FI_PageErase(uint32_t Page, uint16_t NbPages) +{ + EE_Status status = EE_OK; + FLASH_EraseInitTypeDef s_eraseinit; + uint32_t bank = FLASH_BANK_1, page_error = 0U; + +#if defined(FLASH_BANK_2) + bank = GetBankNumber(PAGE_ADDRESS(Page)); +#endif + + s_eraseinit.TypeErase = FLASH_TYPEERASE_PAGES; + s_eraseinit.NbPages = NbPages; + s_eraseinit.Page = Page; + s_eraseinit.Banks = bank; + + /* Erase the Page: Set Page status to ERASED status */ + if (HAL_FLASHEx_Erase(&s_eraseinit, &page_error) != HAL_OK) + { + status = EE_ERASE_ERROR; + } + return status; +} + +/** + * @brief Erase a page with interrupt enabled + * @param Page Page number + * @param NbPages Number of pages to erase + * @retval EE_Status + * - EE_OK: on success + * - EE error code: if an error occurs + */ +EE_Status FI_PageErase_IT(uint32_t Page, uint16_t NbPages) +{ + EE_Status status = EE_OK; + FLASH_EraseInitTypeDef s_eraseinit; + uint32_t bank = FLASH_BANK_1; + +#if defined(FLASH_BANK_2) + bank = GetBankNumber(PAGE_ADDRESS(Page)); +#endif + + s_eraseinit.TypeErase = FLASH_TYPEERASE_PAGES; + s_eraseinit.NbPages = NbPages; + s_eraseinit.Page = Page; + s_eraseinit.Banks = bank; + + /* Erase the Page: Set Page status to ERASED status */ + if (HAL_FLASHEx_Erase_IT(&s_eraseinit) != HAL_OK) + { + status = EE_ERASE_ERROR; + } + return status; +} + +/** + * @brief Flush the caches if needed to keep coherency when the flash content is modified + */ +void FI_CacheFlush() +{ + /* To keep its coherency, flush the D-Cache: its content is not updated after a flash erase. */ + __HAL_FLASH_DATA_CACHE_DISABLE(); + __HAL_FLASH_DATA_CACHE_RESET(); + __HAL_FLASH_DATA_CACHE_ENABLE(); +} + +#if defined(FLASH_BANK_2) +/** + * @brief Gets the bank of a given address + * @param Address Address of the FLASH Memory + * @retval Bank_Number The bank of a given address + */ +static uint32_t GetBankNumber(uint32_t Address) +{ + uint32_t bank = 0U; + + if (READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE) == 0U) + { + /* No Bank swap */ + if (Address < (FLASH_BASE + FLASH_BANK_SIZE)) + { + bank = FLASH_BANK_1; + } + else + { + bank = FLASH_BANK_2; + } + } + else + { + /* Bank swap */ + if (Address < (FLASH_BASE + FLASH_BANK_SIZE)) + { + bank = FLASH_BANK_2; + } + else + { + bank = FLASH_BANK_1; + } + } + + return bank; +} +#endif + +/** + * @brief Delete corrupted Flash address, can be called from NMI. No Timeout. + * @param Address Address of the FLASH Memory to delete + * @retval EE_Status + * - EE_OK: on success + * - EE error code: if an error occurs + */ +EE_Status FI_DeleteCorruptedFlashAddress(uint32_t Address) +{ + uint32_t dcachetoreactivate = 0U; + EE_Status status = EE_OK; + + /* Deactivate the data cache if they are activated to avoid data misbehavior */ + if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != RESET) + { + /* Disable data cache */ + __HAL_FLASH_DATA_CACHE_DISABLE(); + dcachetoreactivate = 1U; + } + + /* Set FLASH Programmation bit */ + SET_BIT(FLASH->CR, FLASH_CR_PG); + + /* Program double word of value 0 */ + *(__IO uint32_t*)(Address) = (uint32_t)0U; + *(__IO uint32_t*)(Address+4U) = (uint32_t)0U; + + /* Wait programmation completion */ + while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY)) + { + } + + /* Check if error occured */ + if((__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PROGERR)) || + (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR)) || + (__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGSERR))) + { + status = EE_DELETE_ERROR; + } + + /* Check FLASH End of Operation flag */ + if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) + { + /* Clear FLASH End of Operation pending bit */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); + } + + /* Clear FLASH Programmation bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_PG); + + /* Flush the caches to be sure of the data consistency */ + if(dcachetoreactivate == 1U) + { + /* Reset data cache */ + __HAL_FLASH_DATA_CACHE_RESET(); + /* Enable data cache */ + __HAL_FLASH_DATA_CACHE_ENABLE(); + } + + /* Clear FLASH ECCD bit */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_ECCD); + + return status; +} + +/** + * @brief Check if the configuration is 128-bits bank or 2*64-bits bank + * @param None + * @retval EE_Status + * - EE_OK: on success + * - EE error code: if an error occurs + */ +EE_Status FI_CheckBankConfig(void) +{ +#if defined (FLASH_OPTR_DBANK) + FLASH_OBProgramInitTypeDef sOBCfg; + EE_Status status; + + /* Request the Option Byte configuration : + - User and RDP level are always returned + - WRP and PCROP are not requested */ + sOBCfg.WRPArea = 0xFF; + sOBCfg.PCROPConfig = 0xFF; + HAL_FLASHEx_OBGetConfig(&sOBCfg); + + /* Check the value of the DBANK user option byte */ + if ((sOBCfg.USERConfig & OB_DBANK_64_BITS) != 0) + { + status = EE_OK; + } + else + { + status = EE_INVALID_BANK_CFG; + } + + return status; +#else + /* No feature 128-bits single bank, so always 64-bits dual bank */ + return EE_OK; +#endif +} + + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Middlewares/ST/EEPROM_Emul/Porting/STM32L4/flash_interface.h b/Middlewares/ST/EEPROM_Emul/Porting/STM32L4/flash_interface.h new file mode 100644 index 0000000..41a793a --- /dev/null +++ b/Middlewares/ST/EEPROM_Emul/Porting/STM32L4/flash_interface.h @@ -0,0 +1,125 @@ +/** + ****************************************************************************** + * @file EEPROM_Emul/Porting/STM32L4/flash_interface.h + * @author MCD Application Team + * @brief This file contains all the functions prototypes for the EEPROM + * emulation flash interface. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __FLASH_INTERFACE_H +#define __FLASH_INTERFACE_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx_hal.h" +#include "stm32l4xx_ll_crc.h" +#include "stm32l4xx_ll_bus.h" + +/** @addtogroup EEPROM_Emulation + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +/* Private types -------------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @addtogroup EEPROM_Private_Constants + * @{ + */ + +/** @addtogroup Private_Other_Constants + * @{ + */ + +#define BANK_SIZE FLASH_BANK_SIZE /*!< Alias to FLASH_BANK_SIZE definition from HAL STM32L4 */ +#define EE_ACCESS_32BITS /*!< Enable EEPROM 32bits R/W functions, only valid for flash allowing 64bits access*/ + +/* Page state header */ +#define EE_PAGESTAT_ERASED (uint64_t)0xFFFFFFFFFFFFFFFFU /*!< State saved in 1st,2nd,3rd,4th data type of page header */ +#define EE_PAGESTAT_RECEIVE (uint64_t)0xAAAAAAAAAAAAAAAAU /*!< State saved in 1st data type of page header */ +#define EE_PAGESTAT_ACTIVE (uint64_t)0xAAAAAAAAAAAAAAAAU /*!< State saved in 2nd data type of page header */ +#define EE_PAGESTAT_VALID (uint64_t)0xAAAAAAAAAAAAAAAAU /*!< State saved in 3rd data type of page header */ +#define EE_PAGESTAT_ERASING (uint64_t)0xAAAAAAAAAAAAAAAAU /*!< State saved in 4th data type of page header */ + +/* Description of the 8 Bytes (64 bits) element in flash */ +/* Bit: 63 32 31 16 15 0 */ +/* <--- Data Value -----> <-unused-> <-VirtAddr-> */ +#define EE_ELEMENT_SIZE 8U /*!< Size of element in Bytes */ +#define EE_ELEMENT_TYPE uint64_t /*!< Type of element */ +#define EE_VIRTUALADDRESS_TYPE uint16_t /*!< Type of Virtual Address */ +#define EE_VIRTUALADDRESS_SHIFT 0U /*!< Bits Shifting to get Virtual Address in element */ +#define EE_CRC_TYPE uint16_t /*!< Type of Crc */ +#define EE_CRC_SHIFT 16U /*!< Bits Shifting to get Crc in element */ +#define EE_DATA_TYPE uint32_t /*!< Type of Data */ +#define EE_DATA_SHIFT 32U /*!< Bits Shifting to get Data value in element */ +#define EE_MASK_VIRTUALADDRESS (uint64_t)0x000000000000FFFFU +#define EE_MASK_CRC (uint64_t)0x00000000FFFF0000U +#define EE_MASK_DATA (uint64_t)0xFFFFFFFF00000000U +#define EE_MASK_FULL (uint64_t)0xFFFFFFFFFFFFFFFFU + +/** + * @} + */ + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/** @addtogroup EEPROM_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @addtogroup EEPROM_Private_Functions + * @{ + */ +HAL_StatusTypeDef FI_WriteDoubleWord(uint32_t Address, uint64_t Data); +EE_Status FI_PageErase(uint32_t Page, uint16_t NbPages); +EE_Status FI_PageErase_IT(uint32_t Page, uint16_t NbPages); +EE_Status FI_DeleteCorruptedFlashAddress(uint32_t Address); +EE_Status FI_CheckBankConfig(void); +void FI_CacheFlush(void); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +#endif /* __FLASH_INTERFACE_H */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/PeltierControllerV1.srec b/PeltierControllerV1.srec deleted file mode 100644 index bb95531..0000000 --- a/PeltierControllerV1.srec +++ /dev/null @@ -1,1145 +0,0 @@ -S0220000687474703A2F2F737265636F72642E736F75726365666F7267652E6E65742F1D -S3250800280000000120CDAD0008094B00080B4B00080D4B00080F4B0008114B00080000000027 -S32508002820000000000000000000000000A18B0008134B000800000000418C0008154B0008B3 -S325080028401DAE00081DAE00081DAE00081DAE00081DAE00081DAE00081DAE00081DAE0008D2 -S325080028601DAE00081DAE00081DAE00081DAE00082D4B00083D4B00081DAE00081DAE000848 -S325080028801DAE00081DAE00084D4B00085D4B00086D4B00087D4B00088D4B00081DAE0008F1 -S325080028A01DAE00081DAE00081DAE00081DAE00081DAE000800000000000000001DAE000818 -S325080028C01DAE000800000000000000009D4B0008000000001DAE00081DAE00080000000081 -S325080028E01DAE00081DAE000800000000000000000000000000000000000000000000000024 -S325080029000000000000000000000000001DAE000800000000000000001DAE00081DAE000830 -S325080029201DAE00081DAE0008AD4B00081DAE00081DAE00080000000000000000000000003D -S325080029401DAE00081DAE00081DAE00081DAE00081DAE00081DAE00081DAE00081DAE0008D1 -S325080029601DAE00081DAE00081DAE0008000000001DAE00081DAE000800000000000000002A -S325080029801DAE00081DAE00081DAE0008EE11AA5581F0004102E000BF83F0004330B54FEA8B -S325080029A041044FEA430594EA050F08BF90EA020F1FBF54EA000C55EA020C7FEA645C7FEA58 -S325080029C0655C00F0E2804FEA5454D4EB5555B8BF6D420CDD2C4480EA020281EA030382EAC2 -S325080029E0000083EA010180EA020281EA0303362D88BF30BD11F0004F4FEA01314FF4801C4A -S32508002A004CEA113102D0404261EB410113F0004F4FEA03334CEA133302D0524263EB430317 -S32508002A2094EA050F00F0A780A4F10104D5F1200E0DDB02FA0EFC22FA05F2801841F1000185 -S32508002A4003FA0EF2801843FA05F359410EE0A5F120050EF1200E012A03FA0EFC28BF4CF0D9 -S32508002A60020C43FA05F3C01851EBE37101F0004507D54FF0000EDCF1000C7EEB00006EEBA3 -S32508002A800101B1F5801F1BD3B1F5001F0CD349085FEA30004FEA3C0C04F101044FEA44523B -S32508002AA012F5800F80F09A80BCF1004F08BF5FEA500C50F1000041EB045141EA050130BDA0 -S32508002AC05FEA4C0C404141EB0101013C28BFB1F5801FE9D291F0000F04BF01460020B1FA0F -S32508002AE081F308BF2033A3F10B03B3F120020CDA0C3208DD02F1140CC2F10C0201FA0CF0FE -S32508002B0021FA02F10CE002F11402D8BFC2F1200C01FA02F120FA0CFCDCBF41EA0C0190407B -S32508002B20E41AA2BF01EB0451294330BD6FEA04041F3C1CDA0C340EDC04F11404C4F12002CE -S32508002B4020FA04F001FA02F340EA030021FA04F345EA030130BDC4F10C04C4F1200220FA54 -S32508002B6002F001FA04F340EA0300294630BD21FA04F0294630BD94F0000F83F4801306BF0D -S32508002B8081F480110134013D4EE77FEA645C18BF7FEA655C29D094EA050F08BF90EA020F72 -S32508002BA005D054EA000C04BF1946104630BD91EA030F1EBF0021002030BD5FEA545C05D11C -S32508002BC04000494128BF41F0004130BD14F580043CBF01F5801130BD01F0004545F0FE4131 -S32508002BE041F470014FF0000030BD7FEA645C1ABF194610467FEA655C1CBF0B46024650EA66 -S32508002C00013406BF52EA033591EA030F41F4002130BD00BF90F0000F04BF0021704730B59A -S32508002C204FF4806404F132044FF000054FF0000150E700BF90F0000F04BF0021704730B5AB -S32508002C404FF4806404F1320410F0004548BF40424FF000013EE700BF42004FEAE2014FEA8B -S32508002C6031014FEA02701FBF12F07F4393F07F4F81F06051704732F07F4208BF704793F0B9 -S32508002C807F4F04BF41F40021704730B54FF4607401F0004521F000411CE700BF50EA010205 -S32508002CA008BF704730B54FF000050AE050EA010208BF704730B511F0004502D5404261EBEA -S32508002CC041014FF4806404F132045FEA915C3FF4D8AE4FF003025FEADC0C18BF03325FEA99 -S32508002CE0DC0C18BF033202EBDC02C2F1200300FA03FC20FA02F001FA03FE40EA0E0021FADD -S32508002D0002F11444BDE600BF70B54FF0FF0C4CF4E06C1CEA11541DBF1CEA135594EA0C0FAF -S32508002D2095EA0C0F00F0DEF82C4481EA030621EA4C5123EA4C5350EA013518BF52EA033532 -S32508002D4041F4801143F4801338D0A0FB02CE4FF00005E1FB02E506F00042E0FB03E54FF021 -S32508002D600006E1FB03569CF0000F18BF4EF0010EA4F1FF04B6F5007F64F5407404D25FEA5D -S32508002D804E0E6D4146EB060642EAC62141EA55514FEAC52040EA5E504FEACE2EB4F1FD0C21 -S32508002DA088BFBCF5E06F1ED8BEF1004F08BF5FEA500E50F1000041EB045170BD06F0004631 -S32508002DC046EA010140EA020081EA0301B4EB5C04C2BFD4EB0C0541EA045170BD41F4801155 -S32508002DE04FF0000E013C00F3AB8014F1360FDEBF002001F0004170BDC4F10004203C35DA93 -S32508002E000C341BDC04F11404C4F1200500FA05F320FA04F001FA05F240EA020001F0004235 -S32508002E2021F0004110EBD37021FA04F642EB06015EEA430E08BF20EAD37070BDC4F10C040C -S32508002E40C4F1200500FA04F320FA05F001FA04F240EA020001F0004110EBD37041F10001CA -S32508002E605EEA430E08BF20EAD37070BDC4F1200500FA05F24EEA020E20FA04F301FA05F254 -S32508002E8043EA020321FA04F001F0004121FA04F220EA020000EBD3705EEA430E08BF20EAFC -S32508002EA0D37070BD94F0000F0FD101F00046400041EB010111F4801F08BF013CF7D041EAE2 -S32508002EC0060195F0000F18BF704703F00046520043EB030313F4801F08BF013DF7D043EA5D -S32508002EE00603704794EA0C0F0CEA135518BF95EA0C0F0CD050EA410618BF52EA4306D1D141 -S32508002F0081EA030101F000414FF0000070BD50EA410606BF1046194652EA430619D094EAAF -S32508002F200C0F02D150EA013613D195EA0C0F05D152EA03361CBF104619460AD181EA030181 -S32508002F4001F0004141F0FE4141F470014FF0000070BD41F0FE4141F4780170BD70B54FF000 -S32508002F60FF0C4CF4E06C1CEA11541DBF1CEA135594EA0C0F95EA0C0F00F0A7F8A4EB05049D -S32508002F8081EA030E52EA03354FEA013100F088804FEA03334FF0805545EA131343EA126356 -S32508002FA04FEA022245EA111545EA10654FEA00260EF000419D4208BF964244F1FD0404F562 -S32508002FC0407402D25B084FEA3202B61A65EB03055B084FEA32024FF480104FF4002CB6EBB0 -S32508002FE0020E75EB030E22BFB61A754640EA0C005B084FEA3202B6EB020E75EB030E22BFCD -S32508003000B61A754640EA5C005B084FEA3202B6EB020E75EB030E22BFB61A754640EA9C006D -S325080030205B084FEA3202B6EB020E75EB030E22BFB61A754640EADC0055EA060E18D04FEAAA -S32508003040051545EA16754FEA06164FEAC30343EA52734FEAC2025FEA1C1CC0D111F4801F95 -S325080030600BD141EA00014FF000004FF0004CB6E711F4801F04BF01430020B4F1FD0C88BF13 -S32508003080BCF5E06F3FF6AFAEB5EB030C04BFB6EB020C5FEA500C50F1000041EB045170BDDB -S325080030A00EF0004E4EEA113114EB5C04C2BFD4EB0C0541EA045170BD41F480114FF0000ECC -S325080030C0013C90E645EA060E8DE60CEA135594EA0C0F08BF95EA0C0F3FF43BAF94EA0C0F6B -S325080030E00AD150EA01347FF434AF95EA0C0F7FF425AF104619462CE795EA0C0F06D152EACC -S3250800310003353FF4FDAE1046194622E750EA410618BF52EA43067FF4C5AE50EA41047FF418 -S325080031200DAF52EA43057FF4EBAE12E74FEA4102B2F1E04324BFB3F5001CDCF1FE5C0DD946 -S3250800314001F0004C4FEAC0024CEA5070B2F1004F40EB830008BF20F00100704711F0804F34 -S3250800316021D113F13872BCBF01F00040704741F480114FEA5252C2F11802C2F1200C10FAE5 -S325080031800CF320FA02F018BF40F001004FEAC1234FEAD32303FA0CFC40EA0C0023FA02F375 -S325080031A04FEA4303CCE77FEA625307D150EA01331EBF4FF0FE4040F44000704701F00040B5 -S325080031C040F0FE4040F40000704700BF10B5054C237833B9044B13B10448AFF30080012387 -S325080031E0237010BD0001002000000000F4AF000808B5034B1BB103490348AFF3008008BD40 -S325080032000000000004010020F4AF000808B500F0A3FB00F0010400F091FE044000F058FD88 -S32508003220044000F0A5FD044000F030FF044000F0F3FB044001F02AF8044000F0C5FD044094 -S3250800324000F0C6F9044000F00DF904421AD104F083FF022000F0FCFE0D4B1B689B0B6422BD -S3250800326002FB03F3002BF4D000BF00BF00BF00BF00BF00BF00BF00BF00BF00BF00BF00BF6A -S32508003280013BEFE7034B186804F0DAFFFEE700BF9C0000201C01002008B5054A002105485C -S325080032A004F06FFF044B1860003818BF012008BD1CB000080D3200081C01002000B585B0A0 -S325080032C0EC468CE80F0000231A4661460548006805F0D2F90121044B186805F05FF805B09A -S325080032E05DF804FB200100202401002008B50146024B186805F052F808BD00BF240100200D -S3250800330030B589B04FF0FF33002207215248006805F091F8044610F0010F0AD114F0020FFC -S3250800332040F0968014F0040FECD0002000F00AF9E8E700231A4602A94848006805F0DEF992 -S325080033409DF808509DF81130012B1DD0022B3BD0002BE3D1072D43D86AB2002ADED0013DEB -S32508003360062DDBD801A252F825F000BFF1330008F9330008013400081D3300080F34000858 -S325080033801934000831340008132D08D9FF228DF81820059A012106A800F05EFDBEE7284691 -S325080033A000F0A6FA01908DF8185004220DF119010DEB020001F024FC9DF81130059A05210D -S325080033C006A800F049FDA9E704220DEB02010DF1090001F015FC0199284600F035FA9DE796 -S325080033E0FF2D9BD1002000F0ADF802F095FE95E7012000F0A7F891E7002000F0A3F88DE72A -S3250800340040F6B831164B186804F08CFF86E70021132000F05FFA81E706228DF818200122A5 -S325080034208DF81920059A022106A800F015FD75E704220DEB02010DF1090001F0E1FB9DED73 -S32508003440010A00F073FC9DED010A00F0AFFC65E7022000F0FDFD65E724010020200100209A -S325080034603001002070B5254804F076FF244B1860041E18BF0124234A0021234804F081FE81 -S32508003480224B186000280CBF002404F00104204A1021082005F0A5F81E4B186000280CBF00 -S325080034A0002404F001041C4E1C4B02220121304604F0E4FE1A4D286000280CBF002404F084 -S325080034C00104184B02220121304604F0D7FE164B186000280CBF002404F001044FF47A71DA -S325080034E0286804F01FFF002814BF002404F001040E4800F0D9FC204670BD00BFB0B000082F -S3250800350024010020C0B00008013300082801002098B0000820010020ED320008E4B0000807 -S325080035202C010020F4B0000830010020BD32000808B50146024B186804F030FF08BD00BFC4 -S325080035403401002010B504460146032000F044FD2146122000F0BEF910BD08B5122000F072 -S32508003560DBF908BD0000000008B5F2EE087AB4EEE70AF1EE10FA01DDB0EE670AF8EE087AB4 -S32508003580B4EEE70AF1EE10FA01D5B0EE670A10EE100AFFF761FB0AA3D3E90023FFF7FEF9D9 -S325080035A009A3D3E90023FFF7D9FCFFF7BFFD00EE100A00F0FBFB00F0010008BDAFF300802F -S325080035C04A0C022B8716344077BE9F1A2F0D414038B5174A0021174804F0D3FD164B186033 -S325080035E0041E18BF0124154804F0B6FE144B186000280CBF002404F00104124B01221146DC -S32508003600114804F03BFE114D286000280CBF002404F001049FED0E0AFFF7A6FF64212868CC -S3250800362004F080FE002814BF002004F0010038BD48B10008553600083801002038B1000827 -S32508003640340100206CB10008313500083C0100200000000008B52DED088BDFED438AB0EE76 -S32508003660688A05E0DFED408AB0EE6A0AFFF77CFFF0EE689AB0EE489A4FF0FF330022012137 -S325080036803A48006804F0D7FE10F0010FF4D0384803F027FAFFF761FF9FED338AF0EE488AB2 -S325080036A00028E5D0002000F037F9002848D1022000F036F9F0EE408A032000F031F9B0EEDA -S325080036C040AA042000F02CF9B0EE40BA062000F027F9F0EE40AA072000F022F9F0EE40BA19 -S325080036E0092000F01DF9B0EE408A052000F018F938EE408A68EE887ADFED1E6A68EE268A5D -S3250800370078EEA98A2AEE28AA38EE497A27EE0B7A87EE266A77EE8A7A77EE867AF4EEE7AA4F -S32508003720F1EE10FA9ED4F4EEE7BAF1EE10FA02DCF0EE67AA98E7F0EE6BAADFED0B8A93E79A -S32508003740002000F0E9F8012804D0F0EE698AB0EE498A8DE700F0E4F8FFF706FFDFED028A98 -S32508003760B0EE688A84E700BF0000000034010020F4030020CDCCCC3D01288CBF00200120BE -S3250800378070470000084B03EB00139B688B4207D8054B03EB0013DB688B4203D20020704754 -S325080037A0002070470120704788B10008084B03EB00139B688B4207DC054B03EB0013DB6870 -S325080037C08B4203DA00207047002070470120704788B100080C4B03EB0013D3ED027AF4EEF4 -S325080037E0C07AF1EE10FA0BD8074B03EB0013D3ED037AF4EEC07AF1EE10FA03DA002070476C -S32508003800002070470120704788B1000808B503010C4AD35C13F0010F09D113F0020F0BD187 -S3250800382013F0040F0BD00846FFF7A6FF03E000EE101AFFF7CFFF08BDFFF7B8FFFBE7FFF797 -S32508003840A1FFF8E788B1000838B503010D4AD35C13F0080F00D038BD04460D464FF0FF3138 -S32508003860094B186804F06BFE29462046FFF7CEFF10B1064B43F83450034B186804F08BFE55 -S32508003880E9E700BF88B10008E00100204001002038B504460D464FF0FF310C4B186804F024 -S325080038A04EFE29462046FFF7B1FF30B9084B03EBC4031A7942F002021A71054B43F83450DF -S325080038C0024B186804F067FE38BD00BFE00100204001002008B5FFF7DBFF08BD00B583B064 -S325080038E08DED010A0199FFF7D3FF03B05DF804FB38B50446064D4FF0FF31286804F01FFE32 -S32508003900044B53F83440286804F045FE204638BDE00100204001002008B5FFF7E9FF08BDA7 -S3250800392008B5FFF7E5FF00EE100A08BD08B5034B03EB00135968FFF7ABFF08BD88B10008A2 -S3250800394010B5002404E0E0B2FFF7F0FF0134A4B2132CF8D910BD000010B5064804F0A5FD04 -S32508003960054B1860041E18BF0124FFF7E9FF204610BD00BFC8B20008E001002008B572B120 -S325080039800D4B60F07F00187000225A7099700B480323838100F088FB00F0010008BD064B7E -S325080039A060F07F001870597004480223838100F07BFB00F00100F1E7EC0100200000002008 -S325080039C010B50C4692B1114B187000225A709A700F480323838100F067FB00F001000D4B89 -S325080039E05A789B7843EA0223238010BD074B187000225A7006480223838100F055FB00F0A5 -S32508003A000100044B5B782380EFE700BFEC01002000000020E401002038B5144804F045FD8C -S32508003A20134D2860041E18BF01244FF0FF3104F086FD002000F062FA002282211046FFF70F -S32508003A409DFF0440002000F069FA012000F056FA002282211046FFF791FF0440012000F0AE -S32508003A605DFA286804F097FD204638BDE4B20008F40100202DE9F04182B00F4690460023F4 -S32508003A800B70ADF8063018B1012854D0012600E001263F4D4FF0FF31286804F050FD30463C -S32508003AA000F02CFA0022A0211046FFF767FF00F00104304600F032FA286804F06CFD642055 -S32508003AC004F0CDFB4FF0FF31286804F038FD304600F014FA01220DF106011046FFF770FF9D -S32508003AE00440304600F01AFA286804F054FD24B3BDF8063013F0010F24D15B08ADF806301D -S32508003B00A8F80030224D4FF0FF31286804F017FD304600F0F3F9002284211046FFF72EFFBF -S32508003B200440304600F0FAF9286804F034FD204602B0BDE8F0810026ABE73B7843F0020354 -S32508003B403B70F4E7124C4FF0FF31206804F0F7FC304600F0D3F9002239460720FFF730FF76 -S32508003B60304600F0DBF9304600F0C8F9002282211046FFF703FF304600F0D0F9206804F018 -S32508003B800AFD3B7843F001033B700024CFE700BFF401002010B52DED028B88B0012004F014 -S32508003BA05EFB08224149424801F0B0FD6EE004244FF0FF313F4B186804F0C1FC00230AE015 -S32508003BC0E1183A4A32F8111008AA02EB830242F8101C01339BB2032BF2D9002325E008AA31 -S32508003BE002EB830151ED047AF8EE677A9FED327A67EE877A9FED317A67EE877A304A92EDAF -S32508003C00007A67EE877A2F4A02EB830292ED007A67EE277A2C4A02EB830292ED007A77EEA6 -S32508003C20C77A41ED087A01339BB2032BD7D9DDED028AB0EE680A0B20FFF750FE9DED038A3A -S32508003C40B0EE480A0C20FFF749FE88EE880A0D20FFF744FE28EE880A0D20FFF73FFEDDEDBE -S32508003C60008AB0EE680A0F20FFF738FE9DED018AB0EE480A1020FFF731FE28EE880A11200E -S32508003C80FFF72CFE0B4B186804F085FC4FF0FF33002203210D48006804F0CDFB10F0020F6A -S32508003CA085D110F0010FF1D0002481E7F8010020280200200C0200200000803D000080393C -S32508003CC04400002020B3000830B300080802002010B50F4A00210F4804F053FA0E4B1860DA -S32508003CE0041E18BF01240D4804F036FB0C4B186000280CBF002404F001040A4804F0D5FB29 -S32508003D00094B186000280CBF002004F0010010BD60B30008953B00081002002050B30008C4 -S32508003D200802002040B300080C020020014B83ED000A70474400002008B50221024B186894 -S32508003D4004F02CFB08BD00BF0802002008B50121024B186804F022FB08BD00BF0802002021 -S32508003D60836D836D836D836DC36CDB6B7047000008B50021034802F007FAB0FA80F04009CA -S32508003D8008BD00BFB4020020DFED067A20EE270A054B93ED007AC0EE077AFCEEE77A17EE67 -S32508003DA0900A704700F07F454800002008B5FFF7EBFF034600221146024802F017FA00F0EC -S32508003DC0010008BDB402002070B5042000F020F91D4C237803432370032000F019F923784A -S32508003DE043EA40032370022000F012F9237843EA80032370012000F00BF9237843EAC0001A -S32508003E00C0B22070114E336843EA40133360104D1049284601F01BFE04463146284601F037 -S32508003E2016FE0443E4B2284601F094FE0443E4B20221284601F0D6FF204310F0FF0F0CBF22 -S32508003E400120002070BD00BF180200204C0000208C02002074000020082901D9002070475D -S32508003E6000B587B012021FFA82FC4CEA03130C4A1278134343F41073009300230193029382 -S32508003E80039304918DF81430012302466946054801F08EFEB0FA80F0400907B05DF804FBCD -S32508003EA0180200208C020020014B1860704700BF1402002030B58FB005AB07AA002101F005 -S32508003EC0ECFE079BC3F300220492C3F301138DF80D309DF82C208DF80C2001AC214605A8FB -S32508003EE000F08EFE034B1D6894E80F00A8470FB030BD00BF14020020436A704708B5064BD8 -S32508003F004FEA401C03EB4010027F818853F80C0002F0EDFC08BD00BF24B4000808B5064B92 -S32508003F204FEA401C03EB4010027E818853F80C0002F0DDFC08BD00BF24B4000870B582B03A -S32508003F40224B1A6E42F001021A661B6E03F001030193019B012500240BE000231D401C4BDD -S32508003F604A0103EB41110431985802F0E1FB0134E4B2042C08D82146154B03EB44139B68CB -S32508003F80002BEAD10123E9E700240EE001231D402046FFF7C3FF0F4B720103EB4611043141 -S32508003FA0985802F0C5FB0134E4B2032C0AD82646084B03EB44139B68012BE8D0112BE5D099 -S32508003FC00023E4E7284602B070BD00BF0010024084B3000824B4000808B559B10B4B4FEA12 -S32508003FE0401C03EB4010027F818853F80C0002F07EFC08BD054B4FEA401C03EB4010027E64 -S32508004000818853F80C0002F072FCF2E724B4000838B504460D4B420103EB4015A9889858E3 -S3250800402002F05EFCEB69012B07D0084B03EB44139B69012B05D0002038BD0128F5D101200D -S32508004040FAE708B10020F7E70120F5E784B3000808B5044B420103EB40108188985802F006 -S325080040604BFC08BD24B400080246002008B10020704700EB8003044951F823309342F7D05B -S32508004080431CD8B2F2E700BFC8B4000808B5044804F062F9034B1860003818BF012008BDFA -S325080040A0ECB400081C02002038B504460378244D03EB830305EB83034FF0FF31586804F0DC -S325080040C03EFA237803EB830305EB8303D96841F002011C4B186804F08EF9237803EB830032 -S325080040E0A389A268616855F8200003F0DBFD00280CBF0125002511D00020237810F0020F90 -S3250800410005F0010518BF002503EB83030C4A02EB8303586804F03FFA284638BD237803EB84 -S325080041208303074A02EB8303D9684FF0FF33002241F002010348006804F07DF9DDE700BF7F -S32508004140C8B400081C02002008B5FFF78DFF00EB8000044B03EB8003D968034B186804F022 -S325080041601DF908BDC8B400081C02002008B5FFF77BFF00EB8000044B03EB8003D968034BAD -S32508004180186804F00BF908BDC8B400081C02002008B5026E826DD26B436DDB6BFFF764FF6A -S325080041A00221024B186804F0F9F808BD1C02002000EE100AB8EEC00ADFED097A20EE270A13 -S325080041C0DFED087A60EE277A9FED077A77EE877A20EE270ADFED057A30EE670A704700BF92 -S325080041E000000039DB8A1F416DE76B4342E0754310B52DED028B84B000238DF80F300A2026 -S3250800420004F02DF8012422E01F4B019300238DF80F30012429E0BDF80C00FFF7C9FF8DED44 -S32508004220020ADDED018AB0EE680A0820FFF756FB9DED028AB0EE480A0920FFF74FFB38EEFB -S32508004240C80A0A20FFF74AFB642004F008F803AA0DF10F010020FFF70DFC0440D4D0BDF82A -S325080042600C00FFF7A5FF8DED010A03AA0DF10F010120FFF7FFFB0440CDD1034B0293002351 -S325080042808DF80F300124CCE77B9488C308B5054A0021054803F075FF044B1860003818BF63 -S325080042A0012008BD08B50008F141000820020020014A024B9A6070470028000800ED00E083 -S325080042C02DE9F04188B0002403940494059406940794364BDA6C42F00402DA64DA6C02F0BB -S325080042E004020092009ADA6C42F00102DA64DA6C02F001020192019ADA6C42F00202DA64A2 -S32508004300DB6C03F002030293029B294F22464FF48041384602F0EBFA22464FF480714FF00A -S32508004320904002F0E4FA234D22466021284602F0DEFA4FF4804303930126049605940694AE -S3250800434003A9384602F0F4F94FF40048CDF80C800494059403A9384602F0EAF94FF4807304 -S32508004360039304960594069403A94FF0904002F0DFF9CDF80C800494059403A94FF090400A -S3250800438002F0D6F9982303930494059403A9284602F0CEF96023039304960594069403A967 -S325080043A0284602F0C5F908B0BDE8F08100100240000800480004004800B583B0164B9A6CC6 -S325080043C042F001029A649A6C02F001020092009A9A6C42F002029A649B6C03F002030193A8 -S325080043E0019B002205210C2001F050FE0C2001F085FE002205210D2001F048FE0D2001F0F6 -S325080044007DFE002205213A2001F040FE3A2001F075FE03B05DF804FB0010024008B5FEF779 -S325080044203BFF024B186803F00BFFFEE72402002072B6FEE700B587B0002300930193029367 -S325080044400393049305932F482F4A026043608360C3600122026108214161037642760421E7 -S32508004460C16180F820308362C36280F83020436380F838201C21C163802101644364826408 -S3250800448000F024FC002832D1204B009306230193072302937F2303930423049300230593A8 -S325080044A06946184800F072FE18BB194B00930C2301936946134800F069FEE0B9154B009305 -S325080044C01223019369460F4800F060FEA8B9124B00931823019369460A4800F057FE70B922 -S325080044E07F21084801F0BCF907B05DF804FBFFF79FFFFFF79DFFFFF79BFFFFF799FFFFF7D3 -S3250800450097FF00BF280200200000045040002019000021438000501D0080F03E08B50D4810 -S325080045200D4B03602023436000238360C3604FF4402202614FF4A0024261037643768376E8 -S325080045400122C2760377437701F0DBF900B908BDFFF76EFF8C0200200064004000B58BB0D6 -S325080045602422002101A806F05AFC1048104B036001F0F8FD98B90022019202920392049210 -S32508004580059201A9094801F048FE50B9002201A9064801F0DDFE30B90BB05DF804FBFFF767 -S325080045A047FFFFF745FFFFF743FF00BFB40200200074004008B51048104B03604FF48273E1 -S325080045C04360002383604FF4E062C2600361012242614FF4007282613022C261036243623C -S325080045E083620722C2620363436303F0EBFA00B908BDFFF71DFF00BF0404002000300140AF -S3250800460008B51148114B0360114B4360002383600122C260036143618361C361036202F006 -S3250800462074F950B90021084802F0CDF938B90021054802F0F6F920B908BDFFF7F9FEFFF70C -S32508004640F7FEFFF7F5FE00BFA003002000540040EC9C901008B50848084B036006234360A1 -S3250800466040F6FF73C3609623836002F006FA00B908BDFFF7DDFE00BFF4030020003000403E -S3250800468000B597B04422002105A806F0C8FB0023009301930293039304934FF4007002F072 -S325080046A02FFA30BB092305934FF4A023069301230A9302230F93032210920422119210222B -S325080046C01292072213921493159305A802F002FB88B90F2300930323019300230293039361 -S325080046E004930421684602F02BFE30B917B05DF804FBFFF79DFEFFF79BFEFFF799FE000076 -S3250800470008B5FFF7D5FD00F0ABFAFFF7B9FFFFF7D7FDFFF751FEFFF78DFEFFF7FFFEFFF74A -S325080047201DFFFFF747FFFFF76BFFFFF793FF03F0E5FC054A0021054803F023FD044B1860C0 -S3250800474003F0EEFCFEE700BF34B500081D4400082402002000B583B00D4B1A6E42F001022D -S325080047601A661A6E02F001020092009A9A6D42F080529A659B6D03F080530193019B0022D8 -S325080047800F216FF0010001F081FC03B05DF804FB0010024070B59EB00446002119911A9181 -S325080047A01B911C911D91542204A806F038FB2268334B9A4201D01EB070BD4FF4804304934C -S325080047C04FF04053169304A802F034FF002850D12C4BDA6C42F40052DA64DA6C02F4005225 -S325080047E00192019ADA6C42F00102DA64DA6C02F001020292029ADA6C42F00202DA64DB6C58 -S3250800480003F002030393039B062319930B261A9600251B9519A94FF0904001F089FF032363 -S3250800482019931A961B9519A9174801F081FF1748174B036045608560C560802303614FF4AF -S32508004840807343614FF4806383612023C3614FF40053036201F022FE70B90C4BE3649C6271 -S3250800486000220521122001F011FC122001F046FCA1E7FFF7DDFDABE7FFF7DAFDEDE700BF03 -S32508004880000004500010024000040048C80200203004024000B589B00023039304930593E2 -S325080048A0069307930268244B9A4202D009B05DF804FB03F5D6339A6D42F000729A659A6D71 -S325080048C002F000720192019ADA6C42F00102DA64DB6C03F001030293029B4FF4C053039323 -S325080048E002230493032306930923079303A94FF0904001F01DFF00220521132001F0C6FB74 -S32508004900132001F0FBFB00220521142001F0BEFB142001F0F3FB00220521152001F0B6FB17 -S32508004920152001F0EBFB00220521162001F0AEFB162001F0E3FBB9E70064004000B589B00E -S325080049400023039304930593069307930268124B9A4202D009B05DF804FB03F5CE339A6DAC -S3250800496042F000529A659A6D02F000520192019ADA6C42F00102DA64DB6C03F001030293A1 -S32508004980029B102303930323049303A94FF0904001F0CEFEDEE700BF0074004010B59CB025 -S325080049A0044600211791189119911A911B91542202A806F034FA2268184B9A4201D01CB082 -S325080049C010BD4023029302A802F034FE18BB144CE36C43F00103E364E36C03F0010300935D -S325080049E0009B4FF4C0631793122318930023199303231A9304231B9317A94FF0904001F0E7 -S32508004A0097FEA36D43F40013A365A36D03F400130193019BD3E7FFF70BFDD8E7005400403C -S32508004A200010024010B588B000230393049305930693079302682F4B9A4201D008B010BDE8 -S32508004A40044603F560431A6E42F480521A661A6E02F480520192019ADA6C42F00102DA641C -S32508004A60DB6C03F001030293029BE023039302230493032306930523079303A94FF0904027 -S32508004A8001F056FE1C481D4B03600123436000238360C3608022026143618361C36103628E -S32508004AA001F0FCFC00BB144BA3659C621448154B036001234360102383600023C3608022FB -S32508004AC0026143618361C361036201F0E7FC70B90B4B63659C6200220521232001F0D6FAEF -S32508004AE0232001F00BFBA9E7FFF7A2FCDBE7FFF79FFCEDE700300140100300201C00024021 -S32508004B005803002030000240FEE7FEE7FEE7FEE7FEE7704708B500F0B3F805F08DFD01286A -S32508004B2000D108BD04F0BEF8FBE7000008B5024801F09BFD08BD00BF1003002008B50248F7 -S32508004B4001F093FD08BD00BF5803002008B5024800F0B0F908BD00BF2802002008B5024852 -S32508004B6001F05DF908BD00BF8C02002008B5024801F055F908BD00BF8C02002008B502482F -S32508004B8001F04DF908BD00BF8C02002008B5024801F045F908BD00BF8C02002008B502482F -S32508004BA003F00EFA08BD00BF0404002008B5024801F05BFD08BD00BFC80200200E4AD2F860 -S32508004BC0883043F47003C2F888300C4B1A6842F001021A60002199601A6822F0A85222F4AD -S32508004BE010221A604FF48052DA601A6822F480221A609961704700BF00ED00E00010024069 -S32508004C0008B50B460146184606F08EF908BD0000104B1B780BB90120704710B504464FF4B5 -S32508004C207A70B0FBF3F30C4A1068B0FBF3F001F085FA68B90F2C01D901200AE00022214655 -S32508004C404FF0FF3001F022FA044B1C60002000E0012010BDA00000209C000020A4000020D2 -S32508004C6010B5032001F000FA0F20FFF7D1FF10B10124204610BD0446FFF76CFDF9E70000BC -S32508004C80034B1B78034A11680B441360704700BFA000002068040020014B1868704700BF99 -S32508004CA06804002038B50446FFF7F6FF0546B4F1FF3F02D0044B1B781C44FFF7EDFF401BB9 -S32508004CC0A042FAD338BD00BFA000002030B583B000230193002800F0DA800446436D13B3A2 -S32508004CE023689A6812F0005F05D09A6822F0204222F03F029A602268936813F0805F1FD1C9 -S32508004D00936823F0104323F03F0343F080539360604B1B689B09604AA2FB03239B090133BF -S32508004D205B00019309E0FFF735FD0023A36584F85030D5E7019B013B0193019B002BF9D185 -S32508004D402268936813F0805F78D1636D43F010036365A36D43F00103A3650120936813F049 -S32508004D60040300D00123616D11F0100F40F08880002B40F08580636D23F4817343F0020391 -S32508004D806365936813F0010F0BD1444B9B6813F0010F06D1636842498A6822F47C12134395 -S32508004DA08B60627E636B43EA4233E2681343A268134394F8202043EA0243012A40D0A26A25 -S32508004DC022B102F47072E16A0A4313432168CD68344A2A401A43CA6021688B6813F0040379 -S32508004DE000D001238A6812F0080200D00122B3B9AAB9237E94F83020520042EA8332CB680E -S32508004E0023F4804323F002031343CB6094F83830012B1AD02268136923F0010313612369EA -S32508004E20012B24D02268136B23F00F031363636D23F0030343F00103636526E000208DE71F -S32508004E40626A013A43EA4243B9E721680B6923F4FF6323F00403E26B256C2A43656C2A43D2 -S32508004E60A56C2A43134343F001030B61D7E721680B6B23F00F03E269013A13430B63D6E7C4 -S32508004E80636D43F010036365012003B030BD0120FBE700BF9C000020632D3E0500000450C0 -S32508004EA00003045007C0F0FF08B5806AFEF74EFF08BD704770B5044603681E685D6816F047 -S32508004EC0020F10D015F0020F0DD0436D13F0100F03D1436D43F400634365204600F010FDE5 -S32508004EE0236802221A6016F0040F02D015F0040F05D116F0080F3AD015F0080F37D0636D88 -S32508004F0013F0100F03D1636D43F4007363652368DA6812F4406F24D1DA6812F4005F20D13C -S32508004F201A6812F0080F1CD09A6812F0040F10D15A6822F00C025A60636D23F480736365A6 -S32508004F40636D13F4805F0CD1636D43F00103636507E0636D43F010036365A36D43F00103D5 -S32508004F60A3652046FEF7E8FE23680C221A6016F0200F02D015F0200F05D116F0400F4CD025 -S32508004F8015F0400F49D0636D13F0100F03D1636D43F4005363652368DA6C12F0C00F2AD111 -S32508004FA00121DA6812F4406F27D10120DA6871B312F0007F03D050B312F4005F27D1196816 -S32508004FC011F0400F23D012F4001F20D19A6812F0080F14D15A6822F060025A60636D23F493 -S32508004FE080536365636D13F4807F10D1636D43F0010363650BE00021D3E70020D6E7636D0F -S3250800500043F010036365A36D43F00103A365204600F072FC236860221A6016F0800F02D073 -S3250800502015F0800F2DD116F4807F02D015F4807F32D116F4007F02D015F4007F38D116F0F8 -S32508005040100F17D015F0100F14D0636B23B12368DB6813F0010F0AD0636D43F48063636525 -S32508005060A36D43F00203A3652046FEF779FE236810221A6016F4806F02D015F4806F23D112 -S3250800508070BD636D43F4803363652046FFF711FF236880221A60C6E7636D43F40033636591 -S325080050A0204600F02BFC23684FF480721A60C0E7636D43F480236365204600F020FC236815 -S325080050C04FF400721A60BAE7636D43F480436365A36D43F00803A36523684FF480621A60E0 -S325080050E0204600F00AFCCBE708B50346806A426D12F0500F30D1436D43F400734365036826 -S325080051001A6812F0080F14D0DA6812F4406F20D1DB6813F4005F1CD1436D23F48073436522 -S32508005120436D13F4805F14D1436D43F0010343650FE0DB6813F0020F0BD1436D23F480737B -S325080051404365436D13F4805F03D1436D43F001034365FEF7F1FD08BD426D12F0100F04D153 -S32508005160C26C526B18469047F5E7FEF7F9FDF2E708B5806A436D43F040034365836D43F0C9 -S3250800518004038365FEF7ECFD08BD0000F0B583B00022019290F85020012A00F03F820346C5 -S325080051A0012280F850200268926812F0040F09D0426D42F0200242650120002283F85020AC -S325080051C003B0F0BD4A68052A08D8023A032A68D8DFE802F0025D60630C224A601D684C680B -S325080051E03035220A920002F00C02A85804F01F0E1F2404FA0EF420EA04000C68C4F3846CF1 -S325080052000CFA0EFC40EA0C00A8501C68A26812F0040200D00122A06810F0080000D00120B8 -S325080052200AB9002840D01868826812F0010F17D10A68CD68D0F8B040C2F3120C24EA0C04B1 -S3250800524005F0180CAE4D25FA0CF52A40C2F312022243C0F8B020C868AA4A904200F0B880CE -S325080052600A68A9490A4200F0D581A849896801F0E074A748824200F07F81A648824200F0BE -S32508005280A281A548824200F0B281002095E712224A60A3E718224A60A0E74FF480724A60BB -S325080052A09CE706224A6099E70E688D681434720E920002F00402A058C6F3045C072606FA10 -S325080052C00CF620EA060005FA0CF52843A0504C691868C268C2F3C102520094400D69042DAF -S325080052E00ED00E68603050F825708C4A3A4006F0F8463443224342F0004240F8252092E715 -S32508005300026E046EC4F384640A68C2F3120585BBC2F38462944234D01C68626E606EC0F336 -S3250800532084600A68C2F3120585BBC2F38462904234D01C68A26EA06EC0F384600A68C2F32C -S32508005340120585BBC2F38462904234D01C68E26EE06EC0F384600A68C2F3120585BBC2F38B -S32508005360846290427FF45FAFE26E22F00042E26659E792FAA2F212B1B2FA82F2CAE72022C4 -S32508005380C8E7026E22F000420266C5E792FAA2F212B1B2FA82F2CAE72022C8E7626E22F0F1 -S325080053A000426266C5E792FAA2F212B1B2FA82F2CAE72022C8E7A26E22F00042A266C5E76C -S325080053C092FAA2F212B1B2FA82F2CAE72022C8E71C680A68C2F31205002D3BD1900E013050 -S325080053E000F01F0009288CBF00200120002869D0002D3ED1900E0130800600F0F840002D8C -S3250800540043D14FEA926C0CF1010C0CF01F0C012606FA0CF63043002D46D1920E013202F05D -S325080054201F0202EB4202120510438D6804F1140E420E920002F004025EF80240C0F304501D -S325080054400726864024EA060C85404CEA05054EF8025005E792FAA2F048B1B0FA80F0013040 -S3250800546000F01F0009288CBF00200120BEE72020F5E792FAA2F030B1B0FA80F001308006C1 -S3250800548000F0F840BBE72020F8E792FAA2F64EB1B6FA86F6013606F01F064FF0010C0CFA22 -S325080054A006F6B7E72026F5E792FAA2F242B1B2FA82F2013202F01F0202EB42021205B3E7C7 -S325080054C02022F6E765BB900E0130800600F0F84095BB4FEA926C0CF1010C0CF01F0C012623 -S325080054E006FA0CF63043B5BB920E013202F01F0202EB42021E3A120542F00072104394E7C1 -S32508005500FFFF070000007F400000088000030450000052C7000084CB0100008000F0FF03FF -S3250800552092FAA2F030B1B0FA80F00130800600F0F840CDE72020F8E792FAA2F64EB1B6FABF -S3250800554086F6013606F01F064FF0010C0CFA06F6C8E72026F5E792FAA2F25AB1B2FA82F205 -S32508005560013202F01F0202EB42021E3A120542F00072C3E72022F3E711F4000F7FF47DAE1B -S325080055801968274A914201D0002016E644F400022448816821F0E0710A438260224A126845 -S325080055A092092249A1FB02129209013202EB42029200019202E0019A013A0192019A002AF3 -S325080055C0F9D10020F9E511F0807F7FF45AAE1968134A914201D00020EFE544F08072114885 -S325080055E0816821F0E0710A4382600020E5E511F4800F11D119680A4A914201D00020DCE569 -S3250800560044F480020748816821F0E0710A4382600020D2E50020D0E50020CEE50220CFE5A4 -S3250800562000000450000304509C000020632D3E0530B583B00023019303689A6812F0010FD4 -S3250800564058D1044699682D4A114219D19A6822F0004222F03F0242F001029A60284B9B68C6 -S3250800566013F4000F1CD0274B1B689B09264AA2FB03239B09013303EB43039B0001930CE027 -S32508005680436D43F010034365836D43F001038365012030E0019B013B0193019B002BF9D121 -S325080056A0FFF7FAFA054623681A6812F0010F1FD19A6812F0010F07D19A6822F0004222F044 -S325080056C03F0242F001029A60FFF7E6FA431B022BE9D923681B6813F0010FE4D1636D43F050 -S325080056E010036365A36D43F00103A365012002E0002000E0002003B030BD00BF3F00008031 -S32508005700000304509C000020632D3E0570B504460068806810F0040F4ED10E46154694F869 -S325080057205030012B4AD0012384F850302046FFF77FFF00283CD1636D23F4706323F0010395 -S3250800574043F480736365636D13F4805F2DD0A36D23F00603A365E36C194ADA62E36C194AC2 -S325080057601A63E36C184A5A6323681C221A60002384F850302268536843F010035360226806 -S32508005780D36843F00103D36021682B4632464031E06C00F007FF2268936823F0004323F043 -S325080057A03F0343F00403936007E00023A365D2E7002384F8503000E0022070BD0220FCE74E -S325080057C0E9500008A94E00087151000838B504460268936813F0020300D00123916811F01F -S325080057E0010F39D0002B39D1936803F00D03012B09D0636D43F010036365A36D43F0010325 -S32508005800A365012029E0936823F0004323F03F0343F002039360236803221A60FFF73CFA21 -S32508005820054623689B6813F0010F13D0FFF734FA401B0228F5D923689B6813F0010FF0D0B3 -S32508005840636D43F010036365A36D43F00103A365012002E0002000E0002038BD0020FCE7F2 -S3250800586030B583B00023019390F85030012B41D004460D46012380F85030FFF7A7FF80BB76 -S32508005880636D23F4885323F0020343F0020363652268936823F0404323F03F0305F08045F6 -S325080058A02B4343F00043936023689B68002B06DB636D23F0030343F00103636515E0019BF0 -S325080058C001330193019BB3F5912FEDD3636D23F0120343F010036365002384F850300120E8 -S325080058E006E0636D43F010036365002384F8503003B030BD0220FBE7704770477047704737 -S325080059007047002800F0A18038B5044690F82030D3B12268136843F001031360FFF7BCF99C -S32508005920054623685A6812F0010F10D1FFF7B4F9401B0A28F5D9636A43F4003363620523AC -S3250800594084F82030012038BDFEF7A4FFE1E71A6822F002021A60FFF79FF9054623685A68BF -S3250800596012F0020F0DD0FFF797F9401B0A28F5D9636A43F400336362052384F82030012037 -S32508005980E1E7227E012A3DD01A6822F080021A60637E012B3BD02268136823F040031360E3 -S325080059A0A37E012B39D02268136823F020031360E37E012B37D02268136843F01003136083 -S325080059C0237F012B35D02268136823F008031360637F012B33D02268136823F004031360AD -S325080059E0A368E268134322691343626913436268013A21681343CB6100206062012384F85A -S32508005A002030A0E71A6842F080021A60C0E72268136843F040031360C2E72268136843F07B -S32508005A2020031360C4E72268136823F010031360C6E72268136843F008031360C8E72268DD -S32508005A40136843F004031360CAE701207047026890F82030013BDBB2012B05D9436A43F48E -S32508005A60802343620120704730B4D2F8003243F00103C2F800324B6903F01F03012000FA11 -S32508005A8003F3D2F81C026FEA030C20EA0300C2F81C02C869B0B9D2F80C020CEA0000C2F8AB -S32508005AA00C028C884869CD6844EA0544483042F830400C8848698D6844EA0544483002EB21 -S32508005AC0C0004460C86901281BD0886980BBD2F804020CEA0000C2F80402086970BBD2F8F7 -S32508005AE014020CEA0000C2F81402096A01292BD0D2F8003223F00103C2F80032002030BC19 -S32508005B007047D2F80C021843C2F80C028C8848690D6844EA0544483042F830408C8948692C -S32508005B208D6844EA0544483002EBC0004460CCE7D2F804021843C2F80402CEE7D2F81402EF -S32508005B401843C2F81402D0E7D2F81C120B43C2F81C32CDE770B5044690F82050EDB2012D1F -S32508005B6006D0436A43F4002343620125284670BD022380F820300268136823F00103136078 -S32508005B80FFF78AF8064623685B6813F0010F0CD0FFF782F8831B0A2BF5D9636A43F40033AE -S32508005BA06362052384F82030E0E700256562DDE730B590F820C00468A4680CF1FF3C5FFA51 -S32508005BC08CFCBCF1010F62D814F0E05F59D0C4F3016C012404FA0CF41C608B68002B3DD1DD -S32508005BE00D68CB68046843EA45550CF118031B01E55003680C690CF1180E03EB0E135C6085 -S32508005C000B7D012B35D0D17993791B0443EA0163517943EA012314790168234301EB0C1137 -S32508005C20C1F88C31D17893781B0443EA0163517843EA0123117802680B4302EB0C12C2F8BC -S32508005C40883102680CF1180C4FEA0C1C52F80C3043F0010342F80C3000201DE04C6843EA60 -S32508005C60C403CC6823430CF11804240105682B51BFE7036803EB0E13596841F480715960CE -S32508005C80C1E7436A43F400134362012004E0436A43F480234362012030BD90F820C00CF10E -S32508005CA0FF3C5FFA8CFCBCF1010F00F2958030B451B90468E46814F0030F10D1436A43F475 -S32508005CC000134362012077E00468246914F0030F05D1436A43F40013436201206CE001F1A6 -S32508005CE01B04240105682C5904F004049460002C64D101F11B04240105682C59640D146002 -S32508005D00046801F11B0C4FEA0C1C54F80C4004F00204D46004686444646804F00F0414616D -S32508005D20046864446468C4F307249461046864446468240C5461026802EB0112D2F8B821CC -S32508005D401A70026802EB0112D2F8B821C2F307225A70026802EB0112D2F8B821C2F30742EB -S32508005D609A70026802EB0112D2F8B821120EDA70026802EB0112D2F8BC211A71026802EBA1 -S32508005D800112D2F8BC21C2F307225A71026802EB0112D2F8BC21C2F307429A71026802EB21 -S32508005DA00112D2F8BC21120EDA7179B90268D36843F02003D360002030BC704701F11B047C -S32508005DC0240105682C59E408546099E70268136943F020031361EEE7436A43F480234362CD -S32508005DE00120704790F82030013BDBB2012B05D9436A43F4802343620120704702685369E8 -S32508005E000B43536100207047704770477047704770477047704770477047704770472DE9A8 -S32508005E20F84F054603685C69D3F804809F68D3F80CB0D3F810A0D3F8189014F001063BD0B1 -S32508005E4017F0010616D001229A6017F0020F08D117F0040F0CD117F0080606D04FF4805637 -S32508005E6008E0FFF7D1FF002604E0FFF7D0FF01E04FF4006617F4807F0DD02B684FF480725E -S32508005E809A6017F4007F40F0868017F4806F00F0868046F4005617F4803F0DD02B684FF43D -S32508005EA080329A6017F4003F40F0838017F4802F00F0838046F4004614F0080F07D01BF081 -S32508005EC0100F04D046F400762B681022DA6014F0040F02D01BF0080F79D114F0020F04D0D4 -S32508005EE02B68DB6813F0030F78D114F0400F07D01AF0100F04D046F480662B6810221A61D9 -S32508005F0014F0200F02D01AF0080F6BD114F0100F04D02B681B6913F0030F6AD114F4003F6C -S32508005F2002D018F0100F68D114F4803F02D018F0080F69D114F4004F7AD018F0040F74D02F -S32508005F4014F4807F04D019F0010F01D046F0010614F4007F04D019F0020F01D046F00206AD -S32508005F6014F4806F04D019F0040F01D046F0040614F4006F59D019F0700956D0B9F1400FDA -S32508005F8065D058D8B9F1200F5ED0B9F1300F42D146F0200644E02846FFF737FF7BE717F404 -S32508005FA0006F02D046F4804675E72846FFF730FF71E72846FFF72AFF7EE717F4002F02D04D -S32508005FC046F4803678E72846FFF723FF74E72B680822DA602846FFF71DFF7EE72846FDF745 -S32508005FE069FF82E72B6808221A612846FFF714FF8CE72846FFF70FFF90E72B6810225A6038 -S325080060002846FFF70AFF8FE72B6808225A602846FFF704FF8EE7B9F1100F01D146F008065D -S325080060202A68936923F0700393612B6804225A609EB9BDE8F88FB9F1500F0BD0B9F1600F57 -S32508006040EED146F48076EBE746F01006E8E746F04006E5E746F08006E2E76B6A33436B6271 -S325080060602846FDF749FFE4E7074AD36823F4E0631B041B0C000200F4E060034343F0BF63A0 -S3250800608043F40033D360704700ED00E000B5194BDB68C3F30223C3F1070CBCF1040F28BF2C -S325080060A04FF0040C03F1040EBEF1060F18D9033B4FF0FF3E0EFA0CFC21EA0C0199400EFA05 -S325080060C003FE22EA0E020A4300280BDB1201D2B200F1604000F5614080F800235DF804FB8D -S325080060E00023E5E700F00F001201D2B2024B1A54F4E700BF00ED00E014ED00E0002807DB00 -S3250800610000F01F02400901239340024A42F82030704700BF00E100E0BFF34F8F0549CA6803 -S3250800612002F4E062044B1343CB60BFF34F8F00BFFDE700BF00ED00E00400FA050138B0F1AD -S32508006140807F0BD24FF0E0235861054AF02182F823100020986107221A6170470120704701 -S3250800616000ED00E070B110B50446037933B102232371002020610123237110BD4371FEF72C -S32508006180DDFBF4E7012070474279012A2CD010B4034601224271022018711C68206801F0F9 -S325080061A0100C02FA0CF20243226089B919680A6802F03C02042A06D001221A7100205871F4 -S325080061C05DF8044B70474A6842F001024A60F3E719680A6802F47012B2F5802FECD14A68BB -S325080061E042F002024A60E7E70220704710B483B0002401940068019051B901990A44083235 -S325080062000192019A1360002003B05DF8044B704701990A4414320192F3E7F8B54379012B71 -S3250800622000F0948004460D46164601234371022303710B68042B32D02B69012B79D02068AD -S32508006240C16B06F010020723934021EA03012B68AE683343EE68334393400B43C363206836 -S3250800626003684FF48041914023EA010303602068016840F6FC73934021EA03016B6893403E -S325080062800B43036020680368C02101FA02F223EA020303600123237100206071F8BDFEF7B4 -S325080062A0FBFC07467EB123685B6B002B3ADAFEF7F3FCC01B0128F6D9236943F008032361C8 -S325080062C003202071EAE723685B6B13F4004F0BD0FEF7E2FCC01B0128F5D9236943F008033A -S325080062E0236103202071D9E70120FEF7DBFC2368AA691A642068836C06F0100240F2FF31AE -S32508006300914023EA0103E96991400B4383642068C36CFF21914023EA0103296A91400B43CA -S32508006320C36489E70120FEF7BDFC2368AA695A64E0E721688A6B06F010001F23834022EA31 -S3250800634003026B69834013438B6378E70220A5E7002800F083802DE9F04F83B08946044686 -S325080063600379DBB2022B7BD04379012B7AD0012141710068C56B02F010070723BB4005EAD3 -S32508006380030B0568B94025EA010101602068C16B6FEA030A21EA0303C3632368019392B94E -S325080063A0019B08330193019B4FF400621A60226813684FF4804808FA07F843EA08031360ED -S325080063C00825102605E0019B14330193EBE72E446D089DB121688B6B1F22BA4023EA02031D -S325080063E006FA07F213438B630120FEF75BFC23685B6B38EA0303EAD1761BE9E721688B6BD1 -S325080064001F22BA40D54323EA020306FA07F213438B630120FEF746FC23685A6B18EA020F11 -S3250800642006D101369A6B154006FA07F73D439D632268136823EA08031360C9F8146001237F -S32508006440C9F810302268D36B0AEA030A4AEA0B03D3630020607103B0BDE8F08F012070474C -S325080064600120F8E70220F6E730B4446C04F01C0C012404FA0CF4056C6C60046863608368E5 -S32508006480102B05D0036899600368DA6030BC704703689A600368D960F8E70000002873D0DF -S325080064A010B403460068394A90424AD8384A02443849A1FB0212120992005A64364A1A6480 -S325080064C0022283F82520016821F4FF4121F070019A68DC6822431C6922435C6922439C69C6 -S325080064E02243DC6922431C6A22430A4302609A68B2F5804F1BD0196C274A91422CD0264A4D -S32508006500D2F8A814586C00F01C0C0F2000FA0CF021EA0001C2F8A814D2F8A81458685C6C56 -S3250800652004F01C0C00FA0CF00143C2F8A8140020D863012283F8252083F824005DF8044B00 -S325080065407047164A02441349A1FB0212120992005A64134A1A64B3E7D2F8A810586C00F0AE -S325080065601C0C0F2000FA0CF021EA0001C2F8A810D2F8A81058685C6C04F01C0C00FA0CF026 -S325080065800143C2F8A810D2E70120704707040240F8FFFDBFCDCCCCCC00000240F8FBFDBF84 -S325080065A00004024038B5044690F82400012832D0012084F8240094F82500C0B2012804D098 -S325080065C0002384F82430022038BD022084F825000020E0632568286820F001002860204661 -S325080065E0FFF742FF236B5BB12268136843F00E0313602268136843F0010313600020E3E767 -S325080066002268136823F0040313602268136843F00A031360EDE70220D6E708B590F82530D5 -S32508006620DBB2022B03D00423C363012008BD0268136823F00E0313600268136823F0010314 -S325080066401360436C03F01C03016C012202FA03F34B6080F82520002380F82430836B13B16D -S3250800666098470020E2E70020E0E738B5036C196804682568436C03F01C0304229A400A427A -S3250800668015D015F0040F12D0236813F0200F03D1236823F004032360436C03F01C02016C27 -S325080066A0042393404B60036B03B1984738BD02229A400A421CD015F0020F19D0236813F06E -S325080066C0200F06D1236823F00A032360012380F82530436C03F01C02016C022393404B60B7 -S325080066E0002380F82430C36A002BDFD09847DDE7082202FA03F30B42D8D015F0080FD5D021 -S32508006700236823F00E032360436C03F01C03016C012202FA03F34B60C26380F82520002346 -S3250800672080F82430436B002BC0D09847BEE70000F0B583B0002362E085685E000324B440EF -S3250800674025EA0405CC68B4402C438460456825EA0C054C68C4F300149C402C4344605FE01E -S32508006760DD08083550F8254003F0070C4FEA8C0C4FF00F0E0EFA0CFE24EA0E0E0C6904FA5A -S325080067800CF444EA0E0440F8254060E0022400E0002404FA0EF42C430CF1020C4C4D45F854 -S325080067A02C404C4CA568D44325EA02064F6817F4801F01D042EA0506464DAE60ED6804EA3F -S325080067C005064F6817F4001F01D042EA0506414DEE606D6804EA05064F6817F4003F01D03B -S325080067E042EA05063B4D6E602D682C404E6816F4803F01D042EA0504364A146001330A68DE -S3250800680032FA03F462D04FF0010C0CFA03FC1CEA0202F3D04C6804F00304013C012C8BD97A -S325080068204C6804F00304032C0CD0C4685D004FF0030C0CFA05FC24EA0C0C8C68AC4044EA7E -S325080068400C04C4604C6804F00304022C88D004684FEA430E4FF0030C0CFA0EFC24EA0C0C47 -S325080068604C6804F0030404FA0EF444EA0C0404604C6814F4403FC1D0174C256E45F00105BC -S325080068802566246E04F001040194019C4FEA930C0CF102050E4C54F8255003F0030E4FEA6E -S325080068A08E0E0F2404FA0EF425EA0405B0F1904F3FF46EAF094CA04206D004F58064A04247 -S325080068C03FF464AF072464E7012462E703B0F0BD00000140000401400010024000040048FC -S325080068E00369194201D001207047002070470AB18161704781627047436901EA030221EAAE -S32508006900030141EA024181617047002859D010B5044690F84130002B43D0242384F8413093 -S325080069202268136823F0010313606368226823F0706313612268936823F400439360E368EE -S32508006940012B33D0A368226843F404439360E368022B31D02268536843F0007343F4004316 -S3250800696053602268D36823F40043D360236962691343A169226843EA0123D360E369216A68 -S3250800698022680B4313602268136843F00103136000206064202384F84130206384F842009A -S325080069A010BD80F84030FDF7F9FFB6E7A368226843F400439360CAE723684FF400625A60EE -S325080069C0C8E701207047034690F84120D2B2202A23D190F84020012A21D0012280F840202F -S325080069E0242280F841200068026822F0010202601868026822F480520260186802681143AF -S32508006A00016019680A6842F001020A60202283F84120002083F840007047022070470220CA -S32508006A207047034690F84120D2B2202A21D190F84020012A1FD0012280F84020242280F8E4 -S32508006A4041200068026822F0010202601868026822F4706242EA0122026019680A6842F0D6 -S32508006A6001020A60202283F84120002083F840007047022070470220704700282FD038B525 -S32508006A80044603684CF6CC421A60036845F255521A60036842685A60036882689A60FEF793 -S32508006AA0FBF805462368DA6812F0070F0BD0FEF7F3F8401B3128F5D92368DB6813F0070F81 -S32508006AC0F0D0032005E01969E268914202D01A61002038BD4AF6AA221A600020F9E7012038 -S32508006AE0704703684AF6AA221A60002070470000024B186800F4C060704700BF0070004002 -S32508006B00B0F5007F0FD01F4B1B6803F4C063B3F5806F34D01B4A136823F4C06343F480638E -S32508006B20136000207047174B1B6803F4C063B3F5007F20D0134A136823F4C06343F400732B -S32508006B401360114B1B68322202FB03F30F4AA2FB03239B0C013300E0013B0A4A526912F466 -S32508006B60806F01D0002BF7D1064B5B6913F4806F03D10020704700207047032070470020CD -S32508006B80704700BF007000409C00002083DE1B4330B583B00446204B9B6D13F0805F0BD0B4 -S32508006BA0FFF7A6FFB0F5007F17D0802C1FD82DD0702C2DD000211BE0174DAB6D43F080534A -S32508006BC0AB65AB6D03F080530193019BFFF790FFAB6D23F08053AB65E4E7802C03D9A02CD7 -S32508006BE003D9022104E0002102E0012100E003210A4A136823F007030B431360136803F060 -S32508006C0007038B4206D1002003B030BD0221EFE70121EDE70120F7E7001002400020024056 -S32508006C20284A9368D26802F0030213F00C030AD00C2B06D0042B1FD0082B20D00020024606 -S32508006C4010E0012AF6D11F4A126812F0080F0CD11C4AD2F89420C2F303221B4951F82220BE -S32508006C6043B100200C2B0DD07047164A1268C2F30312F2E71046F5E714480022F2E71448C5 -S32508006C800022EFE70F4BDB6803F00303022B16D0032B00D10E4A0B49CB68C3F30213013368 -S32508006CA0C868C0F3062002FB00F0B0FBF3F0CB68C3F3416301335B00B0FBF3F0D4E7034A90 -S32508006CC0E9E700BF0010024068B500080024F400005A6202002800F01C83F0B583B00446F1 -S32508006CE0964B9D6805F00C05DE6806F00306036813F0100F5AD0E5B10C2D18D0A369002BB0 -S32508006D0000F0BB808D4A136843F001031360FDF7C3FF0746894B1B6813F0020F40F09A8086 -S32508006D20FDF7BAFFC01B0228F4D90320FCE2012EE4D1824B1B6813F0020F03D0A369002B73 -S32508006D4000F0E982206A7D4B1B6813F0080F5BD07A4B1B6803F0F00398425CD8774B1A6830 -S32508006D6042F008021A601A6822F0F002216A0A431A605A6822F47F42E16942EA01225A608B -S32508006D80002D60D0FFF74CFF6C4B9B68C3F303136B4AD35C03F01F03D8406A4B18606A4BCE -S32508006DA01868FDF735FF002840F0BE82236813F0010F00F08180082D75D00C2D71D0636837 -S32508006DC0B3F5803F00F09780B3F5A02F00F099805A4B1A6822F480321A601A6822F4802214 -S32508006DE01A606368002B00F09980FDF755FF0746524B1B6813F4003F5ED1FDF74DFFC01BC7 -S32508006E006428F5D903208FE24C4BD3F894301B0903F0F003A0E7FFF7BBFE002840F07D82B9 -S32508006E20464B1A6842F008021A601A6822F0F002216A0A431A605A6822F47F42E16942EA94 -S32508006E4001225A609EE7206AFFF7A2FE002899D0012069E2394B1A6842F008021A601A6867 -S32508006E6022F0F002216A0A431A605A6822F47F42E16942EA01225A6098E7304A136823F03B -S32508006E8001031360FDF708FF07462C4B1B6813F0020F8BD0FDF700FFC01B0228F5D90320D3 -S32508006EA042E2032E8BD1254B1B6813F4003F03D06368002B00F03382236813F0020F58D0A5 -S32508006EC0042D45D00C2D41D0E368002B77D01B4A136843F480731360FDF7DEFE0646174B5C -S32508006EE01B6813F4806F61D1FDF7D6FE801B0228F5D9032018E2114A136843F4803313602E -S32508006F006FE703F18043A3F53C331A6842F480221A601A6842F480321A6062E7FDF7BCFEA0 -S32508006F200746064B1B6813F4003FC5D0FDF7B4FEC01B6428F5D90320F6E100BF0010024061 -S32508006F4058B500089C000020A4000020022EBBD1A44B1B6813F4806F03D0E368002B00F031 -S32508006F60E081A04A536823F0F853216943EA01635360236813F0080F4CD063699BB3994A13 -S32508006F80D2F8943043F00103C2F89430FDF784FE0646944BD3F8943013F0020F3AD1FDF75D -S32508006FA07BFE801B0228F4D90320BDE18D4A536823F0F853216943EA01635360D9E7894AA6 -S32508006FC0136823F480731360FDF766FE0646854B1B6813F4806FCCD0FDF75EFE801B02280D -S32508006FE0F5D90320A0E17F4AD2F8943023F00103C2F89430FDF750FE06467A4BD3F8943043 -S3250800700013F0020F06D0FDF747FE801B0228F4D9032089E1236813F0040F7AD0714B9B6D71 -S3250800702013F0805F36D16F4B9A6D42F080529A659B6D03F080530193019B01266A4B1B6838 -S3250800704013F4807F28D0A368012B39D0052B3FD0644BD3F8902022F00102C3F89020D3F830 -S32508007060902022F00402C3F89020A368002B3DD0FDF712FE07465B4BD3F8903013F0020FF6 -S3250800708046D1FDF709FEC01B41F288339842F2D9032049E10026D1E7534A136843F48073F5 -S325080070A01360FDF7F9FD07464F4B1B6813F4807FC9D1FDF7F1FDC01B0228F5D9032033E16F -S325080070C0484AD2F8903043F00103C2F89030CCE7444BD3F8902042F00402C3F89020D3F8AA -S325080070E0902042F00102C3F89020BEE7FDF7D4FD07463C4BD3F8903013F0020F08D0FDF789 -S32508007100CBFDC01B41F288339842F2D903200BE1E6B9236813F0200F35D0636AE3B1314ADF -S32508007120D2F8983043F00103C2F89830FDF7B4FD06462C4BD3F8983013F0020F23D1FDF7FF -S32508007140ABFD801B0228F4D90320EDE0254A936D23F080539365DCE7224AD2F8983023F0D6 -S325080071600103C2F89830FDF797FD06461D4BD3F8983013F0020F06D0FDF78EFD801B02287E -S32508007180F4D90320D0E0A36A002B00F0CC80022B17D00C2D00F0CC80124A136823F0807367 -S325080071A01360FDF779FD04460E4B1B6813F0007F00F0A880FDF770FD001B0228F4D903208E -S325080071C0B2E0084BDB6803F00301E26A91420DD00C2D00F0AB80034B1B6813F0806F2FD070 -S325080071E00120A1E0001002400070004003F07002216B0139B2EB011FEAD103F4FE42616B37 -S32508007200B2EB012FE4D103F07842A16BB2EBC16FDED103F4C001E26B5208013AB1EB425FD2 -S32508007220D6D103F0C063226C5208013AB3EB426FCED1404B1B6813F0007F49D0002073E056 -S325080072403C4A136823F080731360FDF725FD0546384B1B6813F0007F06D0FDF71DFD401B7E -S325080072600228F5D903205FE0324AD36832491940E36A206B013843EA0013606B43EA0023AF -S32508007280E06B4008013843EA4053206C4008013843EA4063A06B43EAC0631943D160136814 -S325080072A043F080731360D36843F08073D360FDF7F3FC04461F4B1B6813F0007F06D1FDF72C -S325080072C0EBFC001B0228F5D903202DE000202BE0184B1A6842F080721A60DA6842F0807262 -S325080072E0DA60FDF7D9FC0446124B1B6813F0007F06D1FDF7D1FC031B022BF5D9032013E00A -S32508007300002011E00B4AD1680C4B0B40D36000200AE001207047012006E0012004E00120DC -S3250800732002E0012000E0002003B0F0BD0120FBE70120F9E7001002408C809D01FCFFEEFEF5 -S32508007340002800F0AF8070B50D460446594B1B6803F007038B420BD2564A136823F0070310 -S325080073600B431360136803F007038B4240F09C80236813F0020F0CD0A2684F4B9B6803F098 -S32508007380F0039A4205D94C498B6823F0F0031A438A60236813F0010F39D06368032B09D0E4 -S325080073A0022B26D063BB444A126812F0020F06D1012076E0404A126812F0007F76D03E49C3 -S325080073C08A6822F0030213438B60FDF765FC0646394B9B6803F00C036268B3EB820F16D04C -S325080073E0FDF75AFC801B41F288339842F0D9032057E0314A126812F4003FE0D1012050E073 -S325080074002D4A126812F4806FD9D1012049E0236813F0020F0CD0A268274B9B6803F0F003A4 -S325080074209A4205D224498B6823F0F0031A438A60204B1B6803F00703AB420AD91D4A136841 -S3250800744023F007032B431360136803F00703AB422ED1236813F0040F06D0174A936823F4D2 -S32508007460E063E1680B439360236813F0080F07D0114A936823F46053216943EAC103936027 -S32508007480FFF7CEFB0C4B9B68C3F303130B4AD35C03F01F03D8400A4B18600A4B1868FDF7B2 -S325080074A0B7FB70BD012070470120FAE70120F8E70120F6E7002002400010024058B500083E -S325080074C09C000020A4000020F8B504460F46584BDB6813F0030F18D0554BDB6803F0030313 -S325080074E00268934202D001252846F8BD002A00F09D804F4BDB68C3F3021301334268934292 -S3250800750001D00125F0E7002509E00368022B56D0032B5BD0012B41D00125002DE4D1444A97 -S32508007520136823F080631360FDF7B6FB0646404B1B6813F0006F05D0FDF7AEFB831B022BAB -S32508007540F5D90325002DCFD1002F4DD138490B6923F0784323F4FE43A068E268D20642EA9C -S32508007560002213430B61324A136843F080631360FDF792FB06462E4B1B6813F0006F05D188 -S32508007580FDF78AFB831B022BF5D90325002DABD1274A1369A1690B431361A5E7244A1268CD -S325080075A012F0020F1ED02248C26822F073026168013943EA01131343C3600025ADE71C4AC5 -S325080075C0126812F4806FEED10125A6E7184A126812F4003FE7D1164A126812F4802FE2D1A1 -S325080075E001259AE7012598E7012F0FD01048026922F0C06222F4FE42A16863695B08013B61 -S325080076005B0643EA01231A430261ACE70848026922F4C00222F4FE42A16823695B08013B3A -S325080076205B0543EA01231A4302619CE701255BE7001002402DE9F04182B00446036813F459 -S32508007640006F25D0C36BB3F5000F06D0B3F5400F12D04BB1012637461CE0AE4AD36843F41E -S325080076608033D360002708E000210430FFF72CFF074610B106460DE00027A64AD2F88830B1 -S3250800768023F44003E16B0B43C2F88830002601E000263746236813F4003F6BD09D4B9B6DD0 -S325080076A013F0805F4CD19B4B9A6D42F080529A659B6D03F080530193019B4FF00108964AA7 -S325080076C0136843F480731360FDF7E6FA0546924B1B6813F4807F05D1FDF7DEFA401B0228D8 -S325080076E0F5D90327002F40D18A4BD3F8903013F4407315D0226D9A4212D0864AD2F890309E -S3250800770023F44073D2F8901041F48031C2F89010D2F8901021F48031C2F89010C2F89030E3 -S3250800772013F0010F0FD1002F40F0C980794AD2F8903023F44073216D0B43C2F8903015E03E -S325080077404FF00008BBE7FDF7A7FA0546714BD3F8903013F0020FE6D1FDF79EFA401B41F226 -S3250800776088339842F2D90327DDE73E46B8F1000F40F0A780236813F0010F08D0654AD2F82B -S32508007780883023F00303216A0B43C2F88830236813F0020F08D05F4AD2F8883023F00C03FB -S325080077A0616A0B43C2F88830236813F0200F08D0584AD2F8883023F44063A16A0B43C2F8AA -S325080077C08830236813F4007F08D0524AD2F8883023F44023616B0B43C2F88830236813F444 -S325080077E0806F08D04B4AD2F8883023F44013A16B0B43C2F88830236813F0400F08D0454A23 -S32508007800D2F8883023F44053E16A0B43C2F88830236813F4807F08D03E4AD2F8883023F499 -S325080078204033216B0B43C2F88830236813F4005F0FD0384AD2F8883023F04063216C0B4316 -S32508007840C2F88830236CB3F1006F40D0B3F1806F42D0236813F4802F0FD02E4AD2F8883037 -S3250800786023F04063616C0B43C2F88830636CB3F1006F39D0B3F1806F3BD0236813F4804FCD -S325080078800CD0244AD2F8883023F04053A16C0B43C2F88830A36CB3F1805F32D0236813F475 -S325080078A0004F08D01B4AD2F8883023F08043E16C0B43C2F88830304602B0BDE8F0813E4607 -S325080078C054E7144A936D23F08053936552E7D36843F48013D360BCE70121201DFFF7F4FDC9 -S325080078E00028B6D00646B4E7D36843F48013D360C3E70121201DFFF7E7FD0028BDD00646C9 -S32508007900BBE70221201DFFF7DFFD0028C6D00646C4E700BF00100240007000402DE9F047C2 -S3250800792082B00546884617461E46FDF7B5F90A9B1B1A03EB0609FDF7AFF982462A4B1B6858 -S32508007940C3F3CB3309FB03F301932B689C6838EA04040CBF01230023BB4240D0B6F1FF3F12 -S32508007960F3D0FDF799F9A0EB0A0048450AD2B9F1000F07D0019A02B14A46019B013B0193D8 -S325080079809146E2E72A68536823F0E00353606B68B3F5827F0BD0AB6AB3F5005F14D00123C8 -S325080079A085F85D30002385F85C30032018E0AB68B3F5004F02D0B3F5806FECD12A6813682B -S325080079C023F040031360E6E72A68136823F4005313602A68136843F400531360DFE7002029 -S325080079E002B0BDE8F08700BF9C0000202DE9F04782B006460C4615461F4600238DF8033078 -S32508007A00FDF74AF90A9B1B1A03EB0708FDF744F98146D6F800A0314B1B6803EB8303C3EBC3 -S32508007A20C3031B0D08FB03F3019302E0B7F1FF3F12D133689B6803EA040CAC454AD0B4F5C3 -S32508007A40C06FF3D1002DF1D19AF80C30DBB28DF803309DF80330E9E7FDF71EF9A0EB0900EC -S32508007A6040450AD2B8F1000F07D0019A02B14246019B013B01939046DBE73268536823F0C6 -S32508007A80E00353607368B3F5827F0BD0B36AB3F5005F14D0012386F85D30002386F85C307F -S32508007AA0032018E0B368B3F5004F02D0B3F5806FECD13268136823F040031360E6E7326820 -S32508007AC0136823F4005313603268136843F400531360DFE7002002B0BDE8F0879C000020BE -S32508007AE070B582B004460D46164600920B4600224FF4C051FFF77AFFB0B900962B460022CE -S32508007B0080212046FFF70AFFA8B900962B4600224FF4C0612046FFF769FF50B1236E43F0DA -S32508007B2020032366032004E0236E43F020032366032002B070BD236E43F02003236603207F -S32508007B40F7E770B582B004460D4616464368B3F5827F0DD000962B46002280212046FFF792 -S32508007B60DDFE90B96368B3F5827F14D002B070BD8368B3F5004F02D0B3F5806FEAD122680C -S32508007B80136823F040031360E4E7236E43F0200323660320EAE7A368B3F5004F02D0B3F5E8 -S32508007BA0806FE3D100962B4600224FF4C0612046FFF71CFF0028D9D0236E43F020032366CF -S32508007BC00320D3E700286AD010B50446436A33B94368B3F5827F05D00023C36102E000233B -S32508007BE0036143610023A36294F85D30002B4DD0022384F85D302268136823F040031360EA -S32508007C00E368B3F5E06F47D90022B3F5706F04D0B3F5E06F01D00023A362636803F48273D0 -S32508007C20A16801F404410B43216901F002010B43616901F001010B43A16901F400710B4310 -S32508007C40E16901F038010B43216A01F080010B43A16A01F4005120680B430360638B03F09E -S32508007C600403616A01F010010B43616B01F008010B43E16801F470610B4321681A434A60D3 -S32508007C8000202066012384F85D3010BD84F85C302046FCF7C7FEABE74FF48052B5E70120AC -S32508007CA07047000038B5044690F85C00012800F0F780012084F85C0094F85D00C0B2656833 -S32508007CC001280AD0B5F5827F40F0DB80A568002D40F0DC80042840F0DB80002900F0DA806D -S32508007CE0002A00F0D980002B00F0D88094F85D00C0B2042802D0052084F85D000020206693 -S32508007D00A163A387E3872264A4F84430A4F84630E06420652268536823F4C0435360E368EF -S32508007D20B3F5E06F28D92268536823F48053536094F85D30DBB2042B69D0A36D594A1A631D -S32508007D40A36D594ADA62A36D584A5A63A36D00229A632168B4F846309BB2226C0C31A06DB8 -S32508007D60FEF720FC002859D0236E43F010032366012084F85D0085E02268536843F4805385 -S32508007D805360636D9B69B3F5806F1AD0A36D9B69B3F5806FCCD12268536823F480535360A3 -S32508007DA0B4F8463013F0010F24D12268536823F400535360B4F84630C3F34E03A4F84630EE -S32508007DC0B6E7A38F13F0010F09D12268536823F480435360E38FC3F34E03E387D6E72268DD -S32508007DE0536843F480435360E38FC3F34E030133E387CBE72268536843F400535360B4F816 -S32508007E004630C3F34E030133A4F8463090E7A36D274A1A63A36D274ADA6294E7226853689F -S32508007E2043F001035360626D00231363626DD362626D5363626D93632268E38F9BB20C320D -S32508007E40A16B606DFEF7AEFB98B923681A6812F0400F03D11A6842F040021A602268536865 -S32508007E6043F0200353602268536843F00203536008E0236E43F010032366012084F85D0079 -S32508007E8000E00220002384F85C3038BD0220F9E70220F7E70120F5E70120F3E70120F1E7BF -S32508007EA00220F2E7C77E0008637F0008D17E0008BB7E0008F37E0008704708B5806AFFF71D -S32508007EC0FBFF08BD704708B5806AFFF7FBFF08BD08B5806A0268536823F003035360036EB9 -S32508007EE043F010030366012380F85D30FCF750F908BD38B50546846AFCF7CEFE2B681B68A0 -S32508007F0013F0200F1FD1024621684B6823F020034B60A3681BB96368B3F5827F17D0216809 -S32508007F204B6823F001034B6064212046FFF709FE08B1202323660023A4F84630012384F87C -S32508007F405D30236E4BB92046FCF710F938BD21684B6823F003034B60E6E72046FCF718F963 -S32508007F60F4E738B50546846AFCF796FE2B681B6813F0200F1CD1024621684B6823F020037C -S32508007F804B6064212046FFF7ABFD18B1236E43F0200323662268536823F003035360002332 -S32508007FA0E387A4F84630012384F85D30236E1BB92046FCF7C9F838BD2046FCF7E9F8FAE77B -S32508007FC010B584B0044602685168936803F04100012867D013F0020F02D011F0800F68D1EF -S32508007FE013F4B07F68D011F0200F65D013F0400F0FD094F85D00C0B203285FD0206E40F0FC -S325080080000400206600200090D068009090680090009813F0200F0CD0206E40F001002066DD -S325080080200020029090680290106820F040001060029A13F4807F09D0236E43F008032366EB -S325080080400023039323689B680393039B236E002B32D02268536823F0E0035360012384F84B -S325080080605D3011F0030F31D02268536823F003035360A36D4BB1174A9A63A06DFEF7CDFA0D -S3250800808018B1236E43F040032366636DA3B1114A9A63606DFEF7C1FA70B1236E43F0400358 -S325080080A0236609E011F0400F94D0E36C2046984702E0236D2046984704B010BD0023019309 -S325080080C0D368019393680193019BF5E72046FCF75FF8F1E7D980000808B5806A0023A0F871 -S325080080E04630C387FCF754F808BD08B502F047FE10B102684068904708BD0000EFF30583E1 -S325080081002BB9064B186828B901221A6070476FF0050070474FF0FF30704700BFF007002051 -S32508008120EFF3058373B90A4B1B68012B0DD110B50024084BDC77064B02221A6001F0F4FE58 -S32508008140204610BD6FF0050070474FF0FF307047F007002000ED00E008B5EFF3058343B997 -S3250800816002F06AFA40B1022808D101F033FF002006E06FF0050003E0012001E04FF0FF30C7 -S3250800818008BDF0B587B000240594EFF305847CBB70B32AB31568936903B918235C1E372C84 -S325080081A04AD8546814F0010F48D1566976B14FEA960C946834B1D768B7F5C07F02D3176985 -S325080081C007B1C6B92CB14FF0FF340EE04FF0800CEFE7D4688CB9146994B14FF0FF3404E0E3 -S325080081E01546002418234FF0800C012C0AD0ACB1059807B0F0BD0124F7E74FF0FF34F4E737 -S325080082000024F2E7146992680292019400930B466246294601F016FE0590E9E705AA01920C -S3250800822000930B461FFA8CF2294601F048FE0128DED000230593DBE70020DAE70020D8E7FB -S3250800824008B5EFF3058323B930B102F04FF8002008BD6FF00500FBE76FF00300F8E708B5CA -S32508008260EFF3058333B908B9002008BD01F0C8FF0020FAE76FF00500F7E700002DE9F043B0 -S3250800828083B0EFF30587002F43D10646894615461C4600283FD0082000F04CFE804600288D -S325080082A03BD006604560B9F1000F00D0012704B32068A36813B1E2682B2A10D853B14FF011 -S325080082C0FF33DBB10024404600F0B2FE204603B0BDE8F083E3687BB14FF0FF33F1E7019303 -S325080082E00F4B009343463A46012102F093FB04460CE020460023E4E70023E2E7084B00937C -S3250800830043463A46012102F069FB0446002CDDD1D9E70024DAE70024D8E70446D6E700BF5C -S32508008320EB800008EFF305836BB90A4670B100B583B00093042102F097FB012809D1002076 -S3250800834003B05DF804FB6FF0050070476FF0030070476FF00200F3E708B5EFF30583CBB9EE -S32508008360A0B1836813B1C2681F2A0BD82BB14FF0FF338BB900F04EFA08BDC36843B14FF0AD -S32508008380FF33F6E7184600F020FAF5E70023F0E70023EEE70020EFE70020EDE7F8B110B532 -S325080083A082B00C4611F07F4F1CD1EFF305829AB10022019201AA00F049FBB8B1019BC3B1AE -S325080083C04FF0E0234FF08052C3F8042DBFF34F8FBFF36F8F204607E000F0EEFA04E06FF0A8 -S325080083E0030070476FF0030002B010BD6FF00200FAE72046F8E770B5B0B10C46064611F028 -S325080084007F4F14D1EFF3058353B100F0C7FA05462146304600F0B8FA58B96FF0020508E053 -S3250800842000F08AFA054604E06FF0030501E06FF00305284670BD40B370B582B00C461D4642 -S32508008440844611F07F4F23D1EFF3058323BB12F0010610D0012312F0020F0ED00022009584 -S325080084602146604600F0E4F94EB1844312D0B5B16FF001000EE00023EDE70122EFE7044282 -S3250800848008D17DB16FF0010004E06FF0030070476FF0030002B070BD6FF00500FAE76FF085 -S325080084A00200F7E76FF00200F4E770B5EFF30583002B3FD1044600B1436813F0010600D048 -S325080084C0012613F0080F38D14CB3A16811B1E3684F2B19D899B14FF0FF334BBB1EB304200E -S325080084E001F01DF805462DB104B124682146284601F0B0FAFDB1F6B145F001051BE0E368B8 -S325080085007BB14FF0FF33E8E726B1042001F012F80546E8E7012001F00DF80546E3E7002382 -S32508008520DBE70023D9E7012000F0F9FF0546DAE70025DFE70025284670BD0025FBE7EFF3DF -S325080085400582C2B910B503460C4620F0010003F0010398B13BB101F005FA012811D094B12F -S325080085606FF001000EE001F02AF901280ED07CB16FF0010006E06FF0050070476FF0030094 -S3250800858000E0002010BD6FF00200FBE70020F9E76FF00200F6E7EFF30582B2B908B50346A5 -S325080085A020F0010003F0010390B12BB100F0D1FF012810D1002008BD00231A46194600F007 -S325080085C0DEFE01280AD10020F5E76FF0050070476FF00300EFE76FF00200ECE76FF00200C9 -S325080085E0E9E770B582B0EFF30583002B3AD1144600283BD000293BD06AB393684BB1D26897 -S325080086004F2A06D9226922B101FB00F56669AE421BD273B14FF0FF3363BB002200F08BFEAB -S32508008620054605B304B124682146284601F012FA19E0E3688BB9236913B14FF0FF33EBE7FB -S3250800864063696BB14FF0FF33E6E70025009500F028FE0546E5E70023DEE74FF0FF33DBE7E4 -S325080086600023D9E70025284602B070BD0025FAE70025F8E70025F6E710B582B01C46EFF350 -S325080086800583C3B118B329B33CBB0023019301AA00F07FFF012823D1019850B14FF0E02369 -S325080086A04FF08052C3F8042DBFF34F8FBFF36F8F002002B010BDB0B1C1B10023224600F082 -S325080086C05EFE012815D0B4B16FF00100F1E76FF00300EEE76FF00300EBE76FF00300E8E7E9 -S325080086E06FF00200E5E76FF00300E2E76FF00300DFE70020DDE76FF00200DAE710B582B0EF -S325080087001C46EFF30583C3B110B321B334BB0023019301AA01F046F9012822D1019850B13D -S325080087204FF0E0234FF08052C3F8042DBFF34F8FBFF36F8F002002B010BDA8B1B9B12246E2 -S3250800874000F08EFF012815D0B4B16FF00100F2E76FF00300EFE76FF00300ECE76FF0030013 -S32508008760E9E76FF00200E6E76FF00300E3E76FF00300E0E70020DEE76FF00200DBE7000090 -S32508008780034B0360034B0B6080231360704700BF700600206C040020034B0360034B0B6045 -S325080087A04FF4807313607047F80B0020F40700201AB9084205D110467047814303D0002056 -S325080087C07047012070470120704780B110B582B0044620230193019B202B11D04FF0500381 -S325080087E083F31188BFF36F8FBFF34F8FFEE74FF0500383F31188BFF36F8FBFF34F8FFEE771 -S32508008800002340F8043B00F02BF901232377204602B010BD38B5202000F08CFB044628B132 -S32508008820002540F8045B00F01BF92577204638BD2DE9F84378B10C4616461D46074611F09A -S325080088407F4811D04FF0500383F31188BFF36F8FBFF34F8FFEE74FF0500383F31188BFF349 -S325080088606F8FBFF34F8FFEE741B94FF0500383F31188BFF36F8FBFF34F8FFEE701F0DCFEEC -S3250800888050B9089B43B14FF0500383F31188BFF36F8FBFF34F8FFEE701F09CFBD7F800907D -S325080088A02A4621464846FFF783FFF0B116B129EA04033B6001F028FCB8F1000F12D048B900 -S325080088C04FF0E0234FF08052C3F8042DBFF34F8FBFF36F8F01F0A4FF814610F0007F1AD047 -S325080088E029F07F494846BDE8F883089B83B166B941460DB141F08061089A2143381D01F042 -S325080089006FFDC146DDF82080D4E74FF08071F0E7DDF82080CEE700F055F9D7F800902A4668 -S3250800892021464846FFF744FF18B116B129EA04043C6000F069F9D3E770B170B50C460546C5 -S3250800894011F07F4F11D04FF0500383F31188BFF36F8FBFF34F8FFEE74FF0500383F31188F2 -S32508008960BFF36F8FBFF34F8FFEE700F02BF92E6826EA04042C6000F047F9304670BD08B5E6 -S32508008980FFF7DAFF08BD000008B50A4600230146014802F007FA08BD7F890008EFF3118337 -S325080089A04FF0500282F31188BFF36F8FBFF34F8F006883F311887047F8B568B10D46044639 -S325080089C011F07F4711D04FF0500383F31188BFF36F8FBFF34F8FFEE74FF0500383F311887A -S325080089E0BFF36F8FBFF34F8FFEE700F10C0601F0F1FA206923682B4323600AE0216832EAD1 -S32508008A00010105D111E0216841F0007101F076FD2846B0420ED04568036823F07F4213F0C3 -S32508008A20806FEBD121681142F2D013F0807FEAD01743E8E7236823EA0703236001F064FB85 -S32508008A402068F8BD08B5FFF7B7FF08BD08B513460A460146014802F0A5F908BD458A00087B -S32508008A6000F1080343604FF0FF328260C360036100230360704700230361704743684B609F -S32508008A809A688A60516099600861036801330360704730B40D68B5F1FF3F11D000F10803F6 -S32508008AA01C465B681A68AA42FAD963684B6099608C606160086103680133036030BC704718 -S32508008AC00469F2E70369416882688A60416851605A68824206D0002202611A68013A1A60E7 -S32508008AE01868704782685A60F5E7000082B0002301930D4B1B68B3F1FF3F08D04FF05003A1 -S32508008B0083F31188BFF36F8FBFF34F8FFEE74FF0500383F31188BFF36F8FBFF34F8F019B96 -S32508008B20002BFCD002B07047A800002008480068006880F308884FF0000080F3148862B676 -S32508008B4061B6BFF34F8FBFF36F8F00DF00BF000008ED00E0DFF80C00016841F470010160EA -S32508008B607047000088ED00E04FF0807340F8043C21F0010140F8081C054B40F80C3C40F8BA -S32508008B80202C6FF0020340F8243C4438704700BFED8A00080000000000000000000000000E -S32508008BA0074B19680868B0E8F04F80F30988BFF36F8F4FF0000080F311887047AFF30080B5 -S32508008BC0E08D00204FF0500383F31188BFF36F8FBFF34F8F0B4A136801331360012B00D0A6 -S32508008BE070474FF0E023D3F8043D13F0FF0FF7D04FF0500383F31188BFF36F8FBFF34F8FA9 -S32508008C00FEE700BFA8000020094B1B6843B94FF0500383F31188BFF36F8FBFF34F8FFEE741 -S32508008C20013B034A13600BB983F31188704700BFA800002000000000000000000000000019 -S32508008C40EFF30980BFF36F8F154B1A681EF0100F08BF20ED108A20E9F04F10602DE9090097 -S32508008C604FF0500080F31188BFF34F8FBFF36F8F01F0ECFA4FF0000080F3118809BC1968A3 -S32508008C800868B0E8F04F1EF0100F08BFB0EC108A80F30988BFF36F8F704700BFAFF3008009 -S32508008CA0E08D002008B54FF0500383F31188BFF36F8FBFF34F8F01F09BF928B14FF0E023DB -S32508008CC04FF08052C3F8042D002383F3118808BD4FF0E022002313619361054B1B680549A5 -S32508008CE0A1FB03139B09013B53610723136170479C000020D34D62104FF0E023D3F8002D43 -S32508008D003D4B9A421CD04FF0E023D3F8002D3B4B9A421ED030B583B0394B1A78D2B2019226 -S32508008D20FF221A701B78DBB28DF803309DF8033003F05003334A1370334B07221A601BE078 -S32508008D404FF0500383F31188BFF36F8FBFF34F8FFEE74FF0500383F31188BFF36F8FBFF33C -S32508008D604F8FFEE7284A1368013B13609DF803305B00DBB28DF803309DF8033013F0800FC4 -S32508008D80F0D1214B1B68032B08D04FF0500383F31188BFF36F8FBFF34F8FFEE71B021A4AC8 -S32508008DA0136003F4E0631360019BDBB2144A13704FF0E024D4F8203D43F47003C4F8203D4C -S32508008DC0D4F8203D43F07043C4F8203DFFF780FF00250E4B1D60FFF7BDFED4F8343F43F0CA -S32508008DE04043C4F8343FFFF7A1FE01F02FFAFFF77DFE284603B030BD71C20F4170C20F4180 -S32508008E0000E400E0780D00207C0D0020A8000020EFF305830F2B0FD9114A9B5CDBB2114AA4 -S32508008E2012789A4208D94FF0500383F31188BFF36F8FBFF34F8FFEE74FF0E023D3F80C3DC1 -S32508008E4003F4E063084A1268934208D94FF0500383F31188BFF36F8FBFF34F8FFEE77047CB -S32508008E60F0E300E0780D00207C0D0020124A12F0070F1ED0D11D21F00701C1F5004313442A -S32508008E800A460E480260002141601344083B23F007030B48036059601960991A5160136084 -S32508008EA0084B1960084B1960084B4FF000421A6070474FF40043E4E7840D0020988D0020C0 -S32508008EC0800D00208C8D0020888D0020848D0020164B1A461B688342FBD3516802EB010CAE -S32508008EE0844509D0416800EB010C634509D00360904219D010607047406801445160104667 -S32508008F00F0E710B40A4C2468A3420BD05B681944416013681B680360904200D010605DF87D -S32508008F20044B70470460F7E7704700BF988D0020800D002070B5054601F04CF8364B1B68CA -S32508008F40A3B1364B1B681D424ED135B1083515F0070F02D025F007050835002D46D0304B01 -S32508008F601B68AB4251D32F4A146804E0FFF77EFFE7E722461C466368AB4202D22368002B29 -S32508008F80F7D1254B1B68A34241D0166808362368136063685B1B102B10D9601910F0070F64 -S32508008FA008D04FF0500383F31188BFF36F8FBFF34F8FFEE743606560FFF78AFF62681849F3 -S32508008FC00B689B1A0B60184909688B4201D216490B60124B1B681343636000232360134AB8 -S32508008FE013680133136002E0002600E0002601F08BF816F0070F0CD04FF0500383F3118826 -S32508009000BFF36F8FBFF34F8FFEE70026EFE70026EDE7304670BD00BF800D0020848D0020E7 -S32508009020888D0020988D00208C8D0020908D0020002834D038B50446A0F1080550F8043CA9 -S32508009040174A1268134208D14FF0500383F31188BFF36F8FBFF34F8FFEE750F8081C41B1D5 -S325080090604FF0500383F31188BFF36F8FBFF34F8FFEE723EA020340F8043C00F0ABFF54F8AC -S32508009080041C084A13680B4413602846FFF720FF054A13680133136001F036F838BD704754 -S325080090A0848D0020888D0020948D00200346406A18B11B6B1868C0F13800704710B504468A -S325080090C0FFF780FDA26BE36B9A4204D00024FFF79BFD204610BD0124F9E710B50446FFF715 -S325080090E071FDA36B23B90124FFF78EFD204610BD0024F9E770B504461546866B026C5AB9F1 -S3250800910003681BB100200136A66370BD806801F0EFFA0023A360F6E76DB9406801F004FFF6 -S32508009120226C636813446360A268934219D3236863602846E7E7C06801F0F6FE226C51422B -S32508009140E3689B1AE3602268934202D2A3680B44E360022D01D00020D5E726B1013E0020DC -S32508009160D1E72846CFE70020CDE70346026C6AB110B50846D9681144D9609C68A14201D3C2 -S325080091801968D960D96801F0CFFE10BD704738B50546FFF717FD95F8454064B201E0013CFC -S325080091A064B2002C0ADD6B6A43B105F1240001F05FF90028F3D001F033FAF0E7FF2385F8CD -S325080091C04530FFF721FDFFF7FDFC95F8444064B201E0013C64B2002C0ADD2B6943B105F11D -S325080091E0100001F045F90028F3D001F019FAF0E7FF2385F84430FFF707FD38BD38B5E0B1DC -S325080092000D460446FFF7DEFC2368E26B216C01FB0230A0600020A0636360013A02FB0133EE -S32508009220E360FF2384F8443084F84530FDB9236963B9FFF7E9FC012038BD4FF0500383F383 -S325080092401188BFF36F8FBFF34F8FFEE704F1100001F00EF90028ECD04FF0E0234FF080520E -S32508009260C3F8042DBFF34F8FBFF36F8FE1E704F11000FFF7F5FB04F12400FFF7F1FBD8E747 -S3250800928038B51D46049C0B4649B92460E063236401212046FFF7B2FF84F84C5038BD226071 -S325080092A0F4E740B94FF0500383F31188BFF36F8FBFF34F8FFEE710B584B01C46844653B1DD -S325080092C092B189B94FF0500383F31188BFF36F8FBFF34F8FFEE74FF0500383F31188BFF3E2 -S325080092E06F8FBFF34F8FFEE76AB150230393039B502B13D04FF0500383F31188BFF36F8F7C -S32508009300BFF34F8FFEE70029EFD04FF0500383F31188BFF36F8FBFF34F8FFEE7039B01235A -S3250800932084F8463000949DF818306046FFF7A8FF204604B010BD40B94FF0500383F31188F8 -S32508009340BFF36F8FBFF34F8FFEE7F0B583B00D461446064601FB00F05030FFF7EBFD074672 -S3250800936050B1002380F846300090234600F1500229463046FFF784FF384603B0F0BDF0B5B0 -S3250800938085B0019288B10F461D460446B1B1022D20D1E36B012B1DD04FF0500383F3118832 -S325080093A0BFF36F8FBFF34F8FFEE74FF0500383F31188BFF36F8FBFF34F8FFEE7036C002B1A -S325080093C0E5D04FF0500383F31188BFF36F8FBFF34F8FFEE701F030F9064658B9019B002BC6 -S325080093E048D04FF0500383F31188BFF36F8FBFF34F8FFEE700263DE02A4639462046FFF7F3 -S3250800940079FE636A7BB948B14FF0E0234FF08052C3F8042DBFF34F8FBFF36F8FFFF7F4FB69 -S32508009420012005B0F0BD04F1240001F021F80028F4D04FF0E0234FF08052C3F8042DBFF39B -S325080094404F8FBFF36F8FE9E7FFF7DEFB0020E8E702A801F097F8012619E0002384F8443085 -S3250800946021E0002384F8453023E02046FFF78FFE00F04AFEFFF7A6FBA26BE36B9A42BBD349 -S32508009480022DB9D0019B002BDED0002EE0D0FFF7BBFB00F09FFDFFF795FB94F8442052B201 -S325080094A0B2F1FF3FD9D094F8452052B2B2F1FF3FD7D0FFF7A9FB01A902A801F06FF8D8B9C0 -S325080094C02046FFF7FBFD0028CFD0019904F1100000F06EFF2046FFF75AFE00F015FE002888 -S325080094E0C8D14FF0E0234FF08052C3F8042DBFF34F8FBFF36F8FBDE72046FFF748FE00F010 -S3250800950003FE00208DE748B108B5002181600160C1600B460A46FFF732FF08BD704710B565 -S32508009520024600210120FFF706FF0446FFF7EBFF204610BD10B582B00B46009000221146EA -S325080095400120FFF7AEFE0446FFF7DDFF204602B010BD38B538B10446856801F067F8854215 -S325080095600AD0002038BD4FF0500383F31188BFF36F8FBFF34F8FFEE7E368013BE3600BB1A2 -S325080095800120EFE71A4619462046FFF7F8FE0120E8E72DE9F84390B10F4616461C460546D5 -S325080095A0B1B1022C20D1EB6B012B1DD04FF0500383F31188BFF36F8FBFF34F8FFEE74FF0A8 -S325080095C0500383F31188BFF36F8FBFF34F8FFEE7036C002BE5D04FF0500383F31188BFF354 -S325080095E06F8FBFF34F8FFEE7FFF712FCEFF311884FF0500383F31188BFF36F8FBFF34F8F8A -S32508009600AA6BEB6B9A4206D3022C04D0002088F31188BDE8F88395F845904FFA89F9AB6B83 -S32508009620224639462846FFF765FDB9F1FF3F06D009F101035BB285F845300120E7E76B6AF0 -S325080096400BB90120E3E705F1240000F011FF18B126B101203060DAE70120D8E70120D6E763 -S32508009660F0B585B0019290B10F460446C1B100F0E3FF064600BB019B002B5ED04FF05003BD -S3250800968083F31188BFF36F8FBFF34F8FFEE74FF0500383F31188BFF36F8FBFF34F8FFEE7C2 -S325080096A0036C002BE3D04FF0500383F31188BFF36F8FBFF34F8FFEE700263EE03946204660 -S325080096C0FFF753FD013DA563236923B9FFF79CFA012005B0F0BD04F1100000F0C9FE002895 -S325080096E0F4D04FF0E0234FF08052C3F8042DBFF34F8FBFF36F8FE9E7FFF786FA0020E8E7E4 -S3250800970002A800F03FFF012621E0002384F8443029E0002384F845302BE02046FFF737FD70 -S3250800972000F0F2FC09E02046FFF731FD00F0ECFC2046FFF7D2FC00283FD1FFF743FAA56B4D -S32508009740002DBBD1019B002BD6D0002ED8D0FFF75BFA00F03FFCFFF735FA94F844305BB257 -S32508009760B3F1FF3FD1D094F845305BB2B3F1FF3FCFD0FFF749FA01A902A800F00FFF002816 -S32508009780D1D12046FFF7A9FC0028C6D0019904F1240000F00DFE2046FFF7F9FC00F0B4FCBB -S325080097A00028CAD14FF0E0234FF08052C3F8042DBFF34F8FBFF36F8FBFE7002089E770B5FE -S325080097C084B0019158B10446036C8BB14FF0500383F31188BFF36F8FBFF34F8FFEE74FF0B2 -S325080097E0500383F31188BFF36F8FBFF34F8FFEE700F022FF054650B9019B5BB14FF0500335 -S3250800980083F31188BFF36F8FBFF34F8FFEE70026354655E0064653E0013BA36323683BB1F8 -S3250800982023694BB9FFF7F0F90126304604B070BD01F002F8A060F3E704F1100000F018FE5D -S325080098400028EFD04FF0E0234FF08052C3F8042DBFF34F8FBFF36F8FE4E746B14FF0500340 -S3250800986083F31188BFF36F8FBFF34F8FFEE7FFF7CBF9DAE702A800F085FE01252AE00023BB -S3250800988084F8443032E0002384F8453034E0FFF799F9A06800F0E0FE0646FFF7B5F93BE027 -S325080098A02046FFF774FC00F02FFC09E02046FFF76EFC00F029FC2046FFF70FFC002842D14D -S325080098C0FFF780F9A36B002BA6D1019B002BC4D0002DCFD0FFF798F900F07CFBFFF772F9E5 -S325080098E094F844305BB2B3F1FF3FC8D094F845305BB2B3F1FF3FC6D0FFF786F901A902A884 -S3250800990000F04CFE0028D1D12046FFF7E6FB0028C6D02368002BBAD0019904F1240000F057 -S3250800992047FD2046FFF733FC00F0EEFB0028C7D14FF0E0234FF08052C3F8042DBFF34F8FE2 -S32508009940BFF36F8FBCE70EB900266EE7FFF73AF92046FFF7ABFB0146A06800F011FFFFF7F4 -S3250800996053F9F1E780B170B50C460546866800F05DFE864211D021462846FFF720FF80B1C5 -S32508009980EB680133EB600CE04FF0500383F31188BFF36F8FBFF34F8FFEE7EB680133EB6063 -S325080099A0012070BD2DE9F843B0B10D4690460446D9B1FFF72DFAEFF311874FF0500383F3FD -S325080099C01188BFF36F8FBFF34F8FA66BCEB9002087F31188BDE8F8834FF0500383F3118814 -S325080099E0BFF36F8FBFF34F8FFEE7036C002BE0D04FF0500383F31188BFF36F8FBFF34F8F09 -S32508009A00FEE794F844904FFA89F929462046FFF7ACFB731EA363B9F1FF3F06D009F1010363 -S32508009A205BB284F844300120D2E723690BB90120CEE704F1100000F01BFD30B1B8F1000F75 -S32508009A4005D00120C8F80000C2E70120C0E70120BEE700000023072B0CD8074A52F83320E4 -S32508009A600AB10133F7E7044A42F8331002EBC30250607047704700BFA08D002070B50446F5 -S32508009A800D461646FFF79EF894F844305BB2B3F1FF3F0DD094F845305BB2B3F1FF3F0BD0E6 -S32508009AA0FFF7B2F8A36B5BB12046FFF770FB70BD002384F84430EDE7002384F84530EFE719 -S32508009AC03246294604F1240000F0B6FCECE70000084B1B681B6823B9074B4FF0FF321A6092 -S32508009AE07047044B1B68DB68DB685A68024B1A60704700BFE48D00208C9200202DE9F0472E -S32508009B0080460D4617469946089EDDF824A00A9C9200A521206B01F082F9236B07F1804266 -S32508009B20013A03EB820727F00707002D61D04FF0000CBCF10F0F09D815F80C3004EB0C02A5 -S32508009B4082F8343013B10CF1010CF2E7002384F84330372E00D93726E662E6640025256584 -S32508009B60201DFEF788FF04F11800FEF784FF2461C6F13806A6616462C4F8785184F87C5184 -S32508009B804FF49072294604F1580001F048F91B4BE36503F168022266D033636601220023DE -S32508009BA0C4E93C2343F20E33A4F8F8304AF6CD33A4F8FA3041F23423A4F8FC304EF26D63E9 -S32508009BC0A4F8FE304DF6EC63A4F800310523A4F802310B23A4F804314A4641463846FEF7CE -S32508009BE0C3FF2060BAF1000F01D0CAF80040BDE8F087002384F83430ABE700BF0C94002058 -S32508009C0038B5002407E004EB840293000E481844FEF726FF0134372CF5D90C4D2846FEF748 -S32508009C201FFF0B4C2046FEF71BFF0A48FEF718FF0948FEF715FF0948FEF712FF084B1D604D -S32508009C40084B1C6038BD00BFEC8D0020609200207492002098920020C4920020B092002080 -S32508009C60E48D0020E88D002010B50446FEF7AAFF224A136801331360214B1B685BB1214B0E -S32508009C801B686BB91E4B1B68DA6AE36A9A4207D81B4B1C6004E01A4B1C601368012B29D090 -S32508009CA0194A1368013313606364E06A174B1B68984201D9154B186000EB8000211D144B87 -S32508009CC003EB8000FEF7DAFEFEF79EFF0D4B1B687BB10B4B1B68DA6AE36A9A4209D24FF042 -S32508009CE0E0234FF08052C3F8042DBFF34F8FBFF36F8F10BDFFF784FFD2E700BF4C9200205A -S32508009D00E08D0020AC920020589200205C920020EC8D002010B50446583001F089F894F804 -S32508009D207D3163B1012B11D0022B0ED04FF0500383F31188BFF36F8FBFF34F8FFEE7206BEA -S32508009D40FFF776F92046FFF773F910BD2046FFF76FF9FAE70F4B1B68D3B110B5FEF732FF0A -S32508009D600D4BDB68DC68201DFEF7ACFE0B4A1368013B1360074A1368013B1360FEF744FFE8 -S32508009D802046FFF7C7FF034B1B68002BE6D110BD704700BF50920020C49200204C92002027 -S32508009DA008B5FFF7D7FF074B1B68012BF9D94FF0E0234FF08052C3F8042DBFF34F8FBFF3B8 -S32508009DC06F8FEEE7EC8D002070B504460D46174B1E68174B18680430FEF774FEB4F1FF3FFF -S32508009DE00DD03444124B1B685C60A64210D9114B18680F4B19680431FEF74BFE70BD002D0F -S32508009E00EFD00B4B196804310B48FEF737FEF5E70A4B1868064B19680431FEF73AFE084BB4 -S32508009E201B68A342EAD9064B1C60E7E7D8920020E08D0020E88D0020B0920020E48D0020AF -S32508009E408C92002030B587B00B9C8CB10C9DC5B14FF4C0750495049DB5F5C07F1AD04FF0D3 -S32508009E60500383F31188BFF36F8FBFF34F8FFEE74FF0500383F31188BFF36F8FBFF34F8F6C -S32508009E80FEE74FF0500383F31188BFF36F8FBFF34F8FFEE7049D0C9D2C63022485F87D41CF -S32508009EA000240394029505AC01940A9C0094FFF725FE0C98FFF7D8FE059807B030BD2DE9E2 -S32508009EC0F04385B00746884614461E469000FFF731F808B381464FF4C070FFF72BF805462B -S32508009EE0B0B1C0F83090E5B1002385F87D31039302950D9B01930C9B00933346224641468C -S32508009F003846FFF7FBFD2846FFF7AEFE012005E04846FFF78DF8E6E74FF0FF3005B0BDE813 -S32508009F20F0834FF0FF30F9E710B588B000240594069407AA06A905A8FEF722FC059B0293A9 -S32508009F40069B019300942346079A1A491A48FFF779FF1A4B186040B100F00EFD012806D025 -S32508009F60B0F1FF3F1DD008B010BD0020F6E74FF0500383F31188BFF36F8FBFF34F8F104B49 -S32508009F801B6858330F4A13600F4B4FF0FF321A600E4B01221A600E4B00221A60FEF7ACFE0B -S32508009FA0E1E74FF0500383F31188BFF36F8FBFF34F8FFEE798B50008A19D00088892002030 -S32508009FC0E08D0020F80000208C920020AC920020D8920020024A136801331360704700BFC4 -S32508009FE054920020014B1868704700BFD8920020F8B53A4B1B68002B69D1394B1D68013528 -S3250800A0001D60C5B9374B1B681B6843B14FF0500383F31188BFF36F8FBFF34F8FFEE7314A7A -S3250800A0201168314B186810601960304A136801331360FFF74DFD2E4B1B68AB423DD90027B2 -S3250800A0402C4B1B68DB6A03EB83039A002A4B9B58012B00D90127294B1B68002B3CD00127BA -S3250800A0603AE001271F4B1B681B6843B31D4B1B68DB68DC6863689D4226D3261D3046FEF767 -S3250800A08021FDA36A1BB104F11800FEF71BFDE36A1B4A1268934201D9194A136003EB83037C -S3250800A0A09A00314614481044FEF7E8FCE26A114B1B68DB6A9A42D4D2D4E70027D2E70C4B14 -S3250800A0C04FF0FF321A60BBE7094A1360B8E70D4A13680133136000273846F8BD54920020A8 -S3250800A0E0D8920020E48D0020E88D0020909200208C920020E08D0020EC8D0020DC9200206E -S3250800A1005C9200209492002038B5354B1B6843B94FF0500383F31188BFF36F8FBFF34F8F10 -S3250800A120FEE7FEF74FFD2E4B1A68013A1A601B68002B4FD12B4B1B680BB900244BE000243D -S3250800A140294B1B681BB3284BDB68DC6804F11800FEF7B8FC251D2846FEF7B4FCE06A234B6F -S3250800A1601B68984201D9214B186000EB800029461F4B03EB8000FEF781FCE26A1D4B1B685B -S3250800A180DB6A9A42DCD31C4B01221A60D8E70CB1FFF79EFC194B1C6884B9174B1C68D4B141 -S3250800A1A04FF0E0234FF08052C3F8042DBFF34F8FBFF36F8F01240EE0013C07D0FFF718FFDE -S3250800A1C00028F9D00C4B01221A60F5E70B4B00221A60E2E70024FEF717FD204638BD00BFAE -S3250800A1E0549200204C920020989200205C920020EC8D0020E08D0020DC92002094920020FB -S3250800A20010B5A8B10446104B1B6843B14FF0500383F31188BFF36F8FBFF34F8FFEE7FFF73A -S3250800A220D9FE00212046FFF7CFFDFFF76DFF48B94FF0E0234FF08052C3F8042DBFF34F8FBE -S3250800A240BFF36F8F10BD00BF54920020214B1B681BB1214B01221A6070471F4B00221A602D -S3250800A2601E4B1B6803EB83018A001D498A585AB90BB1013BF6E74FF0500383F31188BFF365 -S3250800A2806F8FBFF34F8FFEE703EB830082000A4450684068506003EB830C4FEA8C0208326E -S3250800A2A0114488420FD003EB830291000C4A0A445268D1680B4A116008490B60136858336F -S3250800A2C0094A13607047406862469100044A0A445060E8E754920020DC9200205C92002055 -S3250800A2E0EC8D0020E08D0020F800002038B50446FEF768FCE4B1251D2846FEF7E3FBA36A5D -S3250800A3001BB104F11800FEF7DDFB29462348FEF7B5FB94F87C31DBB2012B0CD0FEF774FCD7 -S3250800A3201F4B1B685BB91F4B1B68A3420ED038BD1C4B1C68DFE7002384F87C31EEE7FEF7A2 -S3250800A34041FCFFF7C5FBFEF75FFCECE7144B1B68B3B1154B1B6843B14FF0500383F311881B -S3250800A360BFF36F8FBFF34F8FFEE74FF0E0234FF08052C3F8042DBFF34F8FBFF36F8FD6E76E -S3250800A380064B1A68094B1B689A4203D1054B00221A60CCE7FFF75AFFC9E700BFB092002096 -S3250800A3A0AC920020E08D0020549200204C92002058B110B50C46094A11681831FEF769FB12 -S3250800A3C001212046FFF700FD10BD4FF0500383F31188BFF36F8FBFF34F8FFEE7E08D0020D4 -S3250800A3E070B110B514460246114B1B688BB94FF0500383F31188BFF36F8FBFF34F8FFEE7DE -S3250800A4004FF0500383F31188BFF36F8FBFF34F8FFEE7084B186841F0004181611968183177 -S3250800A4201046FEF72BFB01212046FFF7CDFC10BD54920020E08D002038B570B10D4614463B -S3250800A4400A4A11681831FEF719FB0CB14FF0FF3521462846FFF7B8FC38BD4FF0500383F323 -S3250800A4601188BFF36F8FBFF34F8FFEE7E08D002038B5C368DC6824B304F118052846FEF7DB -S3250800A48021FB184B1B682BBB251D2846FEF71AFBE06A154B1B68984201D9134B186000EB6A -S3250800A4A080002946114B03EB8000FEF7E7FAE26A0F4B1B68DB6A9A4211D901200D4B1860DA -S3250800A4C038BD4FF0500383F31188BFF36F8FBFF34F8FFEE729460848FEF7D0FAE7E7002047 -S3250800A4E0EEE700BF549200205C920020EC8D0020E08D0020DC9200209892002038B51C4B54 -S3250800A5001B6843B94FF0500383F31188BFF36F8FBFF34F8FFEE741F000410160C468F4B144 -S3250800A520FEF7D0FA251D2846FEF7CCFAE06A114B1B68984201D90F4B186000EB800029465A -S3250800A5400D4B03EB8000FEF799FAE26A0B4B1B68DB6A9A4202D90A4B01221A6038BD4FF058 -S3250800A560500383F31188BFF36F8FBFF34F8FFEE7549200205C920020EC8D0020E08D00200C -S3250800A580DC920020034B1B680360034B1B684360704700BF90920020D8920020F8B5C8B10F -S3250800A5A00C460546F9B1FEF70DFB1B4B19686B68C81A2268B2F1FF3F26D0184E36682F68B1 -S3250800A5C0B74201D08B4224D9824215D80023236001241AE04FF0500383F31188BFF36F8F12 -S3250800A5E0BFF34F8FFEE74FF0500383F31188BFF36F8FBFF34F8FFEE75B1A13442360284655 -S3250800A600FFF7C0FF002400E00024FEF7FDFA2046F8BD0124F9E700BFD892002090920020B8 -S3250800A620014B01221A607047DC920020014B1868704700BFE08D0020054B1B6833B1054B08 -S3250800A6401B680BB1002070470220704701207047AC9200205492002000283ED038B5044654 -S3250800A660C36A204A1268D26A93422ED28269002A05DB1C4A1268D26AC2F1380282616169FF -S3250800A68003EB8303184A02EB8303994205D0154B1B68DB6AE362012038BD251D2846FEF78B -S3250800A6A011FA104B1B68D86AE062104B1B68984201D90E4B186000EB800029460A4B03EB9F -S3250800A6C08000FEF7DBF90120E6E7C26C054B1B68DB6A9A4203D30020DEE700207047012060 -S3250800A6E0DAE700BFE08D0020EC8D00205C92002000283BD038B504461E4B1B68834208D0A5 -S3250800A7004FF0500383F31188BFF36F8FBFF34F8FFEE7036D43B94FF0500383F31188BFF3A6 -S3250800A7206F8FBFF34F8FFEE7013B0365C16AC26C91421DD00BB1002038BD051D2846FEF785 -S3250800A740C1F9E06CE062C0F13803A3610A4B1B68984201D9084B186000EB80002946074B30 -S3250800A76003EB8000FEF78AF90120E5E7002070470020E1E7E08D00205C920020EC8D002005 -S3250800A780002846D038B50446036D43B94FF0500383F31188BFF36F8FBFF34F8FFEE7C26CD6 -S3250800A7A08A4200D20A46E16A914201D0012B00D038BD184B1B68A34222D0E262A369002B85 -S3250800A7C002DBC2F13802A261626901EB8101124B03EB81039A42EBD1251D2846FEF772F9EE -S3250800A7E0E06A0E4B1B68984201D90C4B186000EB80002946084B03EB8000FEF73FF9D7E71C -S3250800A8004FF0500383F31188BFF36F8FBFF34F8FFEE77047E08D0020EC8D00205C92002079 -S3250800A820044A136898691368DB6A1268C3F1380393617047E08D0020054B1B6823B1044BE9 -S3250800A8401A68136D01331365014B1868704700BFE08D0020064B1A6813682BB901230360B4 -S3250800A86023B9D368186870470023F8E700207047E092002008B54160006191420CD8D21AAF -S3250800A88083699A4201D3012008BD011D094B1868FEF7FFF80020F7E79A4201D2994206D2EA -S3250800A8A0011D054B1868FEF7F4F80020ECE70120EAE700BFE4920020E092002030B583B0D7 -S3250800A8C0FEF780F9114B1B681BB1FEF79DF903B030BD0F4D2846FEF7C3F80E4C2046FEF7F7 -S3250800A8E0BFF80D4B1D600D4B1C60002300930C4B0C4A10210A20FEF7D4FC044B1860002878 -S3250800A900E3D00949FFF7A6F8DFE700BF04940020889300209C930020E0920020E4920020A1 -S3250800A920B4930020E8920020A0B500082DE9F041079F41B94FF0500383F31188BFF36F8F73 -S3250800A940BFF34F8FFEE7064614461D4688468FB1FFF7B4FF3E60C7F81880FD61069B3B6223 -S3250800A960381DFEF788F82CB197F8283043F0040387F82830BDE8F08110B588B0FFF79EFF84 -S3250800A980124B1B68CBB100240594069407AA06A905A8FDF701FF059B0293069B0193022366 -S3250800A9A000932346079A0A490A48FFF74BFA0A4B186010B1012008B010BD4FF0500383F3D0 -S3250800A9C01188BFF36F8FBFF34F8FFEE704940020A8B5000869AD0008089400202DE9F0416D -S3250800A9E082B00446884617461D462C20FEF7A2FA064658B1002380F828300190089B009353 -S3250800AA002B463A4641462046FFF790FF304602B0BDE8F08110B584B084462C20039003984A -S3250800AA202C2808D04FF0500383F31188BFF36F8FBFF34F8FFEE70398079860B10220079C06 -S3250800AA4084F828000194069800906046FFF76EFF079804B010BD4FF0500383F31188BFF305 -S3250800AA606F8FBFF34F8FFEE7B8B19C4603461848006858B300B585B000910192029305291D -S3250800AA801CDCFFF7D9FD022810D000231A4669460F480068FEF773FC15E04FF0500383F388 -S3250800AAA01188BFF36F8FBFF34F8FFEE70023069A694607480068FEF762FC04E0002362469F -S3250800AAC06946FEF766FD05B05DF804FB002070470494002070B582B01B4B1B681A6862B3F2 -S3250800AAE0DB681E68DC68251D2846FDF7EBFF236A2046984794F8283013F0040FECD0A36919 -S3250800AB0033449E4207D26360246129460E4B1868FDF7BFFFE0E7002100910B46324620460D -S3250800AB20FFF7A2FF0028D7D14FF0500383F31188BFF36F8FBFF34F8FFEE7044A10680249C9 -S3250800AB400860136002B070BDE0920020E492002038B50546FFF746FA0446074B1B688342B3 -S3250800AB6005D800232B60044B1C60204638BDFFF7B1FF01232B60F6E7B093002070B582B02A -S3250800AB8006460D4617490968C968CC68201DFDF799FF94F828C01CF0040F08D12CF0010C74 -S3250800ABA084F828C0236A2046984702B070BDA16933462A4631442046FFF75CFE0028F1D06B -S3250800ABC0002100910B4632462046FFF74DFF0028E8D14FF0500383F31188BFF36F8FBFF360 -S3250800ABE04F8FFEE7E092002070B582B006460C46FFF7F0F901A8FFF7ABFF019B33BB054600 -S3250800AC000CB9B04219D224B1124A12681268DAB901242246711B104B1868FEF72FFFFFF7BF -S3250800AC2073FAA8B94FF0E0234FF08052C3F8042DBFF34F8FBFF36F8F0AE0FFF765FA29460B -S3250800AC403046FFF79BFF03E01C46E2E7FFF75CFA02B070BDE49200200494002010B588B05C -S3250800AC6002E0049B002B0FDA002204A93D4B1868FEF7F6FC002873D0049B002BF1DA0799D3 -S3250800AC800698059B9847ECE7069C636913B1201DFDF718FF03A8FFF75BFF049B092BE3D8B3 -S3250800ACA0DFE803F00505053037500505303794F8283043F0010384F82830059BA1690246B4 -S3250800ACC019442046FFF7D6FD0028CDD0236A2046984794F8283013F0040FC5D0A269002188 -S3250800ACE000910B46059802442046FFF7BDFE0028BAD14FF0500383F31188BFF36F8FBFF3B4 -S3250800AD004F8FFEE794F8283023F0010384F82830AAE794F8283043F0010384F82830059975 -S3250800AD20A16131B10346024601442046FFF7A2FD9AE74FF0500383F31188BFF36F8FBFF3CC -S3250800AD404F8FFEE794F8283013F0020F04D023F0010384F8283087E72046FEF769F983E7D6 -S3250800AD6008B010BD0494002000B583B001A8FFF771FD0199FFF738FFFFF770FFF6E740B199 -S3250800AD8010B50446FDF71EFFE469FDF73DFF204610BD4FF0500383F31188BFF36F8FBFF3D2 -S3250800ADA04F8FFEE710B584B014461A466FF0010300930190029103940023694602480068DA -S3250800ADC0FEF7E7FB04B010BD04940020DFF834D0F9F7F4FE0C480D490D4A002302E0D45866 -S3250800ADE0C4500433C4188C42F9D30A4A0A4C002301E013600432A242FBD300F06FF8F9F734 -S3250800AE007FFCFEE7000001200000002000010020C0B50008000100204C950020FEE7024498 -S3250800AE200346934200D1704703F8011BF9E70000294B1B68834270B504464BD0C36943B101 -S3250800AE40DB68002B44D1E369196811B1204600F079F8616911B1204600F074F8E16911B1B1 -S3250800AE60204600F06FF8216B11B1204600F06AF8616B11B1204600F065F8A16B11B120468C -S3250800AE8000F060F8A16C11B1204600F05BF8616C11B1204600F056F8E16A11B1204600F04E -S3250800AEA051F8236AB3B12046BDE870401847495941B90435E369802DD968F8D1204600F002 -S3250800AEC041F8C0E70E68204600F03CF83146EFE70025EFE770BD00BFF800002070B50D4DB9 -S3250800AEE00D4C641BA4100026A64209D10B4D0C4C00F080F8641BA4100026A64205D170BD74 -S3250800AF0055F8043B98470136EEE755F8043B98470136F2E7B0B50008B0B50008B0B50008EA -S3250800AF20B4B50008704770470A44914200F1FF3300D1704710B511F8014B03F8014F914220 -S3250800AF40F9D110BD37B5002944D051F8043C0190002BA1F10404B8BFE41800F03FF81E4A42 -S3250800AF600198136833B96360146003B0BDE8304000F03AB8A34208D9256861198B4201BF88 -S3250800AF8019685B6849192160EDE71A465B680BB1A342FAD911685518A5420BD12468214477 -S3250800AFA05418A3421160E0D11C685B6853600C441460DAE702D90C230360D6E72568611960 -S3250800AFC08B4204BF19685B68636004BF491921605460CAE703B030BD489500200148FFF7E5 -S3250800AFE0A1BF00BF449500200148FFF79CBF00BF44950020F8B500BFF8BC08BC9E4670475A -S3250800B000F8B500BFF8BC08BC9E46704700000000494E49545F5468726561640010B00008F0 -S3250800B02000000000000000000000000000000000000400002F0000000000000000000000CF -S3250800B0404D41494E5F5761746368646F670000004D41494E5F55706461746554696D657245 -S3250800B060000000004D41494E5F4576656E745F466C616773000000004D41494E5F43414E9A -S3250800B0805F52785F51756575650000004D41494E5F5468726561640078B000080000000009 -S3250800B0A00000000000000000000000000000000064B0000800000000000000000000000066 -S3250800B0C08CB0000800000000000000000000000000000000000400002100000000000000F9 -S3250800B0E00000000050B0000800000000000000000000000040B00008000000000000000042 -S3250800B100000000005045434F5F4576656E745F466C616773000000005045434F5F5570649E -S3250800B12061746554696D6572000000005045434F5F5468726561640004B10008000000002B -S3250800B14000000000000000002CB100080000000000000000000000000000000000040000F8 -S3250800B16028000000000000000000000018B100080000000000000000000000005641524897 -S3250800B1805F4D7574657800000000000001000000000000000100000001000000000000002C -S3250800B1A0000000C0000040411100000000000000000000000000C842110000000000000014 -S3250800B1C0000000000000C8421100000000000000000000000000C842010000000000B84142 -S3250800B1E0000020C2000048421100000000002041000000000000404111000000000000C011 -S3250800B200000000C0000000000900000000000000000070C20000C842090000000000000012 -S3250800B220000070C20000C8420900000000000000000048C200008C420900000000000000DA -S3250800B2400000A0C0000060410900000000000000000020C10000204109000000000000008B -S3250800B260000000000000A0400900000000000000000048C20000164309000000000000006B -S3250800B2800000A0410000F0410900000000000000000000000000A04009000000000000009C -S3250800B2A0000000000000164308000000000000000000000001000000080000000000000016 -S3250800B2C000000000FFFFFFFF7CB10008030000000000000000000000414443445F4D75748B -S3250800B2E065780000D8B20008030000000000000000000000414E50495F4D75746578000034 -S3250800B300414E50495F4576656E745F466C61677300000000414E50495F546872656164006B -S3250800B320000020410000A040000020410000A04000000000000004419A996D410000044112 -S3250800B340F4B2000803000000000000000000000000B3000800000000000000000000000073 -S3250800B36014B3000800000000000000000000000000000000000400001000000000000000DC -S3250800B3800000000000040048800000000000000000000000010000000000000000000000D2 -S3250800B3A00100000000080048008000000000000000000000010000000000000000000000AD -S3250800B3C0010000000004004808000000000000000000000001000000000000000000000009 -S3250800B3E00100000000040048100000000000000000000000010000000000000000000000E1 -S3250800B400010000000000004800800000000000000000000001000000000000000000000054 -S3250800B42001000000000400484000000001000000000000000100000000000000010000006E -S3250800B44000000000000400482000000001000000000000000100000000000000010000006F -S3250800B46000000000000800480040000001000000000000000100000000000000000000002C -S3250800B480010000000000004800010000010000000000000001000000000000000000000052 -S3250800B4A001000000535049445F4576656E745F466C61677300000000535049445F41444349 -S3250800B4C05F4D7574657800000404002000000000DCB400080100000002000000B8B40008B5 -S3250800B4E0030000000000000000000000A4B4000800000000000000000000000054454D50A5 -S3250800B5005F54687265616400FCB400080000000000000000000000000000000000040000AA -S3250800B52018000000000000000000000044656661756C74002CB50008000000000000000037 -S3250800B5400000000000000000000200001800000000000000000000000000000000000000C3 -S3250800B5600102030406070809A0860100400D0300801A060000350C0040420F0080841E008A -S3250800B58000093D0000127A000024F40000366E010048E801006CDC0249444C450000000075 -S3250800B5A0546D725100000000546D722053766300F131000800000000CD310008000000004A -S3250800B5C000FF0000EC010020E401002000000000000000000000000000000000000000004C -S3250800B5E000000000000000000000000000000000000000000000000000000000000000003D -S3250800B6000000000033335340333353400060000000000000E0E90000000000000000000001 -S3250800B6200100000000000000010000000100000000000000004000000000000000E80000D1 -S3250800B6400000000000000000000000000000000001000000010000000000000000093D0094 -S3250800B6600100000010000000AAAAAAAA000000000C94002074940020DC940020000000008B -S3250800B68000000000000000000000000000000000000000000000000000000000000000009C -S3250800B6A0000000000000000000000000000000000000000000000000AC00002000000000B0 -S503047682 -S7050800ADCD78 diff --git a/PeltierControllerV2.srec b/PeltierControllerV2.srec new file mode 100644 index 0000000..933f7a3 --- /dev/null +++ b/PeltierControllerV2.srec @@ -0,0 +1,1337 @@ +S0220000687474703A2F2F737265636F72642E736F75726365666F7267652E6E65742F1D +S32508002800000001206DBD0008D54D0008D74D0008D94D0008DB4D0008DD4D00080000000071 +S32508002820000000000000000000000000419B0008DF4D000800000000E19B0008E14D0008B8 +S32508002840BDBD0008BDBD0008BDBD0008BDBD0008BDBD0008BDBD0008BDBD0008BDBD00085A +S32508002860BDBD0008BDBD0008BDBD0008BDBD0008F94D0008094E0008BDBD0008BDBD000891 +S32508002880BDBD0008BDBD0008194E0008294E0008394E0008494E0008594E0008BDBD0008D9 +S325080028A0BDBD0008BDBD0008BDBD0008BDBD0008BDBD00080000000000000000BDBD0008FE +S325080028C0BDBD00080000000000000000694E000800000000BDBD0008BDBD000800000000A5 +S325080028E0BDBD0008BDBD0008000000000000000000000000000000000000000000000000C6 +S32508002900000000000000000000000000BDBD00080000000000000000BDBD0008BDBD000823 +S32508002920BDBD0008BDBD0008794E0008BDBD0008BDBD0008000000000000000000000000B2 +S32508002940BDBD0008BDBD0008BDBD0008BDBD0008BDBD0008BDBD0008BDBD0008BDBD000859 +S32508002960BDBD0008BDBD0008BDBD000800000000BDBD0008BDBD00080000000000000000BF +S32508002980BDBD0008BDBD0008BDBD0008EE11AA55844641EA000313F003036DD1403A41D3D8 +S325080029A051F8043B40F8043B51F8043B40F8043B51F8043B40F8043B51F8043B40F8043B0D +S325080029C051F8043B40F8043B51F8043B40F8043B51F8043B40F8043B51F8043B40F8043BED +S325080029E051F8043B40F8043B51F8043B40F8043B51F8043B40F8043B51F8043B40F8043BCD +S32508002A0051F8043B40F8043B51F8043B40F8043B51F8043B40F8043B51F8043B40F8043BAC +S32508002A20403ABDD2303211D351F8043B40F8043B51F8043B40F8043B51F8043B40F8043B3C +S32508002A4051F8043B40F8043B103AEDD20C3205D351F8043B40F8043B043AF9D2043208D034 +S32508002A60D2071CBF11F8013B00F8013B01D30B8803806046704700BF082A13D38B078DD00E +S32508002A8010F003038AD0C3F10403D21ADB071CBF11F8013B00F8013B80D331F8023B20F81A +S32508002AA0023B7BE7043AD9D3013A11F8013B00F8013BF9D20B7803704B7843708B7883709E +S32508002AC06046704781F0004102E000BF83F0004330B54FEA41044FEA430594EA050F08BF45 +S32508002AE090EA020F1FBF54EA000C55EA020C7FEA645C7FEA655C00F0E2804FEA5454D4EB83 +S32508002B005555B8BF6D420CDD2C4480EA020281EA030382EA000083EA010180EA020281EAEB +S32508002B200303362D88BF30BD11F0004F4FEA01314FF4801C4CEA113102D0404261EB4101F6 +S32508002B4013F0004F4FEA03334CEA133302D0524263EB430394EA050F00F0A780A4F10104ED +S32508002B60D5F1200E0DDB02FA0EFC22FA05F2801841F1000103FA0EF2801843FA05F3594123 +S32508002B800EE0A5F120050EF1200E012A03FA0EFC28BF4CF0020C43FA05F3C01851EBE37151 +S32508002BA001F0004507D54FF0000EDCF1000C7EEB00006EEB0101B1F5801F1BD3B1F5001F13 +S32508002BC00CD349085FEA30004FEA3C0C04F101044FEA445212F5800F80F09A80BCF1004FD8 +S32508002BE008BF5FEA500C50F1000041EB045141EA050130BD5FEA4C0C404141EB0101013CEE +S32508002C0028BFB1F5801FE9D291F0000F04BF01460020B1FA81F308BF2033A3F10B03B3F186 +S32508002C2020020CDA0C3208DD02F1140CC2F10C0201FA0CF021FA02F10CE002F11402D8BFF6 +S32508002C40C2F1200C01FA02F120FA0CFCDCBF41EA0C019040E41AA2BF01EB0451294330BDDB +S32508002C606FEA04041F3C1CDA0C340EDC04F11404C4F1200220FA04F001FA02F340EA03005B +S32508002C8021FA04F345EA030130BDC4F10C04C4F1200220FA02F001FA04F340EA03002946BE +S32508002CA030BD21FA04F0294630BD94F0000F83F4801306BF81F480110134013D4EE77FEA35 +S32508002CC0645C18BF7FEA655C29D094EA050F08BF90EA020F05D054EA000C04BF19461046B1 +S32508002CE030BD91EA030F1EBF0021002030BD5FEA545C05D14000494128BF41F0004130BD62 +S32508002D0014F580043CBF01F5801130BD01F0004545F0FE4141F470014FF0000030BD7FEAC4 +S32508002D20645C1ABF194610467FEA655C1CBF0B46024650EA013406BF52EA033591EA030F64 +S32508002D4041F4002130BD00BF90F0000F04BF0021704730B54FF4806404F132044FF00005BE +S32508002D604FF0000150E700BF90F0000F04BF0021704730B54FF4806404F1320410F0004569 +S32508002D8048BF40424FF000013EE700BF42004FEAE2014FEA31014FEA02701FBF12F07F4362 +S32508002DA093F07F4F81F06051704732F07F4208BF704793F07F4F04BF41F40021704730B574 +S32508002DC04FF4607401F0004521F000411CE700BF50EA010208BF704730B54FF000050AE0B6 +S32508002DE050EA010208BF704730B511F0004502D5404261EB41014FF4806404F132045FEA5D +S32508002E00915C3FF4D8AE4FF003025FEADC0C18BF03325FEADC0C18BF033202EBDC02C2F1C2 +S32508002E20200300FA03FC20FA02F001FA03FE40EA0E0021FA02F11444BDE600BF70B54FF0FC +S32508002E40FF0C4CF4E06C1CEA11541DBF1CEA135594EA0C0F95EA0C0F00F0DEF82C4481EA44 +S32508002E60030621EA4C5123EA4C5350EA013518BF52EA033541F4801143F4801338D0A0FBF9 +S32508002E8002CE4FF00005E1FB02E506F00042E0FB03E54FF00006E1FB03569CF0000F18BF66 +S32508002EA04EF0010EA4F1FF04B6F5007F64F5407404D25FEA4E0E6D4146EB060642EAC6216F +S32508002EC041EA55514FEAC52040EA5E504FEACE2EB4F1FD0C88BFBCF5E06F1ED8BEF1004FFF +S32508002EE008BF5FEA500E50F1000041EB045170BD06F0004646EA010140EA020081EA03015E +S32508002F00B4EB5C04C2BFD4EB0C0541EA045170BD41F480114FF0000E013C00F3AB8014F133 +S32508002F20360FDEBF002001F0004170BDC4F10004203C35DA0C341BDC04F11404C4F12005E0 +S32508002F4000FA05F320FA04F001FA05F240EA020001F0004221F0004110EBD37021FA04F66D +S32508002F6042EB06015EEA430E08BF20EAD37070BDC4F10C04C4F1200500FA04F320FA05F096 +S32508002F8001FA04F240EA020001F0004110EBD37041F100015EEA430E08BF20EAD37070BD89 +S32508002FA0C4F1200500FA05F24EEA020E20FA04F301FA05F243EA020321FA04F001F000417A +S32508002FC021FA04F220EA020000EBD3705EEA430E08BF20EAD37070BD94F0000F0FD101F05A +S32508002FE00046400041EB010111F4801F08BF013CF7D041EA060195F0000F18BF704703F059 +S325080030000046520043EB030313F4801F08BF013DF7D043EA0603704794EA0C0F0CEA135580 +S3250800302018BF95EA0C0F0CD050EA410618BF52EA4306D1D181EA030101F000414FF00000D6 +S3250800304070BD50EA410606BF1046194652EA430619D094EA0C0F02D150EA013613D195EA8C +S325080030600C0F05D152EA03361CBF104619460AD181EA030101F0004141F0FE4141F47001BA +S325080030804FF0000070BD41F0FE4141F4780170BD70B54FF0FF0C4CF4E06C1CEA11541DBF29 +S325080030A01CEA135594EA0C0F95EA0C0F00F0A7F8A4EB050481EA030E52EA03354FEA0131DF +S325080030C000F088804FEA03334FF0805545EA131343EA12634FEA022245EA111545EA10651A +S325080030E04FEA00260EF000419D4208BF964244F1FD0404F5407402D25B084FEA3202B61A4F +S3250800310065EB03055B084FEA32024FF480104FF4002CB6EB020E75EB030E22BFB61A7546A9 +S3250800312040EA0C005B084FEA3202B6EB020E75EB030E22BFB61A754640EA5C005B084FEACB +S325080031403202B6EB020E75EB030E22BFB61A754640EA9C005B084FEA3202B6EB020E75EBF8 +S32508003160030E22BFB61A754640EADC0055EA060E18D04FEA051545EA16754FEA06164FEAE8 +S32508003180C30343EA52734FEAC2025FEA1C1CC0D111F4801F0BD141EA00014FF000004FF030 +S325080031A0004CB6E711F4801F04BF01430020B4F1FD0C88BFBCF5E06F3FF6AFAEB5EB030C17 +S325080031C004BFB6EB020C5FEA500C50F1000041EB045170BD0EF0004E4EEA113114EB5C04B6 +S325080031E0C2BFD4EB0C0541EA045170BD41F480114FF0000E013C90E645EA060E8DE60CEA51 +S32508003200135594EA0C0F08BF95EA0C0F3FF43BAF94EA0C0F0AD150EA01347FF434AF95EA69 +S325080032200C0F7FF425AF104619462CE795EA0C0F06D152EA03353FF4FDAE1046194622E7D5 +S3250800324050EA410618BF52EA43067FF4C5AE50EA41047FF40DAF52EA43057FF4EBAE12E766 +S325080032604FEA4102B2F1E04324BFB3F5001CDCF1FE5C0DD901F0004C4FEAC0024CEA50701C +S32508003280B2F1004F40EB830008BF20F00100704711F0804F21D113F13872BCBF01F00040D5 +S325080032A0704741F480114FEA5252C2F11802C2F1200C10FA0CF320FA02F018BF40F00100DD +S325080032C04FEAC1234FEAD32303FA0CFC40EA0C0023FA02F34FEA4303CCE77FEA625307D11F +S325080032E050EA01331EBF4FF0FE4040F44000704701F0004040F0FE4040F40000704700BF84 +S3250800330010B5054C237833B9044B13B10448AFF300800123237010BD0006002000000000D7 +S32508003320D4C2000808B5034B1BB103490348AFF3008008BD0000000004060020D4C20008C4 +S3250800334008B500F0A1FB00F0010400F0DBFE044000F0A4FD044000F0EBFD044000F07AFFBA +S32508003360044000F041FC044001F074F8044000F00FFE044000F0C4F9044000F00BF904427D +S325080033801AD105F0B9FE022000F046FF0D4B1B689B0B642202FB03F3002BF4D000BF00BFCA +S325080033A000BF00BF00BF00BF00BF00BF00BF00BF00BF00BF013BEFE7034B186805F010FFA5 +S325080033C0FEE700BF940000201C06002008B5054A0021054805F0A5FE044B1860003818BF5D +S325080033E0012008BDFCC20008413300081C06002000B585B0EC468CE80F0000231A4661468C +S325080034000548006806F008F90121044B186805F095FF05B05DF804FB2006002024060020DF +S3250800342008B50146024B186805F088FF08BD00BF2406002070B588B092E000231A4602A966 +S325080034405148006806F02AF99DF808509DF81160012E14D0022E33D0002E40F08E80082D6A +S325080034603AD86BB2002B00F08880013D072D00F28480DFE805F0393D4182484D5A6B142DF4 +S3250800348009D9FF238DF818303346059A012106A800F0C6FD71E0284600F0C2FA01908DF831 +S325080034A0185004220DF119010DEB020001F032FD9DF81130059A052106A800F0B1FD5CE01B +S325080034C004220DEB02010DF1090001F023FD0199284600F051FA50E0FF2D4ED1002000F0D7 +S325080034E0C9F802F0A3FF48E0012000F0C3F844E0002000F0BFF840E040F6B831234B18685D +S3250800350005F0E0FE39E00021132000F07BFA34E006238DF8183001238DF819303346059AE4 +S32508003520022106A800F07CFD27E007238DF8183000F0BCFA00B1FF268DF819609DF81130F5 +S32508003540059A022106A800F06BFD16E000F0CEFA13E0022000F060FE12E0002000F08AF800 +S325080035604FF0FF33002207210948006805F033FF044610F0010F7FF460AF14F0020FE8D1F8 +S3250800358014F0040FECD0E8E720060020300600202406002070B5254805F0AEFE244B18607B +S325080035A0041E18BF0124234A0021234805F0B9FD224B186000280CBF002404F00104204ADC +S325080035C01021082005F0DDFF1E4B186000280CBF002404F001041C4E1C4B02220121304635 +S325080035E005F01CFE1A4D286000280CBF002404F00104184B02220121304605F00FFE164B2D +S32508003600186000280CBF002404F001044FF47A71286805F057FE002814BF002404F00104F4 +S325080036200E4800F025FD204670BD00BF90C3000824060020A0C300083534000828060020F3 +S3250800364078C300082006002021340008C4C300082C060020D4C3000830060020F133000874 +S3250800366008B50146024B186805F068FE08BD00BF3406002010B504460146032000F090FD3C +S325080036802146122000F0BEF910BD08B5122000F0DBF908BD0000000008B5F2EE087AB4EED6 +S325080036A0E70AF1EE10FA01DDB0EE670AF8EE087AB4EEE70AF1EE10FA01D5B0EE670A10EE6E +S325080036C0100AFFF763FB0AA3D3E90023FFF700FA09A3D3E90023FFF7DBFCFFF7C1FD00EEF8 +S325080036E0100A00F047FC00F0010008BDAFF300804A0C022B8716344077BE9F1A2F0D414058 +S3250800370038B5174A0021174805F00BFD164B1860041E18BF0124154805F0EEFD144B1860C5 +S3250800372000280CBF002404F00104124B01221146114805F073FD114D286000280CBF0024D9 +S3250800374004F001049FED0E0AFFF7A6FF6421286805F0B8FD002814BF002004F0010038BD5F +S3250800376028C40008853700083806002018C40008340600204CC40008613600083C060020CE +S325080037800000000008B52DED088BDFED438AB0EE688A05E0DFED408AB0EE6A0AFFF77CFF8A +S325080037A0F0EE689AB0EE489A4FF0FF33002201213A48006805F00FFE10F0010FF4D03848A6 +S325080037C003F031FDFFF761FF9FED338AF0EE488A0028E5D0002000F037F9002848D10220EB +S325080037E000F036F9F0EE408A032000F031F9B0EE40AA042000F02CF9B0EE40BA062000F048 +S3250800380027F9F0EE40AA072000F022F9F0EE40BA092000F01DF9B0EE408A052000F018F9EB +S3250800382038EE408A68EE887ADFED1E6A68EE268A78EEA98A2AEE28AA38EE497A27EE0B7AD2 +S3250800384087EE266A77EE8A7A77EE867AF4EEE7AAF1EE10FA9ED4F4EEE7BAF1EE10FA02DC6F +S32508003860F0EE67AA98E7F0EE6BAADFED0B8A93E7002000F0E9F8012804D0F0EE698AB0EEA1 +S32508003880498A8DE700F0E4F8FFF706FFDFED028AB0EE688A84E700BF0000000034060020A0 +S325080038A028090020CDCCCC3D01288CBF0020012070470000084B03EB00139B688B4207D898 +S325080038C0054B03EB0013DB688B4203D200207047002070470120704768C40008084B03EBA9 +S325080038E000139B688B4207DC054B03EB0013DB688B4203DA00207047002070470120704730 +S3250800390068C400080C4B03EB0013D3ED027AF4EEC07AF1EE10FA0BD8074B03EB0013D3EDD6 +S32508003920037AF4EEC07AF1EE10FA03DA00207047002070470120704768C4000808B503019F +S325080039400C4AD35C13F0010F09D113F0020F0BD113F0040F0BD00846FFF7A6FF03E000EE4C +S32508003960101AFFF7CFFF08BDFFF7B8FFFBE7FFF7A1FFF8E768C4000838B503010D4AD35CD7 +S3250800398013F0080F00D038BD04460D464FF0FF31094B186805F0A3FD29462046FFF7CEFF2D +S325080039A010B1064B43F83450034B186805F0C3FDE9E700BF68C40008E8060020400600206E +S325080039C038B504460D464FF0FF310C4B186805F086FD29462046FFF7B1FF30B9084B03EBEC +S325080039E0C4031A7942F002021A71054B43F83450024B186805F09FFD38BD00BFE80600206F +S32508003A004006002008B5FFF7DBFF08BD00B583B08DED010A0199FFF7D3FF03B05DF804FB0A +S32508003A2038B50446064D4FF0FF31286805F057FD044B53F83440286805F07DFD204638BD3E +S32508003A40E80600204006002008B5FFF7E9FF08BD08B5FFF7E5FF00EE100A08BD08B5034B15 +S32508003A6003EB00135968FFF7ABFF08BD68C4000810B5002404E0E0B2FFF7F0FF0134A4B20E +S32508003A80142CF8D910BD000010B5064805F0DDFC054B1860041E18BF0124FFF7E9FF20462F +S32508003AA010BD00BFB8C50008E806002038B500F030FD0024012501E00134E4B2142C0ED8B3 +S32508003AC02301094AD35C13F0100FF5D02046FFF7BBFF0146204600F0E7FC0540ECE700F0AD +S32508003AE011FD284638BD00BF68C4000830B583B00024012501E00134E4B2142C10D82301FA +S32508003B00114AD35C13F0100FF5D001A9204600F0B3FC0540EFD001992046FFF773FFEAE73A +S32508003B207DB103B030BD0134E4B2142CF9D82301054AD35C13F0100FF5D02046FFF78EFF5B +S32508003B40F1E70024F1E700BF68C4000808B572B10D4B60F07F00187000225A7099700B48B9 +S32508003B600323838100F084FB00F0010008BD064B60F07F001870597004480223838100F012 +S32508003B8077FB00F00100F1E7F40600200000002010B50C4692B1114B187000225A709A706E +S32508003BA00F480323838100F063FB00F001000D4B5A789B7843EA0223238010BD074B18705E +S32508003BC000225A7006480223838100F051FB00F00100044B5B782380EFE700BFF4060020D3 +S32508003BE000000020EC06002038B5144805F02DFC134D2860041E18BF01244FF0FF3105F0B4 +S32508003C006EFC002000F05EFA002282211046FFF79DFF0440002000F065FA012000F052FA07 +S32508003C20002282211046FFF791FF0440012000F059FA286805F07FFC204638BDD4C5000831 +S32508003C40FC0600202DE9F04182B00F46904600230B70ADF8063018B1012854D0012600E0FA +S32508003C6001263F4D4FF0FF31286805F038FC304600F028FA0022A0211046FFF767FF00F04E +S32508003C800104304600F02EFA286805F054FC642005F0B5FA4FF0FF31286805F020FC304600 +S32508003CA000F010FA01220DF106011046FFF770FF0440304600F016FA286805F03CFC24B3CB +S32508003CC0BDF8063013F0010F24D15B08ADF80630A8F80030224D4FF0FF31286805F0FFFB78 +S32508003CE0304600F0EFF9002284211046FFF72EFF0440304600F0F6F9286805F01CFC20468C +S32508003D0002B0BDE8F0810026ABE73B7843F002033B70F4E7124C4FF0FF31206805F0DFFB80 +S32508003D20304600F0CFF9002239460720FFF730FF304600F0D7F9304600F0C4F9002282213C +S32508003D401046FFF703FF304600F0CCF9206805F0F2FB3B7843F001033B700024CFE700BF44 +S32508003D60FC06002010B52DED028B88B0012005F046FA08224149424801F052FE6EE0042424 +S32508003D804FF0FF313F4B186805F0A9FB00230AE0E1183A4A32F8111008AA02EB830242F8D0 +S32508003DA0101C01339BB2032BF2D91420FFF750FE002322E008AA02EB830151ED047AF8EEED +S32508003DC0677A9FED317A67EE877A9FED307A67EE877A67EE807A2E4A02EB830292ED007AA9 +S32508003DE067EE277A2B4A02EB830292ED007A77EEC77A41ED087A01339BB2032BDAD9DDED5D +S32508003E00028AB0EE680A0B20FFF700FE9DED038AB0EE480A0C20FFF7F9FD88EE880A0D2085 +S32508003E20FFF7F4FD28EE880A0D20FFF7EFFDDDED008AB0EE680A0F20FFF7E8FD9DED018A53 +S32508003E40B0EE480A1020FFF7E1FD28EE880A1120FFF7DCFD0B4B186805F06DFB4FF0FF3314 +S32508003E60002203210C48006805F0B5FA10F0020F85D110F0010FF1D0002481E700070020A3 +S32508003E8038070020140700200000803D0000803910C6000820C600081007002010B50F4AE3 +S32508003EA000210F4805F03DF90E4B1860041E18BF01240D4805F020FA0C4B186000280CBF3C +S32508003EC0002404F001040A4805F0BFFA094B186000280CBF002004F0010010BD50C60008F8 +S32508003EE0653D00081807002040C600081007002030C600081407002008B50221024B1868A0 +S32508003F0005F01CFA08BD00BF1007002008B50121024B186805F012FA08BD00BF1007002065 +S32508003F20836D836D836D836DC36CDB6B7047000008B50021034802F028FBB0FA80F04009E6 +S32508003F4008BD00BFE807002008B52DED028BDFED087A20EE278A1420FFF77AFDC8EE007A7E +S32508003F60FCEEE77A17EE900ABDEC028B08BD00BF00F07F4508B5FFF7E7FF03460022114680 +S32508003F80024802F034FB00F0010008BDE807002070B5042000F020F91D4C237803432370B4 +S32508003FA0032000F019F9237843EA40032370022000F012F9237843EA80032370012000F024 +S32508003FC00BF9237843EAC000C0B22070114E336843EA40133360104D1049284601F0C1FE64 +S32508003FE004463146284601F0BCFE0443E4B2284601F03AFF0443E4B20221284602F07CF890 +S32508004000204310F0FF0F0CBF0120002070BD00BF20070020440000209C0700206C0000202F +S32508004020082901D90020704700B587B012021FFA82FC4CEA03130C4A1278134343F41073BD +S325080040400093002301930293039304918DF81430012302466946054801F034FFB0FA80F0D9 +S32508004060400907B05DF804FB200700209C070020014B1860704700BF1C07002030B58FB033 +S3250800408005AB07AA002101F092FF079BC3F300220492C3F301138DF80D309DF82C208DF80C +S325080040A00C2001AC214605A800F034FF034B1D6894E80F00A8470FB030BD00BF1C070020E7 +S325080040C0436A704708B5064B4FEA401C03EB4010027F818853F80C0002F0ABFF08BD00BF8C +S325080040E014C7000808B5064B4FEA401C03EB4010027E818853F80C0002F09BFF08BD00BFFE +S3250800410014C7000870B582B0224B1A6E42F001021A661B6E03F001030193019B01250024B3 +S325080041200BE000231D401C4B4A0103EB41110431985802F09FFE0134E4B2042C08D821461E +S32508004140154B03EB44139B68002BEAD10123E9E700240EE001231D402046FFF7C3FF0F4BC4 +S32508004160720103EB46110431985802F083FE0134E4B2032C0AD82646084B03EB44139B68FE +S32508004180012BE8D0112BE5D00023E4E7284602B070BD00BF0010024074C6000814C70008CB +S325080041A008B559B10B4B4FEA401C03EB4010027F818853F80C0002F03CFF08BD054B4FEAA5 +S325080041C0401C03EB4010027E818853F80C0002F030FFF2E714C7000838B504460D4B4201A8 +S325080041E003EB4015A988985802F01CFFEB69012B07D0084B03EB44139B69012B05D000202C +S3250800420038BD0128F5D10120FAE708B10020F7E70120F5E774C6000808B5044B420103EB77 +S3250800422040108188985802F009FF08BD14C700080246002008B10020704700EB80030449D2 +S3250800424051F823309342F7D0431CD8B2F2E700BFB8C7000808B5044805F04EF8034B186006 +S32508004260003818BF012008BDDCC700082407002038B504460378244D03EB830305EB830338 +S325080042804FF0FF31586805F02AF9237803EB830305EB8303D96841F002011C4B186805F0F3 +S325080042A07AF8237803EB8300A389A268616855F8200004F099F800280CBF0125002511D062 +S325080042C00020237810F0020F05F0010518BF002503EB83030C4A02EB8303586805F02BF9F7 +S325080042E0284638BD237803EB8303074A02EB8303D9684FF0FF33002241F0020103480068BF +S3250800430005F069F8DDE700BFB8C700082407002008B5FFF78DFF00EB8000044B03EB80037A +S32508004320D968034B186805F009F808BDB8C700082407002008B5FFF77BFF00EB8000044BEC +S3250800434003EB8003D968034B186804F0F7FF08BDB8C700082407002008B5026E826DD26BF5 +S32508004360436DDB6BFFF764FF0221024B186804F0E5FF08BD2407002000EE100AB8EEC00A90 +S32508004380DFED097A20EE270ADFED087A60EE277A9FED077A77EE877A20EE270ADFED057A47 +S325080043A030EE670A704700BF00000039DB8A1F416DE76B4342E0754310B52DED028B84B070 +S325080043C000238DF80F300A2004F019FF012422E01F4B019300238DF80F30012429E0BDF8C3 +S325080043E00C00FFF7C9FF8DED020ADDED018AB0EE680A0820FFF70AFB9DED028AB0EE480AD1 +S325080044000920FFF703FB38EEC80A0A20FFF7FEFA642004F0F4FE03AA0DF10F010020FFF726 +S3250800442011FC0440D4D0BDF80C00FFF7A5FF8DED010A03AA0DF10F010120FFF703FC044084 +S32508004440CDD1034B029300238DF80F300124CCE77B9488C308B5054A0021054804F061FEE7 +S32508004460044B1860003818BF012008BDF8C70008B94300082807002070B504460D46094E3F +S325080044804FF0FF31306805F02AF82946204604F0FDFBB0FA80F46409306805F04CF820466D +S325080044A070BD00BF3007002038B504460D464FF0FF31124B186805F012F82946204604F00D +S325080044C0ADFD0546B0FA80F4640910F4807F08D1EDB2FF2D10D0094B186805F02CF8204674 +S325080044E038BD074B01221A6004F02EFA0543ADB2B5FA85F46409EBE70024ECE73007002052 +S325080045002C07002008B502F051FBB0FA80F0400908BD08B502F032FBB0FA80F0400908BD13 +S32508004520014A024B9A6070470028000800ED00E02DE9F04188B00024039404940594069422 +S325080045400794364BDA6C42F00402DA64DA6C02F004020092009ADA6C42F00102DA64DA6C0C +S3250800456002F001020192019ADA6C42F00202DA64DB6C03F002030293029B294F22464FF4BC +S325080045808041384602F055FD22464FF480714FF0904002F04EFD234D22466021284602F0E9 +S325080045A048FD4FF480430393012604960594069403A9384602F05EFC4FF40048CDF80C80C6 +S325080045C00494059403A9384602F054FC4FF48073039304960594069403A94FF0904002F0EA +S325080045E049FCCDF80C800494059403A94FF0904002F040FC982303930494059403A9284661 +S3250800460002F038FC6023039304960594069403A9284602F02FFC08B0BDE8F0810010024029 +S32508004620000800480004004800B583B0164B9A6C42F001029A649A6C02F001020092009A27 +S325080046409A6C42F002029A649B6C03F002030193019B002205210C2001F0A2FE0C2001F0C1 +S32508004660D7FE002205210D2001F09AFE0D2001F0CFFE002205213A2001F092FE3A2001F000 +S32508004680C7FE03B05DF804FB0010024008B5FEF79DFE024B186804F0A3FDFEE73407002000 +S325080046A072B6FEE700B587B000230093019302930393049305932F482F4A02604360836077 +S325080046C0C3600122026108214161037642760421C16180F820308362C36280F830204363A0 +S325080046E080F838201C21C163802101644364826400F076FC002832D1204B009306230193A0 +S32508004700072302937F23039304230493002305936946184800F0C4FE18BB194B00930C2361 +S3250800472001936946134800F0BBFEE0B9154B00931223019369460F4800F0B2FEA8B9124B6B +S3250800474000931823019369460A4800F0A9FE70B97F21084801F00EFA07B05DF804FBFFF73E +S325080047609FFFFFF79DFFFFF79BFFFFF799FFFFF797FF00BF38070020000004504000201966 +S32508004780000021438000501D0080F03E08B50D480D4B03602023436000238360C3604FF4ED +S325080047A0402202614FF4A00242610376437683760122C2760377437701F02DFA00B908BD4E +S325080047C0FFF76EFF9C0700200064004000B58BB02422002101A807F0F9FA1048104B036001 +S325080047E001F0C1FE98B900220192029203920492059201A9094801F011FF50B9002201A9CE +S32508004800064801F0A6FF30B90BB05DF804FBFFF747FFFFF745FFFFF743FF00BFE807002032 +S325080048200074004008B51048104B03604FF482734360002383604FF4E062C26003610122D4 +S3250800484042614FF4007282613022C2610362436283620722C2620363436303F055FD00B954 +S3250800486008BDFFF71DFF00BF380900200030014008B51148114B0360114B436000238360E8 +S325080048800122C260036143618361C361036202F0DEFB50B90021084802F037FC38B90021D4 +S325080048A0054802F060FC20B908BDFFF7F9FEFFF7F7FEFFF7F5FE00BFD408002000540040A1 +S325080048C0EC9C901008B50848084B03600623436040F6FF73C3609623836002F070FC00B995 +S325080048E008BDFFF7DDFE00BF280900200030004008B50848084B03600023037143714361E2 +S3250800490083610123036201F0B7FD00B908BDFFF7C7FE00BFC40700200030024000B597B026 +S325080049204422002105A807F051FA0023009301930293039304934FF4007002F083FC30BBD8 +S32508004940092305934FF4A023069301230A9302230F930322109204221192102212920722CF +S3250800496013921493159305A802F056FD88B90F230093032301930023029303930493042179 +S32508004980684603F07FF830B917B05DF804FBFFF787FEFFF785FEFFF783FE000008B5FFF7CF +S325080049A0BFFD00F0E7FAFFF7B9FFFFF7C1FDFFF73BFEFFF777FEFFF7E9FEFFF707FFFFF791 +S325080049C031FFFFF755FFFFF77DFFFFF791FF04F065FB054A0021054804F0A3FB044B1860ED +S325080049E004F06EFBFEE700BF24C800088D4600083407002000B583B00D4B1A6E42F0010281 +S32508004A001A661A6E02F001020092009A9A6D42F080529A659B6D03F080530193019B002235 +S32508004A200F216FF0010001F0BBFC03B05DF804FB0010024070B59EB00446002119911A91A4 +S32508004A401B911C911D91542204A807F0BFF92268334B9A4201D01EB070BD4FF48043049323 +S32508004A604FF04053169304A803F086F9002850D12C4BDA6C42F40052DA64DA6C02F4005235 +S32508004A800192019ADA6C42F00102DA64DA6C02F001020292029ADA6C42F00202DA64DB6CB5 +S32508004AA003F002030393039B062319930B261A9600251B9519A94FF0904002F0DBF9032374 +S32508004AC019931A961B9519A9174802F0D3F91748174B036045608560C560802303614FF4C0 +S32508004AE0807343614FF4806383612023C3614FF40053036201F0D2FE70B90C4BE3649C621F +S32508004B0000220521122001F04BFC122001F080FCA1E7FFF7C5FDABE7FFF7C2FDEDE700BF1C +S32508004B20000004500010024000040048FC0700203004024000B589B0002303930493059306 +S32508004B40069307930268244B9A4202D009B05DF804FB03F5D6339A6D42F000729A659A6DCE +S32508004B6002F000720192019ADA6C42F00102DA64DB6C03F001030293029B4FF4C053039380 +S32508004B8002230493032306930923079303A94FF0904002F06FF900220521132001F000FC49 +S32508004BA0132001F035FC00220521142001F0F8FB142001F02DFC00220521152001F0F0FB8B +S32508004BC0152001F025FC00220521162001F0E8FB162001F01DFCB9E7006400400268094BEC +S32508004BE09A4200D0704782B0A3F500539A6C42F480529A649B6C03F480530193019B02B068 +S32508004C00704700BF0030024000B589B00023039304930593069307930268124B9A4202D020 +S32508004C2009B05DF804FB03F5CE339A6D42F000529A659A6D02F000520192019ADA6C42F0E5 +S32508004C400102DA64DB6C03F001030293029B102303930323049303A94FF0904002F00AF95F +S32508004C60DEE700BF0074004010B59CB0044600211791189119911A911B91542202A807F009 +S32508004C80A5F82268184B9A4201D01CB010BD4023029302A803F070F818BB144CE36C43F084 +S32508004CA00103E364E36C03F001030093009B4FF4C0631793122318930023199303231A9395 +S32508004CC004231B9317A94FF0904002F0D3F8A36D43F40013A365A36D03F400130193019BB9 +S32508004CE0D3E7FFF7DDFCD8E7005400400010024010B588B000230393049305930693079360 +S32508004D0002682F4B9A4201D008B010BD044603F560431A6E42F480521A661A6E02F480522A +S32508004D200192019ADA6C42F00102DA64DB6C03F001030293029BE023039302230493032393 +S32508004D4006930523079303A94FF0904002F092F81C481D4B03600123436000238360C36094 +S32508004D608022026143618361C361036201F096FD00BB144BA3659C621448154B0360012328 +S32508004D804360102383600023C3608022026143618361C361036201F081FD70B90B4B63653A +S32508004DA09C6200220521232001F0FAFA232001F02FFBA9E7FFF774FCDBE7FFF771FCEDE72A +S32508004DC000300140440800201C0002408C08002030000240FEE7FEE7FEE7FEE7FEE7704734 +S32508004DE008B500F0D7F806F0F7FB012800D108BD04F028FFFBE7000008B5024801F035FE5A +S32508004E0008BD00BF4408002008B5024801F02DFE08BD00BF8C08002008B5024800F0D4F975 +S32508004E2008BD00BF3807002008B5024801F081F908BD00BF9C07002008B5024801F079F95E +S32508004E4008BD00BF9C07002008B5024801F071F908BD00BF9C07002008B5024801F069F9FA +S32508004E6008BD00BF9C07002008B5024803F04AFC08BD00BF3809002008B5024801F0F5FDCE +S32508004E8008BD00BFFC07002010B503460C4A0D490D48006840B10C4800680344521A9342B1 +S32508004EA006D8094A136010BD0748084C0460F2E707F00CF80C2303604FF0FF30F3E700BFFF +S32508004EC000000120000400009C090020489C00200E4AD2F8883043F47003C2F888300C4B89 +S32508004EE01A6842F001021A60002199601A6822F0A85222F410221A604FF48052DA601A6838 +S32508004F0022F480221A609961704700BF00ED00E00010024008B50B4601461846FDF738FDE6 +S32508004F2008BD0000104B1B780BB90120704710B504464FF47A70B0FBF3F30C4A1068B0FBCE +S32508004F40F3F001F085FA68B90F2C01D901200AE0002221464FF0FF3001F022FA044B1C60E0 +S32508004F60002000E0012010BD98000020940000209C00002010B5032001F000FA0F20FFF715 +S32508004F80D1FF10B10124204610BD0446FFF732FDF9E70000034B1B78034A11680B44136062 +S32508004FA0704700BF98000020A0090020014B1868704700BFA009002038B50446FFF7F6FFBF +S32508004FC00546B4F1FF3F02D0044B1B781C44FFF7EDFF401BA042FAD338BD00BF9800002029 +S32508004FE030B583B000230193002800F0DA800446436D13B323689A6812F0005F05D09A68DD +S3250800500022F0204222F03F029A602268936813F0805F1FD1936823F0104323F03F0343F081 +S3250800502080539360604B1B689B09604AA2FB03239B0901335B00019309E0FFF7FBFC00239D +S32508005040A36584F85030D5E7019B013B0193019B002BF9D12268936813F0805F78D1636D05 +S3250800506043F010036365A36D43F00103A3650120936813F0040300D00123616D11F0100FBD +S3250800508040F08880002B40F08580636D23F4817343F002036365936813F0010F0BD1444B16 +S325080050A09B6813F0010F06D1636842498A6822F47C1213438B60627E636B43EA4233E2682E +S325080050C01343A268134394F8202043EA0243012A40D0A26A22B102F47072E16A0A431343EE +S325080050E02168CD68344A2A401A43CA6021688B6813F0040300D001238A6812F0080200D02D +S325080051000122B3B9AAB9237E94F83020520042EA8332CB6823F4804323F002031343CB6039 +S3250800512094F83830012B1AD02268136923F0010313612369012B24D02268136B23F00F03ED +S325080051401363636D23F0030343F00103636526E000208DE7626A013A43EA4243B9E7216867 +S325080051600B6923F4FF6323F00403E26B256C2A43656C2A43A56C2A43134343F001030B611A +S32508005180D7E721680B6B23F00F03E269013A13430B63D6E7636D43F010036365012003B066 +S325080051A030BD0120FBE700BF94000020632D3E05000004500003045007C0F0FF08B5806AA3 +S325080051C0FEF7A4FE08BD704770B5044603681E685D6816F0020F10D015F0020F0DD0436DEF +S325080051E013F0100F03D1436D43F400634365204600F010FD236802221A6016F0040F02D042 +S3250800520015F0040F05D116F0080F3AD015F0080F37D0636D13F0100F03D1636D43F4007308 +S3250800522063652368DA6812F4406F24D1DA6812F4005F20D11A6812F0080F1CD09A6812F0FE +S32508005240040F10D15A6822F00C025A60636D23F480736365636D13F4805F0CD1636D43F078 +S325080052600103636507E0636D43F010036365A36D43F00103A3652046FEF73EFE23680C22F0 +S325080052801A6016F0200F02D015F0200F05D116F0400F4CD015F0400F49D0636D13F0100FA5 +S325080052A003D1636D43F4005363652368DA6C12F0C00F2AD10121DA6812F4406F27D101201B +S325080052C0DA6871B312F0007F03D050B312F4005F27D1196811F0400F23D012F4001F20D1CC +S325080052E09A6812F0080F14D15A6822F060025A60636D23F480536365636D13F4807F10D177 +S32508005300636D43F0010363650BE00021D3E70020D6E7636D43F010036365A36D43F00103E8 +S32508005320A365204600F072FC236860221A6016F0800F02D015F0800F2DD116F4807F02D038 +S3250800534015F4807F32D116F4007F02D015F4007F38D116F0100F17D015F0100F14D0636B66 +S3250800536023B12368DB6813F0010F0AD0636D43F480636365A36D43F00203A3652046FEF733 +S32508005380CFFD236810221A6016F4806F02D015F4806F23D170BD636D43F480336365204630 +S325080053A0FFF711FF236880221A60C6E7636D43F400336365204600F02BFC23684FF4807246 +S325080053C01A60C0E7636D43F480236365204600F020FC23684FF400721A60BAE7636D43F458 +S325080053E080436365A36D43F00803A36523684FF480621A60204600F00AFCCBE708B5034680 +S32508005400806A426D12F0500F30D1436D43F40073436503681A6812F0080F14D0DA6812F44F +S32508005420406F20D1DB6813F4005F1CD1436D23F480734365436D13F4805F14D1436D43F068 +S32508005440010343650FE0DB6813F0020F0BD1436D23F480734365436D13F4805F03D1436DF4 +S3250800546043F001034365FEF747FD08BD426D12F0100F04D1C26C526B18469047F5E7FEF7AB +S325080054804FFDF2E708B5806A436D43F040034365836D43F004038365FEF742FD08BD000059 +S325080054A0F0B583B00022019290F85020012A00F03F820346012280F850200268926812F0C3 +S325080054C0040F09D0426D42F0200242650120002283F8502003B0F0BD4A68052A08D8023A9D +S325080054E0032A68D8DFE802F0025D60630C224A601D684C683035220A920002F00C02A85822 +S3250800550004F01F0E1F2404FA0EF420EA04000C68C4F3846C0CFA0EFC40EA0C00A8501C682E +S32508005520A26812F0040200D00122A06810F0080000D001200AB9002840D01868826812F0F0 +S32508005540010F17D10A68CD68D0F8B040C2F3120C24EA0C0405F0180CAE4D25FA0CF52A4057 +S32508005560C2F312022243C0F8B020C868AA4A904200F0B8800A68A9490A4200F0D581A84962 +S32508005580896801F0E074A748824200F07F81A648824200F0A281A548824200F0B28100206B +S325080055A095E712224A60A3E718224A60A0E74FF480724A609CE706224A6099E70E688D686F +S325080055C01434720E920002F00402A058C6F3045C072606FA0CF620EA060005FA0CF52843B0 +S325080055E0A0504C691868C268C2F3C102520094400D69042D0ED00E68603050F825708C4A72 +S325080056003A4006F0F8463443224342F0004240F8252092E7026E046EC4F384640A68C2F3E0 +S32508005620120585BBC2F38462944234D01C68626E606EC0F384600A68C2F3120585BBC2F3A4 +S325080056408462904234D01C68A26EA06EC0F384600A68C2F3120585BBC2F38462904234D058 +S325080056601C68E26EE06EC0F384600A68C2F3120585BBC2F3846290427FF45FAFE26E22F095 +S325080056800042E26659E792FAA2F212B1B2FA82F2CAE72022C8E7026E22F000420266C5E7B5 +S325080056A092FAA2F212B1B2FA82F2CAE72022C8E7626E22F000426266C5E792FAA2F212B1BC +S325080056C0B2FA82F2CAE72022C8E7A26E22F00042A266C5E792FAA2F212B1B2FA82F2CAE72E +S325080056E02022C8E71C680A68C2F31205002D3BD1900E013000F01F0009288CBF0020012015 +S32508005700002869D0002D3ED1900E0130800600F0F840002D43D14FEA926C0CF1010C0CF0E3 +S325080057201F0C012606FA0CF63043002D46D1920E013202F01F0202EB4202120510438D68DA +S3250800574004F1140E420E920002F004025EF80240C0F304500726864024EA060C85404CEA9D +S3250800576005054EF8025005E792FAA2F048B1B0FA80F0013000F01F0009288CBF002001205F +S32508005780BEE72020F5E792FAA2F030B1B0FA80F00130800600F0F840BBE72020F8E792FAF5 +S325080057A0A2F64EB1B6FA86F6013606F01F064FF0010C0CFA06F6B7E72026F5E792FAA2F298 +S325080057C042B1B2FA82F2013202F01F0202EB42021205B3E72022F6E765BB900E01308006EC +S325080057E000F0F84095BB4FEA926C0CF1010C0CF01F0C012606FA0CF63043B5BB920E0132DC +S3250800580002F01F0202EB42021E3A120542F00072104394E7FFFF070000007F400000088009 +S3250800582000030450000052C7000084CB0100008000F0FF0392FAA2F030B1B0FA80F00130DE +S32508005840800600F0F840CDE72020F8E792FAA2F64EB1B6FA86F6013606F01F064FF0010CCC +S325080058600CFA06F6C8E72026F5E792FAA2F25AB1B2FA82F2013202F01F0202EB42021E3A2D +S32508005880120542F00072C3E72022F3E711F4000F7FF47DAE1968274A914201D0002016E615 +S325080058A044F400022448816821F0E0710A438260224A126892092249A1FB02129209013250 +S325080058C002EB42029200019202E0019A013A0192019A002AF9D10020F9E511F0807F7FF419 +S325080058E05AAE1968134A914201D00020EFE544F080721148816821F0E0710A438260002003 +S32508005900E5E511F4800F11D119680A4A914201D00020DCE544F480020748816821F0E0718B +S325080059200A4382600020D2E50020D0E50020CEE50220CFE500000450000304509400002076 +S32508005940632D3E0530B583B00023019303689A6812F0010F58D1044699682D4A114219D1F0 +S325080059609A6822F0004222F03F0242F001029A60284B9B6813F4000F1CD0274B1B689B0930 +S32508005980264AA2FB03239B09013303EB43039B0001930CE0436D43F010034365836D43F0DE +S325080059A001038365012030E0019B013B0193019B002BF9D1FFF7FAFA054623681A6812F07B +S325080059C0010F1FD19A6812F0010F07D19A6822F0004222F03F0242F001029A60FFF7E6FA1F +S325080059E0431B022BE9D923681B6813F0010FE4D1636D43F010036365A36D43F00103A36549 +S32508005A00012002E0002000E0002003B030BD00BF3F0000800003045094000020632D3E0559 +S32508005A2070B504460068806810F0040F4ED10E46154694F85030012B4AD0012384F8503046 +S32508005A402046FFF77FFF00283CD1636D23F4706323F0010343F480736365636D13F4805FB0 +S32508005A602DD0A36D23F00603A365E36C194ADA62E36C194A1A63E36C184A5A6323681C2293 +S32508005A801A60002384F850302268536843F0100353602268D36843F00103D36021682B46F8 +S32508005AA032464031E06C00F07DFF2268936823F0004323F03F0343F00403936007E00023D0 +S32508005AC0A365D2E7002384F8503000E0022070BD0220FCE7FD530008BD5100088554000855 +S32508005AE038B504460268936813F0020300D00123916811F0010F39D0002B39D1936803F0CA +S32508005B000D03012B09D0636D43F010036365A36D43F00103A365012029E0936823F00043BA +S32508005B2023F03F0343F002039360236803221A60FFF73CFA054623689B6813F0010F13D0B2 +S32508005B40FFF734FA401B0228F5D923689B6813F0010FF0D0636D43F010036365A36D43F03E +S32508005B600103A365012002E0002000E0002038BD0020FCE730B583B00023019390F8503019 +S32508005B80012B41D004460D46012380F85030FFF7A7FF80BB636D23F4885323F0020343F01D +S32508005BA0020363652268936823F0404323F03F0305F080452B4343F00043936023689B687B +S32508005BC0002B06DB636D23F0030343F00103636515E0019B01330193019BB3F5912FEDD3A6 +S32508005BE0636D23F0120343F010036365002384F85030012006E0636D43F01003636500236A +S32508005C0084F8503003B030BD0220FBE770477047704770477047002800F0A18038B50446D3 +S32508005C2090F82030D3B12268136843F001031360FFF7BCF9054623685A6812F0010F10D115 +S32508005C40FFF7B4F9401B0A28F5D9636A43F400336362052384F82030012038BDFEF76AFFD4 +S32508005C60E1E71A6822F002021A60FFF79FF9054623685A6812F0020F0DD0FFF797F9401B45 +S32508005C800A28F5D9636A43F400336362052384F820300120E1E7227E012A3DD01A6822F0B1 +S32508005CA080021A60637E012B3BD02268136823F040031360A37E012B39D02268136823F086 +S32508005CC020031360E37E012B37D02268136843F010031360237F012B35D02268136823F0E3 +S32508005CE008031360637F012B33D02268136823F004031360A368E26813432269134362691E +S32508005D0013436268013A21681343CB6100206062012384F82030A0E71A6842F080021A6006 +S32508005D20C0E72268136843F040031360C2E72268136843F020031360C4E72268136823F086 +S32508005D4010031360C6E72268136843F008031360C8E72268136843F004031360CAE7012019 +S32508005D607047026890F82030013BDBB2012B05D9436A43F4802343620120704730B4D2F897 +S32508005D80003243F00103C2F800324B6903F01F03012000FA03F3D2F81C026FEA030C20EA6C +S32508005DA00300C2F81C02C869B0B9D2F80C020CEA0000C2F80C028C884869CD6844EA054459 +S32508005DC0483042F830400C8848698D6844EA0544483002EBC0004460C86901281BD08869E3 +S32508005DE080BBD2F804020CEA0000C2F80402086970BBD2F814020CEA0000C2F81402096A1F +S32508005E0001292BD0D2F8003223F00103C2F80032002030BC7047D2F80C021843C2F80C0292 +S32508005E208C8848690D6844EA0544483042F830408C8948698D6844EA0544483002EBC0002A +S32508005E404460CCE7D2F804021843C2F80402CEE7D2F814021843C2F81402D0E7D2F81C1283 +S32508005E600B43C2F81C32CDE770B5044690F82050EDB2012D06D0436A43F40023436201252E +S32508005E80284670BD022380F820300268136823F001031360FFF78AF8064623685B6813F0E8 +S32508005EA0010F0CD0FFF782F8831B0A2BF5D9636A43F400336362052384F82030E0E70025FB +S32508005EC06562DDE730B590F820C00468A4680CF1FF3C5FFA8CFCBCF1010F62D814F0E05F11 +S32508005EE059D0C4F3016C012404FA0CF41C608B68002B3DD10D68CB68046843EA45550CF1A4 +S32508005F0018031B01E55003680C690CF1180E03EB0E135C600B7D012B35D0D17993791B040B +S32508005F2043EA0163517943EA012314790168234301EB0C11C1F88C31D17893781B0443EA2C +S32508005F400163517843EA0123117802680B4302EB0C12C2F8883102680CF1180C4FEA0C1C0A +S32508005F6052F80C3043F0010342F80C3000201DE04C6843EAC403CC6823430CF11804240143 +S32508005F8005682B51BFE7036803EB0E13596841F480715960C1E7436A43F4001343620120E5 +S32508005FA004E0436A43F480234362012030BD90F820C00CF1FF3C5FFA8CFCBCF1010F00F285 +S32508005FC0958030B451B90468E46814F0030F10D1436A43F400134362012077E004682469F4 +S32508005FE014F0030F05D1436A43F40013436201206CE001F11B04240105682C5904F004047A +S325080060009460002C64D101F11B04240105682C59640D1460046801F11B0C4FEA0C1C54F8DE +S325080060200C4004F00204D46004686444646804F00F041461046864446468C4F307249461C5 +S32508006040046864446468240C5461026802EB0112D2F8B8211A70026802EB0112D2F8B821C9 +S32508006060C2F307225A70026802EB0112D2F8B821C2F307429A70026802EB0112D2F8B82148 +S32508006080120EDA70026802EB0112D2F8BC211A71026802EB0112D2F8BC21C2F307225A7132 +S325080060A0026802EB0112D2F8BC21C2F307429A71026802EB0112D2F8BC21120EDA7179B90A +S325080060C00268D36843F02003D360002030BC704701F11B04240105682C59E408546099E779 +S325080060E00268136943F020031361EEE7436A43F4802343620120704790F82030013BDBB268 +S32508006100012B05D9436A43F48023436201207047026853690B4353610020704770477047F6 +S325080061207047704770477047704770477047704770472DE9F84F054603685C69D3F80480BB +S325080061409F68D3F80CB0D3F810A0D3F8189014F001063BD017F0010616D001229A6017F087 +S32508006160020F08D117F0040F0CD117F0080606D04FF4805608E0FFF7D1FF002604E0FFF77E +S32508006180D0FF01E04FF4006617F4807F0DD02B684FF480729A6017F4007F40F0868017F424 +S325080061A0806F00F0868046F4005617F4803F0DD02B684FF480329A6017F4003F40F08380B6 +S325080061C017F4802F00F0838046F4004614F0080F07D01BF0100F04D046F400762B6810221F +S325080061E0DA6014F0040F02D01BF0080F79D114F0020F04D02B68DB6813F0030F78D114F0E1 +S32508006200400F07D01AF0100F04D046F480662B6810221A6114F0200F02D01AF0080F6BD18B +S3250800622014F0100F04D02B681B6913F0030F6AD114F4003F02D018F0100F68D114F4803FB2 +S3250800624002D018F0080F69D114F4004F7AD018F0040F74D014F4807F04D019F0010F01D040 +S3250800626046F0010614F4007F04D019F0020F01D046F0020614F4806F04D019F0040F01D097 +S3250800628046F0040614F4006F59D019F0700956D0B9F1400F65D058D8B9F1200F5ED0B9F159 +S325080062A0300F42D146F0200644E02846FFF737FF7BE717F4006F02D046F4804675E72846EC +S325080062C0FFF730FF71E72846FFF72AFF7EE717F4002F02D046F4803678E72846FFF723FF60 +S325080062E074E72B680822DA602846FFF71DFF7EE72846FDF7C3FE82E72B6808221A61284627 +S32508006300FFF714FF8CE72846FFF70FFF90E72B6810225A602846FFF70AFF8FE72B680822EB +S325080063205A602846FFF704FF8EE7B9F1100F01D146F008062A68936923F0700393612B683F +S3250800634004225A609EB9BDE8F88FB9F1500F0BD0B9F1600FEED146F48076EBE746F01006C2 +S32508006360E8E746F04006E5E746F08006E2E76B6A33436B622846FDF7A3FEE4E7074AD36801 +S3250800638023F4E0631B041B0C000200F4E060034343F0BF6343F40033D360704700ED00E05D +S325080063A000B5194BDB68C3F30223C3F1070CBCF1040F28BF4FF0040C03F1040EBEF1060F11 +S325080063C018D9033B4FF0FF3E0EFA0CFC21EA0C0199400EFA03FE22EA0E020A4300280BDB83 +S325080063E01201D2B200F1604000F5614080F800235DF804FB0023E5E700F00F001201D2B25D +S32508006400024B1A54F4E700BF00ED00E014ED00E0002807DB00F01F02400901239340024AC4 +S3250800642042F82030704700BF00E100E0BFF34F8F0549CA6802F4E062044B1343CB60BFF3C3 +S325080064404F8F00BFFDE700BF00ED00E00400FA050138B0F1807F0BD24FF0E0235861054A1E +S32508006460F02182F823100020986107221A6170470120704700ED00E0002838D010B50446F8 +S32508006480437F1BB30223637723791BBB2368194A5A612268936823F018039360637913BBF4 +S325080064A023684FF0FF321A612268936823F0600361690B4393602268936823F08003A1692D +S325080064C00B43936001236377002010BD0377FEF785FBD7E7E268A168204600F00DF80028FF +S325080064E0DCD00120F1E7236822691A61DCE70120704700BFB71DC10410B41F231C46013BC1 +S3250800650034B103F01F0C21FA0CFC1CF0010FF5D0182A22D8DFE802F00F212121212121217B +S325080065201D2121212121212119212121212121210D00062B15D80368596101688B6823F08A +S32508006540180313438B60002008E0072BF3D9012004E00F2BEFD9012000E001205DF8044BFE +S3250800656070470120FAE770B110B50446037933B102232371002020610123237110BD437131 +S32508006580FEF742FBF4E7012070474279012A2CD010B4034601224271022018711C6820688C +S325080065A001F0100C02FA0CF20243226089B919680A6802F03C02042A06D001221A710020C8 +S325080065C058715DF8044B70474A6842F001024A60F3E719680A6802F47012B2F5802FECD1A0 +S325080065E04A6842F002024A60E7E70220704710B483B0002401940068019051B901990A44B9 +S3250800660008320192019A1360002003B05DF8044B704701990A4414320192F3E7F8B543795F +S32508006620012B00F0948004460D46164601234371022303710B68042B32D02B69012B79D005 +S325080066402068C16B06F010020723934021EA03012B68AE683343EE68334393400B43C36332 +S32508006660206803684FF48041914023EA010303602068016840F6FC73934021EA03016B6885 +S3250800668093400B43036020680368C02101FA02F223EA020303600123237100206071F8BDD2 +S325080066A0FEF784FC07467EB123685B6B002B3ADAFEF77CFCC01B0128F6D9236943F0080341 +S325080066C0236103202071EAE723685B6B13F4004F0BD0FEF76BFCC01B0128F5D9236943F034 +S325080066E00803236103202071D9E70120FEF764FC2368AA691A642068836C06F0100240F246 +S32508006700FF31914023EA0103E96991400B4383642068C36CFF21914023EA0103296A9140E4 +S325080067200B43C36489E70120FEF746FC2368AA695A64E0E721688A6B06F010001F23834062 +S3250800674022EA03026B69834013438B6378E70220A5E7002800F083802DE9F04F83B08946C0 +S3250800676004460379DBB2022B7BD04379012B7AD0012141710068C56B02F010070723BB4074 +S3250800678005EA030B0568B94025EA010101602068C16B6FEA030A21EA0303C36323680193A6 +S325080067A092B9019B08330193019B4FF400621A60226813684FF4804808FA07F843EA080311 +S325080067C013600825102605E0019B14330193EBE72E446D089DB121688B6B1F22BA4023EAAB +S325080067E0020306FA07F213438B630120FEF7E4FB23685B6B38EA0303EAD1761BE9E7216836 +S325080068008B6B1F22BA40D54323EA020306FA07F213438B630120FEF7CFFB23685A6B18EAA0 +S32508006820020F06D101369A6B154006FA07F73D439D632268136823EA08031360C9F814608E +S325080068400123C9F810302268D36B0AEA030A4AEA0B03D3630020607103B0BDE8F08F0120DB +S3250800686070470120F8E70220F6E730B4446C04F01C0C012404FA0CF4056C6C600468636015 +S325080068808368102B05D0036899600368DA6030BC704703689A600368D960F8E7002873D0F0 +S325080068A010B403460068394A90424AD8384A02443849A1FB0212120992005A64364A1A647C +S325080068C0022283F82520016821F4FF4121F070019A68DC6822431C6922435C6922439C69C2 +S325080068E02243DC6922431C6A22430A4302609A68B2F5804F1BD0196C274A91422CD0264A49 +S32508006900D2F8A814586C00F01C0C0F2000FA0CF021EA0001C2F8A814D2F8A81458685C6C52 +S3250800692004F01C0C00FA0CF00143C2F8A8140020D863012283F8252083F824005DF8044BFC +S325080069407047164A02441349A1FB0212120992005A64134A1A64B3E7D2F8A810586C00F0AA +S325080069601C0C0F2000FA0CF021EA0001C2F8A810D2F8A81058685C6C04F01C0C00FA0CF022 +S325080069800143C2F8A810D2E70120704707040240F8FFFDBFCDCCCCCC00000240F8FBFDBF80 +S325080069A00004024038B5044690F82400012832D0012084F8240094F82500C0B2012804D094 +S325080069C0002384F82430022038BD022084F825000020E0632568286820F00100286020465D +S325080069E0FFF743FF236B5BB12268136843F00E0313602268136843F0010313600020E3E762 +S32508006A002268136823F0040313602268136843F00A031360EDE70220D6E708B590F82530D1 +S32508006A20DBB2022B03D00423C363012008BD0268136823F00E0313600268136823F0010310 +S32508006A401360436C03F01C03016C012202FA03F34B6080F82520002380F82430836B13B169 +S32508006A6098470020E2E70020E0E738B5036C196804682568436C03F01C0304229A400A4276 +S32508006A8015D015F0040F12D0236813F0200F03D1236823F004032360436C03F01C02016C23 +S32508006AA0042393404B60036B03B1984738BD02229A400A421CD015F0020F19D0236813F06A +S32508006AC0200F06D1236823F00A032360012380F82530436C03F01C02016C022393404B60B3 +S32508006AE0002380F82430C36A002BDFD09847DDE7082202FA03F30B42D8D015F0080FD5D01D +S32508006B00236823F00E032360436C03F01C03016C012202FA03F34B60C26380F82520002342 +S32508006B2080F82430436B002BC0D09847BEE7000010B4064C616941F0010161610260BFF3A5 +S32508006B406F8F43605DF8044B704700BF00200240094A536943F480235361EFF3108C72B6C7 +S32508006B60402351F8042B40F8042B013B13F0FF03F7D18CF31088704700200240094B5B6974 +S32508006B80002B01DB00207047064B074A9A6002F188329A605B69002B01DB00207047012003 +S32508006BA0704700BF0020024023016745034A536943F0004353610020704700BF00200240F4 +S32508006BC038B50446FEF7F2F90546144B1B6913F4803F09D0B4F1FF3FF7D0FEF7E7F9401BE9 +S32508006BE0A042F2D3032015E00C4B1B690C4A134009D10A4B1B6913F0010F0CD0074B01222D +S32508006C001A61002006E007494A681A434A60034A1361012038BD0020FCE700BF00200240E1 +S32508006C20FAC30200A00000202DE9F0411646284A1278012A49D004460D469846244B0122D7 +S32508006C401A704CF25030FFF7BBFF074608BB204B00225A601F4B1B6813F4806F1FD01D4A9E +S32508006C60136823F480631360194B02221A77D4B1631E012B1ED900244CF25030FFF7A0FF65 +S32508006C80074624B1134A536923EA0403536100F047F80F4B00221A703846BDE8F0810C4BC3 +S32508006CA000221A77E3E7324643462846FFF740FF0124E1E731462846FFF74AFF022C01D095 +S32508006CC00024D9E74FF48024D6E70227E4E700BFA00000200020024010F0010F04D0054A16 +S32508006CE0536943F004035361024A536943F480335361704700200240084B5A6922F47E7201 +S32508006D00C00000F4FF6002435A615A6942F002025A615A6942F480325A617047002002401F +S32508006D20164B1B7FDBB2012B01D0032B10D1144A116821F400711160116841F40061116063 +S32508006D40116821F400611160116841F400711160023BDBB2012B03D9084B00221A777047A6 +S32508006D60074B1A6842F480521A601A6822F480521A601A6842F480621A60EDE7A000002023 +S32508006D8000200240F8B5394B1B78012B6BD004460E46364B01221A704CF25030FFF710FFC9 +S32508006DA0074600285AD1314B00225A60304B1B6813F4007F2FD02E4B1B6813F4806F26D062 +S32508006DC02B4A136823F480631360284B03221A772368012B31D04FF0FF333360A568A3684B +S32508006DE0E2681344AB4237D961682846FFF784FF4CF25030FFF7E4FE1D4A536923F47E7376 +S32508006E0023F002035361074628BB0135E7E7174B01221A77DCE7164B1B6813F4806F08D0D9 +S32508006E20134A136823F480631360104B02221A77CEE70E4B00221A77CAE76068FFF74CFF74 +S32508006E404CF25030FFF7BCFE0746094A536923F00403536100E03560FFF762FF034B002250 +S32508006E601A703846F8BD0227FBE700BFA000002000200240F0B583B0002362E085685E00D3 +S32508006E800324B44025EA0405CC68B4402C438460456825EA0C054C68C4F300149C402C439F +S32508006EA044605FE0DD08083550F8254003F0070C4FEA8C0C4FF00F0E0EFA0CFE24EA0E0EA3 +S32508006EC00C6904FA0CF444EA0E0440F8254060E0022400E0002404FA0EF42C430CF1020C70 +S32508006EE04C4D45F82C404C4CA568D44325EA02064F6817F4801F01D042EA0506464DAE6065 +S32508006F00ED6804EA05064F6817F4001F01D042EA0506414DEE606D6804EA05064F6817F4C0 +S32508006F20003F01D042EA05063B4D6E602D682C404E6816F4803F01D042EA0504364A14602C +S32508006F4001330A6832FA03F462D04FF0010C0CFA03FC1CEA0202F3D04C6804F00304013C1E +S32508006F60012C8BD94C6804F00304032C0CD0C4685D004FF0030C0CFA05FC24EA0C0C8C68C0 +S32508006F80AC4044EA0C04C4604C6804F00304022C88D004684FEA430E4FF0030C0CFA0EFC0C +S32508006FA024EA0C0C4C6804F0030404FA0EF444EA0C0404604C6814F4403FC1D0174C256E8A +S32508006FC045F001052566246E04F001040194019C4FEA930C0CF102050E4C54F8255003F036 +S32508006FE0030E4FEA8E0E0F2404FA0EF425EA0405B0F1904F3FF46EAF094CA04206D004F57C +S325080070008064A0423FF464AF072464E7012462E703B0F0BD0000014000040140001002403A +S32508007020000400480369194201D001207047002070470AB18161704781627047436901EA2A +S32508007040030221EA030141EA024181617047002859D010B5044690F84130002B43D0242329 +S3250800706084F841302268136823F0010313606368226823F0706313612268936823F40043F8 +S325080070809360E368012B33D0A368226843F404439360E368022B31D02268536843F000730B +S325080070A043F4004353602268D36823F40043D360236962691343A169226843EA0123D3607E +S325080070C0E369216A22680B4313602268136843F00103136000206064202384F8413020633A +S325080070E084F8420010BD80F84030FDF7BDFDB6E7A368226843F400439360CAE723684FF443 +S3250800710000625A60C8E701207047034690F84120D2B2202A23D190F84020012A21D00122A3 +S3250800712080F84020242280F841200068026822F0010202601868026822F48052026018684D +S3250800714002681143016019680A6842F001020A60202283F84120002083F84000704702209E +S32508007160704702207047034690F84120D2B2202A21D190F84020012A1FD0012280F8402082 +S32508007180242280F841200068026822F0010202601868026822F4706242EA01220260196875 +S325080071A00A6842F001020A60202283F84120002083F8400070470220704702207047002826 +S325080071C02FD038B5044603684CF6CC421A60036845F255521A60036842685A60036882684F +S325080071E09A60FDF7E3FE05462368DA6812F0070F0BD0FDF7DBFE401B3128F5D92368DB688A +S3250800720013F0070FF0D0032005E01969E268914202D01A61002038BD4AF6AA221A600020D8 +S32508007220F9E70120704703684AF6AA221A60002070470000024B186800F4C060704700BF69 +S3250800724000700040B0F5007F0FD01F4B1B6803F4C063B3F5806F34D01B4A136823F4C063B1 +S3250800726043F48063136000207047174B1B6803F4C063B3F5007F20D0134A136823F4C06374 +S3250800728043F400731360114B1B68322202FB03F30F4AA2FB03239B0C013300E0013B0A4A36 +S325080072A0526912F4806F01D0002BF7D1064B5B6913F4806F03D1002070470020704703209C +S325080072C070470020704700BF007000409400002083DE1B4330B583B00446204B9B6D13F058 +S325080072E0805F0BD0FFF7A6FFB0F5007F17D0802C1FD82DD0702C2DD000211BE0174DAB6D4F +S3250800730043F08053AB65AB6D03F080530193019BFFF790FFAB6D23F08053AB65E4E7802C31 +S3250800732003D9A02C03D9022104E0002102E0012100E003210A4A136823F007030B431360DE +S32508007340136803F007038B4206D1002003B030BD0221EFE70121EDE70120F7E70010024003 +S3250800736000200240284A9368D26802F0030213F00C030AD00C2B06D0042B1FD0082B20D0C5 +S325080073800020024610E0012AF6D11F4A126812F0080F0CD11C4AD2F89420C2F303221B499A +S325080073A051F8222043B100200C2B0DD07047164A1268C2F30312F2E71046F5E71448002228 +S325080073C0F2E714480022EFE70F4BDB6803F00303022B16D0032B00D10E4A0B49CB68C3F335 +S325080073E002130133C868C0F3062002FB00F0B0FBF3F0CB68C3F3416301335B00B0FBF3F008 +S32508007400D4E7034AE9E700BF0010024058C800080024F400005A6202002800F01C83F0B51B +S3250800742083B00446964B9D6805F00C05DE6806F00306036813F0100F5AD0E5B10C2D18D022 +S32508007440A369002B00F0BB808D4A136843F001031360FDF7ABFD0746894B1B6813F0020F6C +S3250800746040F09A80FDF7A2FDC01B0228F4D90320FCE2012EE4D1824B1B6813F0020F03D033 +S32508007480A369002B00F0E982206A7D4B1B6813F0080F5BD07A4B1B6803F0F00398425CD8F6 +S325080074A0774B1A6842F008021A601A6822F0F002216A0A431A605A6822F47F42E16942EADD +S325080074C001225A60002D60D0FFF74CFF6C4B9B68C3F303136B4AD35C03F01F03D8406A4BD7 +S325080074E018606A4B1868FDF71DFD002840F0BE82236813F0010F00F08180082D75D00C2DE9 +S3250800750071D06368B3F5803F00F09780B3F5A02F00F099805A4B1A6822F480321A601A6878 +S3250800752022F480221A606368002B00F09980FDF73DFD0746524B1B6813F4003F5ED1FDF708 +S3250800754035FDC01B6428F5D903208FE24C4BD3F894301B0903F0F003A0E7FFF7BBFE002894 +S3250800756040F07D82464B1A6842F008021A601A6822F0F002216A0A431A605A6822F47F4294 +S32508007580E16942EA01225A609EE7206AFFF7A2FE002899D0012069E2394B1A6842F00802A6 +S325080075A01A601A6822F0F002216A0A431A605A6822F47F42E16942EA01225A6098E7304A86 +S325080075C0136823F001031360FDF7F0FC07462C4B1B6813F0020F8BD0FDF7E8FCC01B022825 +S325080075E0F5D9032042E2032E8BD1254B1B6813F4003F03D06368002B00F03382236813F0A6 +S32508007600020F58D0042D45D00C2D41D0E368002B77D01B4A136843F480731360FDF7C6FCA3 +S325080076200646174B1B6813F4806F61D1FDF7BEFC801B0228F5D9032018E2114A136843F478 +S32508007640803313606FE703F18043A3F53C331A6842F480221A601A6842F480321A6062E7E1 +S32508007660FDF7A4FC0746064B1B6813F4003FC5D0FDF79CFCC01B6428F5D90320F6E100BFF2 +S325080076800010024048C80008940000209C000020022EBBD1A44B1B6813F4806F03D0E368C0 +S325080076A0002B00F0E081A04A536823F0F853216943EA01635360236813F0080F4CD06369E2 +S325080076C09BB3994AD2F8943043F00103C2F89430FDF76CFC0646944BD3F8943013F0020FFE +S325080076E03AD1FDF763FC801B0228F4D90320BDE18D4A536823F0F853216943EA016353600D +S32508007700D9E7894A136823F480731360FDF74EFC0646854B1B6813F4806FCCD0FDF746FC2B +S32508007720801B0228F5D90320A0E17F4AD2F8943023F00103C2F89430FDF738FC06467A4BDF +S32508007740D3F8943013F0020F06D0FDF72FFC801B0228F4D9032089E1236813F0040F7AD079 +S32508007760714B9B6D13F0805F36D16F4B9A6D42F080529A659B6D03F080530193019B012665 +S325080077806A4B1B6813F4807F28D0A368012B39D0052B3FD0644BD3F8902022F00102C3F82C +S325080077A09020D3F8902022F00402C3F89020A368002B3DD0FDF7FAFB07465B4BD3F8903063 +S325080077C013F0020F46D1FDF7F1FBC01B41F288339842F2D9032049E10026D1E7534A1368DF +S325080077E043F480731360FDF7E1FB07464F4B1B6813F4807FC9D1FDF7D9FBC01B0228F5D969 +S32508007800032033E1484AD2F8903043F00103C2F89030CCE7444BD3F8902042F00402C3F8A6 +S325080078209020D3F8902042F00102C3F89020BEE7FDF7BCFB07463C4BD3F8903013F0020FAC +S3250800784008D0FDF7B3FBC01B41F288339842F2D903200BE1E6B9236813F0200F35D0636AF5 +S32508007860E3B1314AD2F8983043F00103C2F89830FDF79CFB06462C4BD3F8983013F0020FAB +S3250800788023D1FDF793FB801B0228F4D90320EDE0254A936D23F080539365DCE7224AD2F89C +S325080078A0983023F00103C2F89830FDF77FFB06461D4BD3F8983013F0020F06D0FDF776FB55 +S325080078C0801B0228F4D90320D0E0A36A002B00F0CC80022B17D00C2D00F0CC80124A136861 +S325080078E023F080731360FDF761FB04460E4B1B6813F0007F00F0A880FDF758FB001B022865 +S32508007900F4D90320B2E0084BDB6803F00301E26A91420DD00C2D00F0AB80034B1B6813F026 +S32508007920806F2FD00120A1E0001002400070004003F07002216B0139B2EB011FEAD103F40D +S32508007940FE42616BB2EB012FE4D103F07842A16BB2EBC16FDED103F4C001E26B5208013ABC +S32508007960B1EB425FD6D103F0C063226C5208013AB3EB426FCED1404B1B6813F0007F49D045 +S32508007980002073E03C4A136823F080731360FDF70DFB0546384B1B6813F0007F06D0FDF753 +S325080079A005FB401B0228F5D903205FE0324AD36832491940E36A206B013843EA0013606B5D +S325080079C043EA0023E06B4008013843EA4053206C4008013843EA4063A06B43EAC063194329 +S325080079E0D160136843F080731360D36843F08073D360FDF7DBFA04461F4B1B6813F0007F1E +S32508007A0006D1FDF7D3FA001B0228F5D903202DE000202BE0184B1A6842F080721A60DA688D +S32508007A2042F08072DA60FDF7C1FA0446124B1B6813F0007F06D1FDF7B9FA031B022BF5D9E8 +S32508007A40032013E0002011E00B4AD1680C4B0B40D36000200AE001207047012006E0012084 +S32508007A6004E0012002E0012000E0002003B0F0BD0120FBE70120F9E7001002408C809D0190 +S32508007A80FCFFEEFE002800F0AF8070B50D460446594B1B6803F007038B420BD2564A1368FF +S32508007AA023F007030B431360136803F007038B4240F09C80236813F0020F0CD0A2684F4B2A +S32508007AC09B6803F0F0039A4205D94C498B6823F0F0031A438A60236813F0010F39D06368AE +S32508007AE0032B09D0022B26D063BB444A126812F0020F06D1012076E0404A126812F0007F42 +S32508007B0076D03E498A6822F0030213438B60FDF74DFA0646394B9B6803F00C036268B3EBC8 +S32508007B20820F16D0FDF742FA801B41F288339842F0D9032057E0314A126812F4003FE0D11F +S32508007B40012050E02D4A126812F4806FD9D1012049E0236813F0020F0CD0A268274B9B68F2 +S32508007B6003F0F0039A4205D224498B6823F0F0031A438A60204B1B6803F00703AB420AD9F6 +S32508007B801D4A136823F007032B431360136803F00703AB422ED1236813F0040F06D0174ABB +S32508007BA0936823F4E063E1680B439360236813F0080F07D0114A936823F46053216943EA85 +S32508007BC0C1039360FFF7CEFB0C4B9B68C3F303130B4AD35C03F01F03D8400A4B18600A4B28 +S32508007BE01868FDF79FF970BD012070470120FAE70120F8E70120F6E70020024000100240B2 +S32508007C0048C80008940000209C000020F8B504460F46584BDB6813F0030F18D0554BDB68BC +S32508007C2003F003030268934202D001252846F8BD002A00F09D804F4BDB68C3F302130133D0 +S32508007C404268934201D00125F0E7002509E00368022B56D0032B5BD0012B41D00125002D14 +S32508007C60E4D1444A136823F080631360FDF79EF90646404B1B6813F0006F05D0FDF796F920 +S32508007C80831B022BF5D90325002DCFD1002F4DD138490B6923F0784323F4FE43A068E2688E +S32508007CA0D20642EA002213430B61324A136843F080631360FDF77AF906462E4B1B6813F09C +S32508007CC0006F05D1FDF772F9831B022BF5D90325002DABD1274A1369A1690B431361A5E743 +S32508007CE0244A126812F0020F1ED02248C26822F073026168013943EA01131343C360002590 +S32508007D00ADE71C4A126812F4806FEED10125A6E7184A126812F4003FE7D1164A126812F4C1 +S32508007D20802FE2D101259AE7012598E7012F0FD01048026922F0C06222F4FE42A168636956 +S32508007D405B08013B5B0643EA01231A430261ACE70848026922F4C00222F4FE42A1682369F3 +S32508007D605B08013B5B0543EA01231A4302619CE701255BE7001002402DE9F04182B00446E5 +S32508007D80036813F4006F25D0C36BB3F5000F06D0B3F5400F12D04BB1012637461CE0AE4AD7 +S32508007DA0D36843F48033D360002708E000210430FFF72CFF074610B106460DE00027A64A7A +S32508007DC0D2F8883023F44003E16B0B43C2F88830002601E000263746236813F4003F6BD0F7 +S32508007DE09D4B9B6D13F0805F4CD19B4B9A6D42F080529A659B6D03F080530193019B4FF059 +S32508007E000108964A136843F480731360FDF7CEF80546924B1B6813F4807F05D1FDF7C6F860 +S32508007E20401B0228F5D90327002F40D18A4BD3F8903013F4407315D0226D9A4212D0864A5B +S32508007E40D2F8903023F44073D2F8901041F48031C2F89010D2F8901021F48031C2F890108C +S32508007E60C2F8903013F0010F0FD1002F40F0C980794AD2F8903023F44073216D0B43C2F832 +S32508007E80903015E04FF00008BBE7FDF78FF80546714BD3F8903013F0020FE6D1FDF786F8EC +S32508007EA0401B41F288339842F2D90327DDE73E46B8F1000F40F0A780236813F0010F08D0CF +S32508007EC0654AD2F8883023F00303216A0B43C2F88830236813F0020F08D05F4AD2F888305D +S32508007EE023F00C03616A0B43C2F88830236813F0200F08D0584AD2F8883023F44063A16A49 +S32508007F000B43C2F88830236813F4007F08D0524AD2F8883023F44023616B0B43C2F8883086 +S32508007F20236813F4806F08D04B4AD2F8883023F44013A16B0B43C2F88830236813F0400FB0 +S32508007F4008D0454AD2F8883023F44053E16A0B43C2F88830236813F4807F08D03E4AD2F8BA +S32508007F60883023F44033216B0B43C2F88830236813F4005F0FD0384AD2F8883023F04063DB +S32508007F80216C0B43C2F88830236CB3F1006F40D0B3F1806F42D0236813F4802F0FD02E4A97 +S32508007FA0D2F8883023F04063616C0B43C2F88830636CB3F1006F39D0B3F1806F3BD02368DA +S32508007FC013F4804F0CD0244AD2F8883023F04053A16C0B43C2F88830A36CB3F1805F32D0EA +S32508007FE0236813F4004F08D01B4AD2F8883023F08043E16C0B43C2F88830304602B0BDE823 +S32508008000F0813E4654E7144A936D23F08053936552E7D36843F48013D360BCE70121201D73 +S32508008020FFF7F4FD0028B6D00646B4E7D36843F48013D360C3E70121201DFFF7E7FD002873 +S32508008040BDD00646BBE70221201DFFF7DFFD0028C6D00646C4E700BF0010024000700040EF +S325080080602DE9F04782B00546884617461E46FCF79DFF0A9B1B1A03EB0609FCF797FF8246E2 +S325080080802A4B1B68C3F3CB3309FB03F301932B689C6838EA04040CBF01230023BB4240D0B8 +S325080080A0B6F1FF3FF3D0FCF781FFA0EB0A0048450AD2B9F1000F07D0019A02B14A46019B8F +S325080080C0013B01939146E2E72A68536823F0E00353606B68B3F5827F0BD0AB6AB3F5005FB9 +S325080080E014D0012385F85D30002385F85C30032018E0AB68B3F5004F02D0B3F5806FECD1E9 +S325080081002A68136823F040031360E6E72A68136823F4005313602A68136843F400531360BA +S32508008120DFE7002002B0BDE8F08700BF940000202DE9F04782B006460C4615461F4600230A +S325080081408DF80330FCF732FF0A9B1B1A03EB0708FCF72CFF8146D6F800A0314B1B6803EB1E +S325080081608303C3EBC3031B0D08FB03F3019302E0B7F1FF3F12D133689B6803EA040CAC450B +S325080081804AD0B4F5C06FF3D1002DF1D19AF80C30DBB28DF803309DF80330E9E7FCF706FF89 +S325080081A0A0EB090040450AD2B8F1000F07D0019A02B14246019B013B01939046DBE73268B9 +S325080081C0536823F0E00353607368B3F5827F0BD0B36AB3F5005F14D0012386F85D30002374 +S325080081E086F85C30032018E0B368B3F5004F02D0B3F5806FECD13268136823F04003136036 +S32508008200E6E73268136823F4005313603268136843F400531360DFE7002002B0BDE8F087CB +S325080082209400002070B582B004460D46164600920B4600224FF4C051FFF77AFFB0B9009665 +S325080082402B46002280212046FFF70AFFA8B900962B4600224FF4C0612046FFF769FF50B1C4 +S32508008260236E43F020032366032004E0236E43F020032366032002B070BD236E43F0200320 +S3250800828023660320F7E770B582B004460D4616464368B3F5827F0DD000962B4600228021FB +S325080082A02046FFF7DDFE90B96368B3F5827F14D002B070BD8368B3F5004F02D0B3F5806FAE +S325080082C0EAD12268136823F040031360E4E7236E43F0200323660320EAE7A368B3F5004FD6 +S325080082E002D0B3F5806FE3D100962B4600224FF4C0612046FFF71CFF0028D9D0236E43F0BA +S32508008300200323660320D3E700286AD010B50446436A33B94368B3F5827F05D00023C3614C +S3250800832002E00023036143610023A36294F85D30002B4DD0022384F85D302268136823F053 +S3250800834040031360E368B3F5E06F47D90022B3F5706F04D0B3F5E06F01D00023A3626368BF +S3250800836003F48273A16801F404410B43216901F002010B43616901F001010B43A16901F49C +S3250800838000710B43E16901F038010B43216A01F080010B43A16A01F4005120680B43036079 +S325080083A0638B03F00403616A01F010010B43616B01F008010B43E16801F470610B432168B2 +S325080083C01A434A6000202066012384F85D3010BD84F85C302046FCF78BFCABE74FF4805259 +S325080083E0B5E701207047000038B5044690F85C00012800F0F780012084F85C0094F85D006E +S32508008400C0B2656801280AD0B5F5827F40F0DB80A568002D40F0DC80042840F0DB80002930 +S3250800842000F0DA80002A00F0D980002B00F0D88094F85D00C0B2042802D0052084F85D00A7 +S3250800844000202066A163A387E3872264A4F84430A4F84630E06420652268536823F4C04300 +S325080084605360E368B3F5E06F28D92268536823F48053536094F85D30DBB2042B69D0A36DF8 +S32508008480594A1A63A36D594ADA62A36D584A5A63A36D00229A632168B4F846309BB2226C9B +S325080084A00C31A06DFEF77EFA002859D0236E43F010032366012084F85D0085E022685368A2 +S325080084C043F480535360636D9B69B3F5806F1AD0A36D9B69B3F5806FCCD12268536823F4D8 +S325080084E080535360B4F8463013F0010F24D12268536823F400535360B4F84630C3F34E0333 +S32508008500A4F84630B6E7A38F13F0010F09D12268536823F480435360E38FC3F34E03E387CA +S32508008520D6E72268536843F480435360E38FC3F34E030133E387CBE72268536843F40053E6 +S325080085405360B4F84630C3F34E030133A4F8463090E7A36D274A1A63A36D274ADA6294E73E +S325080085602268536843F001035360626D00231363626DD362626D5363626D93632268E38F0C +S325080085809BB20C32A16B606DFEF70CFA98B923681A6812F0400F03D11A6842F040021A607B +S325080085A02268536843F0200353602268536843F00203536008E0236E43F0100323660120C6 +S325080085C084F85D0000E00220002384F85C3038BD0220F9E70220F7E70120F5E70120F3E798 +S325080085E00120F1E70220F2E70B860008A786000815860008FF85000837860008704708B543 +S32508008600806AFFF7FBFF08BD704708B5806AFFF7FBFF08BD08B5806A0268536823F00303B5 +S325080086205360036E43F010030366012380F85D30FBF792FE08BD38B50546846AFCF7B6FC1E +S325080086402B681B6813F0200F1FD1024621684B6823F020034B60A3681BB96368B3F5827F1C +S3250800866017D021684B6823F001034B6064212046FFF709FE08B1202323660023A4F8463065 +S32508008680012384F85D30236E4BB92046FBF752FE38BD21684B6823F003034B60E6E720463A +S325080086A0FBF75AFEF4E738B50546846AFCF77EFC2B681B6813F0200F1CD1024621684B683B +S325080086C023F020034B6064212046FFF7ABFD18B1236E43F0200323662268536823F003038B +S325080086E053600023E387A4F84630012384F85D30236E1BB92046FBF70BFE38BD2046FBF7DA +S325080087002BFEFAE710B584B0044602685168936803F04100012867D013F0020F02D011F065 +S32508008720800F68D113F4B07F68D011F0200F65D013F0400F0FD094F85D00C0B203285FD0AA +S32508008740206E40F00400206600200090D068009090680090009813F0200F0CD0206E40F05F +S32508008760010020660020029090680290106820F040001060029A13F4807F09D0236E43F0B1 +S32508008780080323660023039323689B680393039B236E002B32D02268536823F0E003536010 +S325080087A0012384F85D3011F0030F31D02268536823F003035360A36D4BB1174A9A63A06DE2 +S325080087C0FEF72BF918B1236E43F040032366636DA3B1114A9A63606DFEF71FF970B1236E11 +S325080087E043F04003236609E011F0400F94D0E36C2046984702E0236D2046984704B010BD03 +S3250800880000230193D368019393680193019BF5E72046FBF7A1FDF1E71D88000808B5806A9B +S325080088200023A0F84630C387FBF796FD08BD2DE9F003D0E90089D0E90267D0E90445D0E93D +S325080088400623B3F1FF3F08BFB2F1FF3F13D1B5F1FF3F08BFB4F1FF3F11D1B7F1FF3F08BF56 +S32508008860B6F1FF3F0DD1B9F1FF3F08BFB8F1FF3F09D1002000E00420BDE8F0037047032021 +S32508008880FAE70220F8E70120F6E7000038B5044600F5803C4FEACC2C284BD3F8E02590B24C +S325080088A04FF6FF73984215D0254B03EA82234FF4F832B2FBF3F203FB02CC0CF108050CF160 +S325080088C010000CF1180E0139032931D8DFE801F005101B254FF48023E9E74FF0AA324FF0CB +S325080088E0AA33604600F0A6FB20BB164B1C7038BD4FF0AA324FF0AA33284600F09BFBD8B9DD +S32508008900104B1C70F3E74FF0AA324FF0AA3300F091FB0028EBD00220E9E74FF0AA324FF0A6 +S32508008920AA33704600F086FB0028E0D00220DEE70020DCE70220DAE70220D8E70070FF1F31 +S3250800894000FCFF03A409002010B5274BD3F8E02591B24FF6FF7399420CD0244B03EA822385 +S325080089604FF4F834B4FBF3F403FB04F4C4F5F834E40A2BE04FF48023F2E70121204600F0D9 +S325080089805FFB044608B101242CE000F06BFB29E0164A02EA83224FF4F833B3FBF2F302FBED +S325080089A003F3C3F5F833DB0A0233A34219D904F580304FF4F833B3FBF2F302FB03F303EB54 +S325080089C0C020FFF734FF0428D7D00134064BD3F8E03599B24FF6FF729142D9D14FF48022E4 +S325080089E0D9E70524204610BD0070FF1F00FCFF03F8B50646614B1D7805F58032D202604B5C +S32508008A00D3F8E01588B24FF6FF7398424FD05D4B03EA81234FF4F830B0FBF3F003FB00204E +S32508008A20FFF705FF0746564BD3F8E03599B24FF6FF7291423ED0534A02EA83224FF4F833E2 +S32508008A40B3FBF2F302FB03F3C3F5F832A5EBD224013404F0010404EBD22404F5803003EB70 +S32508008A60C020FFF7E4FE464BD3F8E03599B24FF6FF72914221D0434A02EA83224FF4F8336E +S32508008A80B3FBF2F302FB03F3C3F5F833A5EBD322013202F0010202EBD322012E10D0022E91 +S32508008AA057D0002E4CD04FF0FF352846F8BD4FF48023AFE74FF48022C0E74FF48022DDE7F0 +S32508008AC0022F19D0012F4DD12F4B1B68B3F5006FEBD304282DD003212846FFF7D7FE0028A0 +S32508008AE043D101212046FFF7D1FE002840D1264B20221A602546D8E7234B1B68B3F5006F6F +S32508008B00D3D304280ED003212846FFF7BFFE18BB02212046FFF7BAFE08BB1B4B20221A6063 +S32508008B202546C2E7FFF710FF0028ECD04FF0FF35BBE7FFF709FF0028CDD04FF0FF35B4E744 +S32508008B40022FB2D0012F02D04FF0FF35ADE71546ABE780B92546A8E74FF0FF35A5E74FF0ED +S32508008B60FF35A2E74FF0FF359FE74FF0FF359CE74FF0FF3599E74FF0FF3596E7A40900208B +S32508008B800070FF1F00FCFF03C0000020044B9A6842F001029A6018601980186880B2704761 +S32508008BA0003002402DE9F84F80468A460020FFF71FFFB0F1FF3F63D0814600F58037FF0288 +S32508008BC0304BD3F8E02591B24FF6FF7399420CD02D4B03EA82234FF4F832B2FBF3F203FB84 +S32508008BE002773846FFF723FE3EE04FF48023F2E7083E1F2E16D9BB19D3E90045B5F1FF3F41 +S32508008C0008BFB4F1FF3FF3D0A1B24145F0D12846FFF7BCFFB0EB144FEAD1CAF80050002035 +S32508008C20BDE8F88F174BD3F8E02591B24FF6FF73994220D0144B03EA82234FF4F837B7FBEE +S32508008C40F3F703FB07F7C7F5F833A9EBD32909F1010909F0010909EBD32909F5803307EB0F +S32508008C60C3273846FFF7E3FD0238C0B2022805D84FF4FF66BDE74FF48023DEE70720CFE721 +S32508008C800320CDE70070FF1F00FCFF03431E9BB24FF6FD72934201D90820704710B582B07C +S32508008CA00C460023019301A9FFF77CFF019B236002B010BD214B1B88FB2B39D870B506462D +S32508008CC00D460120FFF794FEB0F1FF3F32D000F58034E4021A4BD3F8E02591B24FF6FF73EB +S32508008CE0994220D0174B03EA82234FF4F832B2FBF3F203FB024405B9C6B131462846FFF754 +S32508008D0045FF114B196846EA00422B46601800F091F988B90C4A136808331360074A1388A3 +S32508008D200133138070BD4FF48023DEE72846E8E7122070470320F5E70220F3E7A609002096 +S32508008D400070FF1F00FCFF03C0000020F0B583B005460E46002301931746002A4CD10220A5 +S32508008D60FFF746FE0446B0F1FF3F00F034819F4B00221A809E4B18709E4B20221A60002FF2 +S32508008D803CD09D4BD3F8E03599B24FF6FF7291423BD09A4A02EA83224FF4F833B3FBF2F39C +S32508008DA002FB03F3C3F5F832A4EBD224013404F0010404EBD22404F5803003EBC020FFF7CB +S32508008DC036FD022824D0042822D0012F40F00581032840F00481012F00F0A6803146284625 +S32508008DE0FFF768FF002840F0FC80804B1C88022C40F2E480023CD2E00120B1E70121FFF740 +S32508008E0045FD0028BDD00223E2E04FF48022C3E7022820D0784BD3F8E03599B24FF6FF7219 +S32508008E20914220D0754A02EA83224FF4F833B3FBF2F302FB03F3C3F5F832A4EBD224013481 +S32508008E4004F0010404EBD22404F5803003EBC020FFF7EDFC28E004212046FFF717FD00280B +S32508008E60D8D00223B4E04FF48022DEE704212046FFF70CFDF0B10223AAE04FF480224FF4D7 +S32508008E80F833B3FBF2F302FB03F3C3F5F832A4EBD224013404F0010404EBD22404F58030F0 +S32508008EA003EBC020FFF7C3FCC31EDBB2012B92D80328DBD0504BD3F8E03599B24FF6FF72CB +S32508008EC09142DAD04D4A02EA8322D8E74FF480224FF4F831B1FBF2F102FB01330344D3E90C +S32508008EE00023B3F1FF3F08BFB2F1FF3F1ED03F4A1388013313803F4A1368083313600830F4 +S32508008F00B0F5006F12D23A4B1B7803F58033DB02394AD2F8E0158CB24FF6FF729442D5D0FA +S32508008F20364A02EA8122D3E72020E9E7304B1C7800271EE04FF480224FF4F833B3FBF2F330 +S32508008F4002FB03F3C3F5F832A4EBD224013404F0010404EBD22404F5803003EBC020FFF729 +S32508008F6066FC03287FF43AAF204A1388FC3313800137012F3FF632AF1F4BD3F8E03599B220 +S32508008F804FF6FF729142D5D01C4A02EA8322D3E701993046FFF78EFE0346C8B90134062C21 +S32508008FA00ED8A542FAD0A6B201A93046FFF7FAFD03460028ECD00728F0D009E00124EEE7A8 +S32508008FC002210B4B1878FFF761FC60B94FF48073184603B0F0BD0423FAE70A23F8E70A23D9 +S32508008FE0F6E70223F4E70223F2E700BFA6090020A4090020C00000200070FF1F00FCFF03C1 +S3250800900038B504460D46FFF755FE122800D038BD002229462046FFF799FEF8E708B5431EEF +S325080090209BB24FF6FD72934201D9082008BDFFF7E7FFFBE708B501460020FDF7F5FD08BDF8 +S3250800904000B587B0002301930293059104900123039301A902A8FDF795FE00B1012007B082 +S325080090605DF804FB084B1A6822F480621A601A6842F480521A601A6822F480521A601A68DD +S3250800908042F480621A6070470020024008B502F046FE10B102684068904708BDEFF305834B +S325080090A02BB9064B186828B901221A6070476FF0050070474FF0FF30704700BF280D002064 +S325080090C0EFF3058373B90A4B1B68012B0DD110B50024084BDC77064B02221A6001F0F4FEA9 +S325080090E0204610BD6FF0050070474FF0FF307047280D002000ED00E008B5EFF3058343B9AA +S3250800910002F06AFA40B1022808D101F033FF002006E06FF0050003E0012001E04FF0FF3017 +S3250800912008BDF0B587B000240594EFF305847CBB70B32AB31568936903B918235C1E372CD4 +S325080091404AD8546814F0010F48D1566976B14FEA960C946834B1D768B7F5C07F02D31769D5 +S3250800916007B1C6B92CB14FF0FF340EE04FF0800CEFE7D4688CB9146994B14FF0FF3404E033 +S325080091801546002418234FF0800C012C0AD0ACB1059807B0F0BD0124F7E74FF0FF34F4E787 +S325080091A00024F2E7146992680292019400930B466246294601F016FE0590E9E705AA01925D +S325080091C000930B461FFA8CF2294601F048FE0128DED000230593DBE70020DAE70020D8E74C +S325080091E008B5EFF3058323B930B102F04FF8002008BD6FF00500FBE76FF00300F8E708B51B +S32508009200EFF3058333B908B9002008BD01F0C8FF0020FAE76FF00500F7E700002DE9F04300 +S3250800922083B0EFF30587002F43D10646894615461C4600283FD0082000F04CFE80460028DD +S325080092403BD006604560B9F1000F00D0012704B32068A36813B1E2682B2A10D853B14FF061 +S32508009260FF33DBB10024404600F0B2FE204603B0BDE8F083E3687BB14FF0FF33F1E7019353 +S325080092800F4B009343463A46012102F093FB04460CE020460023E4E70023E2E7084B0093CC +S325080092A043463A46012102F069FB0446002CDDD1D9E70024DAE70024D8E70446D6E700BFAD +S325080092C08D900008EFF305836BB90A4670B100B583B00093042102F097FB012809D1002015 +S325080092E003B05DF804FB6FF0050070476FF0030070476FF00200F3E708B5EFF30583CBB93F +S32508009300A0B1836813B1C2681F2A0BD82BB14FF0FF338BB900F04EFA08BDC36843B14FF0FD +S32508009320FF33F6E7184600F020FAF5E70023F0E70023EEE70020EFE70020EDE7F8B110B582 +S3250800934082B00C4611F07F4F1CD1EFF305829AB10022019201AA00F049FBB8B1019BC3B1FE +S325080093604FF0E0234FF08052C3F8042DBFF34F8FBFF36F8F204607E000F0EEFA04E06FF0F8 +S32508009380030070476FF0030002B010BD6FF00200FAE72046F8E770B5B0B10C46064611F078 +S325080093A07F4F14D1EFF3058353B100F0C7FA05462146304600F0B8FA58B96FF0020508E0A4 +S325080093C000F08AFA054604E06FF0030501E06FF00305284670BD40B370B582B00C461D4693 +S325080093E0844611F07F4F23D1EFF3058323BB12F0010610D0012312F0020F0ED000220095D5 +S325080094002146604600F0E4F94EB1844312D0B5B16FF001000EE00023EDE70122EFE70442D2 +S3250800942008D17DB16FF0010004E06FF0030070476FF0030002B070BD6FF00500FAE76FF0D5 +S325080094400200F7E76FF00200F4E770B5EFF30583002B3FD1044600B1436813F0010600D098 +S32508009460012613F0080F38D14CB3A16811B1E3684F2B19D899B14FF0FF334BBB1EB304205E +S3250800948001F01DF805462DB104B124682146284601F0B0FAFDB1F6B145F001051BE0E36808 +S325080094A07BB14FF0FF33E8E726B1042001F012F80546E8E7012001F00DF80546E3E70023D3 +S325080094C0DBE70023D9E7012000F0F9FF0546DAE70025DFE70025284670BD0025FBE7EFF330 +S325080094E00582C2B910B503460C4620F0010003F0010398B13BB101F005FA012811D094B180 +S325080095006FF001000EE001F02AF901280ED07CB16FF0010006E06FF0050070476FF00300E4 +S3250800952000E0002010BD6FF00200FBE70020F9E76FF00200F6E7EFF30582B2B908B50346F5 +S3250800954020F0010003F0010390B12BB100F0D1FF012810D1002008BD00231A46194600F057 +S32508009560DEFE01280AD10020F5E76FF0050070476FF00300EFE76FF00200ECE76FF0020019 +S32508009580E9E770B582B0EFF30583002B3AD1144600283BD000293BD06AB393684BB1D268E7 +S325080095A04F2A06D9226922B101FB00F56669AE421BD273B14FF0FF3363BB002200F08BFEFC +S325080095C0054605B304B124682146284601F012FA19E0E3688BB9236913B14FF0FF33EBE74C +S325080095E063696BB14FF0FF33E6E70025009500F028FE0546E5E70023DEE74FF0FF33DBE735 +S325080096000023D9E70025284602B070BD0025FAE70025F8E70025F6E710B582B01C46EFF3A0 +S325080096200583C3B118B329B33CBB0023019301AA00F07FFF012823D1019850B14FF0E023B9 +S325080096404FF08052C3F8042DBFF34F8FBFF36F8F002002B010BDB0B1C1B10023224600F0D2 +S325080096605EFE012815D0B4B16FF00100F1E76FF00300EEE76FF00300EBE76FF00300E8E739 +S325080096806FF00200E5E76FF00300E2E76FF00300DFE70020DDE76FF00200DAE710B582B03F +S325080096A01C46EFF30583C3B110B321B334BB0023019301AA01F046F9012822D1019850B18E +S325080096C04FF0E0234FF08052C3F8042DBFF34F8FBFF36F8F002002B010BDA8B1B9B1224633 +S325080096E000F08EFF012815D0B4B16FF00100F2E76FF00300EFE76FF00300ECE76FF0030064 +S32508009700E9E76FF00200E6E76FF00300E3E76FF00300E0E70020DEE76FF00200DBE70000E0 +S32508009720034B0360034B0B6080231360704700BFA80B0020A8090020034B0360034B0B6017 +S325080097404FF4807313607047301100202C0D00201AB9084205D110467047814303D000202A +S325080097607047012070470120704780B110B582B0044620230193019B202B11D04FF05003D1 +S3250800978083F31188BFF36F8FBFF34F8FFEE74FF0500383F31188BFF36F8FBFF34F8FFEE7C1 +S325080097A0002340F8043B00F02BF901232377204602B010BD38B5202000F08CFB044628B183 +S325080097C0002540F8045B00F01BF92577204638BD2DE9F84378B10C4616461D46074611F0EB +S325080097E07F4811D04FF0500383F31188BFF36F8FBFF34F8FFEE74FF0500383F31188BFF39A +S325080098006F8FBFF34F8FFEE741B94FF0500383F31188BFF36F8FBFF34F8FFEE701F0DCFE3C +S3250800982050B9089B43B14FF0500383F31188BFF36F8FBFF34F8FFEE701F09CFBD7F80090CD +S325080098402A4621464846FFF783FFF0B116B129EA04033B6001F028FCB8F1000F12D048B950 +S325080098604FF0E0234FF08052C3F8042DBFF34F8FBFF36F8F01F0A4FF814610F0007F1AD097 +S3250800988029F07F494846BDE8F883089B83B166B941460DB141F08061089A2143381D01F092 +S325080098A06FFDC146DDF82080D4E74FF08071F0E7DDF82080CEE700F055F9D7F800902A46B9 +S325080098C021464846FFF744FF18B116B129EA04043C6000F069F9D3E770B170B50C46054616 +S325080098E011F07F4F11D04FF0500383F31188BFF36F8FBFF34F8FFEE74FF0500383F3118843 +S32508009900BFF36F8FBFF34F8FFEE700F02BF92E6826EA04042C6000F047F9304670BD08B536 +S32508009920FFF7DAFF08BD000008B50A4600230146014802F007FA08BD1F990008EFF31183D7 +S325080099404FF0500282F31188BFF36F8FBFF34F8F006883F311887047F8B568B10D46044689 +S3250800996011F07F4711D04FF0500383F31188BFF36F8FBFF34F8FFEE74FF0500383F31188CA +S32508009980BFF36F8FBFF34F8FFEE700F10C0601F0F1FA206923682B4323600AE0216832EA21 +S325080099A0010105D111E0216841F0007101F076FD2846B0420ED04568036823F07F4213F014 +S325080099C0806FEBD121681142F2D013F0807FEAD01743E8E7236823EA0703236001F064FBD6 +S325080099E02068F8BD08B5FFF7B7FF08BD08B513460A460146014802F0A5F908BDE59900081D +S32508009A0000F1080343604FF0FF328260C360036100230360704700230361704743684B60EF +S32508009A209A688A60516099600861036801330360704730B40D68B5F1FF3F11D000F1080346 +S32508009A401C465B681A68AA42FAD963684B6099608C606160086103680133036030BC704768 +S32508009A600469F2E70369416882688A60416851605A68824206D0002202611A68013A1A6037 +S32508009A801868704782685A60F5E7000082B0002301930D4B1B68B3F1FF3F08D04FF05003F1 +S32508009AA083F31188BFF36F8FBFF34F8FFEE74FF0500383F31188BFF36F8FBFF34F8F019BE7 +S32508009AC0002BFCD002B07047C400002008480068006880F308884FF0000080F3148862B6AB +S32508009AE061B6BFF34F8FBFF36F8F00DF00BF000008ED00E0DFF80C00016841F4700101603B +S32508009B007047000088ED00E04FF0807340F8043C21F0010140F8081C054B40F80C3C40F80A +S32508009B20202C6FF0020340F8243C4438704700BF8D9A0008000000000000000000000000AE +S32508009B40074B19680868B0E8F04F80F30988BFF36F8F4FF0000080F311887047AFF3008005 +S32508009B60189300204FF0500383F31188BFF36F8FBFF34F8F0B4A136801331360012B00D0B8 +S32508009B8070474FF0E023D3F8043D13F0FF0FF7D04FF0500383F31188BFF36F8FBFF34F8FF9 +S32508009BA0FEE700BFC4000020094B1B6843B94FF0500383F31188BFF36F8FBFF34F8FFEE776 +S32508009BC0013B034A13600BB983F31188704700BFC40000200000000000000000000000004E +S32508009BE0EFF30980BFF36F8F154B1A681EF0100F08BF20ED108A20E9F04F10602DE90900E8 +S32508009C004FF0500080F31188BFF34F8FBFF36F8F01F0ECFA4FF0000080F3118809BC1968F3 +S32508009C200868B0E8F04F1EF0100F08BFB0EC108A80F30988BFF36F8F704700BFAFF3008059 +S32508009C401893002008B54FF0500383F31188BFF36F8FBFF34F8F01F09BF928B14FF0E023ED +S32508009C604FF08052C3F8042D002383F3118808BD4FF0E022002313619361054B1B680549F5 +S32508009C80A1FB03139B09013B536107231361704794000020D34D62104FF0E023D3F8002D9B +S32508009CA03D4B9A421CD04FF0E023D3F8002D3B4B9A421ED030B583B0394B1A78D2B2019277 +S32508009CC0FF221A701B78DBB28DF803309DF8033003F05003334A1370334B07221A601BE0C9 +S32508009CE04FF0500383F31188BFF36F8FBFF34F8FFEE74FF0500383F31188BFF36F8FBFF38D +S32508009D004F8FFEE7284A1368013B13609DF803305B00DBB28DF803309DF8033013F0800F14 +S32508009D20F0D1214B1B68032B08D04FF0500383F31188BFF36F8FBFF34F8FFEE71B021A4A18 +S32508009D40136003F4E0631360019BDBB2144A13704FF0E024D4F8203D43F47003C4F8203D9C +S32508009D60D4F8203D43F07043C4F8203DFFF780FF00250E4B1D60FFF7BDFED4F8343F43F01A +S32508009D804043C4F8343FFFF7A1FE01F02FFAFFF77DFE284603B030BD71C20F4170C20F41D0 +S32508009DA000E400E0B0120020B4120020C4000020EFF305830F2B0FD9114A9B5CDBB2114A5F +S32508009DC012789A4208D94FF0500383F31188BFF36F8FBFF34F8FFEE74FF0E023D3F80C3D12 +S32508009DE003F4E063084A1268934208D94FF0500383F31188BFF36F8FBFF34F8FFEE770471C +S32508009E00F0E300E0B0120020B4120020124A12F0070F1ED0D11D21F00701C1F50043134400 +S32508009E200A460E480260002141601344083B23F007030B48036059601960991A51601360D4 +S32508009E40084B1960084B1960084B4FF000421A6070474FF40043E4E7BC120020D092002096 +S32508009E60B8120020C4920020C0920020BC920020164B1A461B688342FBD3516802EB010C0A +S32508009E80844509D0416800EB010C634509D00360904219D0106070474068014451601046B7 +S32508009EA0F0E710B40A4C2468A3420BD05B681944416013681B680360904200D010605DF8CE +S32508009EC0044B70470460F7E7704700BFD0920020B812002070B5054601F04CF8364B1B68A1 +S32508009EE0A3B1364B1B681D424ED135B1083515F0070F02D025F007050835002D46D0304B52 +S32508009F001B68AB4251D32F4A146804E0FFF77EFFE7E722461C466368AB4202D22368002B79 +S32508009F20F7D1254B1B68A34241D0166808362368136063685B1B102B10D9601910F0070FB4 +S32508009F4008D04FF0500383F31188BFF36F8FBFF34F8FFEE743606560FFF78AFF6268184943 +S32508009F600B689B1A0B60184909688B4201D216490B60124B1B681343636000232360134A08 +S32508009F8013680133136002E0002600E0002601F08BF816F0070F0CD04FF0500383F3118876 +S32508009FA0BFF36F8FBFF34F8FFEE70026EFE70026EDE7304670BD00BFB8120020BC920020BE +S32508009FC0C0920020D0920020C4920020C8920020002834D038B50446A0F1080550F8043C06 +S32508009FE0174A1268134208D14FF0500383F31188BFF36F8FBFF34F8FFEE750F8081C41B126 +S3250800A0004FF0500383F31188BFF36F8FBFF34F8FFEE723EA020340F8043C00F0ABFF54F8FC +S3250800A020041C084A13680B4413602846FFF720FF054A13680133136001F036F838BD7047A4 +S3250800A040BC920020C0920020CC9200200346406A18B11B6B1868C0F13800704710B5044623 +S3250800A060FFF780FDA26BE36B9A4204D00024FFF79BFD204610BD0124F9E710B50446FFF765 +S3250800A08071FDA36B23B90124FFF78EFD204610BD0024F9E770B504461546866B026C5AB941 +S3250800A0A003681BB100200136A66370BD806801F0EFFA0023A360F6E76DB94068F8F768FCE8 +S3250800A0C0226C636813446360A268934219D3236863602846E7E7C068F8F75AFC226C51421C +S3250800A0E0E3689B1AE3602268934202D2A3680B44E360022D01D00020D5E726B1013E00202D +S3250800A100D1E72846CFE70020CDE70346026C6AB110B50846D9681144D9609C68A14201D312 +S3250800A1201968D960D968F8F733FC10BD704738B50546FFF717FD95F8454064B201E0013CEC +S3250800A14064B2002C0ADD6B6A43B105F1240001F05FF90028F3D001F033FAF0E7FF2385F81D +S3250800A1604530FFF721FDFFF7FDFC95F8444064B201E0013C64B2002C0ADD2B6943B105F16D +S3250800A180100001F045F90028F3D001F019FAF0E7FF2385F84430FFF707FD38BD38B5E0B12C +S3250800A1A00D460446FFF7DEFC2368E26B216C01FB0230A0600020A0636360013A02FB01333F +S3250800A1C0E360FF2384F8443084F84530FDB9236963B9FFF7E9FC012038BD4FF0500383F3D4 +S3250800A1E01188BFF36F8FBFF34F8FFEE704F1100001F00EF90028ECD04FF0E0234FF080525F +S3250800A200C3F8042DBFF34F8FBFF36F8FE1E704F11000FFF7F5FB04F12400FFF7F1FBD8E797 +S3250800A22038B51D46049C0B4649B92460E063236401212046FFF7B2FF84F84C5038BD2260C1 +S3250800A240F4E740B94FF0500383F31188BFF36F8FBFF34F8FFEE710B584B01C46844653B12D +S3250800A26092B189B94FF0500383F31188BFF36F8FBFF34F8FFEE74FF0500383F31188BFF332 +S3250800A2806F8FBFF34F8FFEE76AB150230393039B502B13D04FF0500383F31188BFF36F8FCC +S3250800A2A0BFF34F8FFEE70029EFD04FF0500383F31188BFF36F8FBFF34F8FFEE7039B0123AB +S3250800A2C084F8463000949DF818306046FFF7A8FF204604B010BD40B94FF0500383F3118849 +S3250800A2E0BFF36F8FBFF34F8FFEE7F0B583B00D461446064601FB00F05030FFF7EBFD0746C3 +S3250800A30050B1002380F846300090234600F1500229463046FFF784FF384603B0F0BDF0B500 +S3250800A32085B0019288B10F461D460446B1B1022D20D1E36B012B1DD04FF0500383F3118882 +S3250800A340BFF36F8FBFF34F8FFEE74FF0500383F31188BFF36F8FBFF34F8FFEE7036C002B6A +S3250800A360E5D04FF0500383F31188BFF36F8FBFF34F8FFEE701F030F9064658B9019B002B16 +S3250800A38048D04FF0500383F31188BFF36F8FBFF34F8FFEE700263DE02A4639462046FFF743 +S3250800A3A079FE636A7BB948B14FF0E0234FF08052C3F8042DBFF34F8FBFF36F8FFFF7F4FBBA +S3250800A3C0012005B0F0BD04F1240001F021F80028F4D04FF0E0234FF08052C3F8042DBFF3EC +S3250800A3E04F8FBFF36F8FE9E7FFF7DEFB0020E8E702A801F097F8012619E0002384F84430D6 +S3250800A40021E0002384F8453023E02046FFF78FFE00F04AFEFFF7A6FBA26BE36B9A42BBD399 +S3250800A420022DB9D0019B002BDED0002EE0D0FFF7BBFB00F09FFDFFF795FB94F8442052B251 +S3250800A440B2F1FF3FD9D094F8452052B2B2F1FF3FD7D0FFF7A9FB01A902A801F06FF8D8B910 +S3250800A4602046FFF7FBFD0028CFD0019904F1100000F06EFF2046FFF75AFE00F015FE0028D8 +S3250800A480C8D14FF0E0234FF08052C3F8042DBFF34F8FBFF36F8FBDE72046FFF748FE00F060 +S3250800A4A003FE00208DE748B108B5002181600160C1600B460A46FFF732FF08BD704710B5B6 +S3250800A4C0024600210120FFF706FF0446FFF7EBFF204610BD10B582B00B460090002211463B +S3250800A4E00120FFF7AEFE0446FFF7DDFF204602B010BD38B538B10446856801F067F8854266 +S3250800A5000AD0002038BD4FF0500383F31188BFF36F8FBFF34F8FFEE7E368013BE3600BB1F2 +S3250800A5200120EFE71A4619462046FFF7F8FE0120E8E72DE9F84390B10F4616461C46054625 +S3250800A540B1B1022C20D1EB6B012B1DD04FF0500383F31188BFF36F8FBFF34F8FFEE74FF0F8 +S3250800A560500383F31188BFF36F8FBFF34F8FFEE7036C002BE5D04FF0500383F31188BFF3A4 +S3250800A5806F8FBFF34F8FFEE7FFF712FCEFF311884FF0500383F31188BFF36F8FBFF34F8FDA +S3250800A5A0AA6BEB6B9A4206D3022C04D0002088F31188BDE8F88395F845904FFA89F9AB6BD4 +S3250800A5C0224639462846FFF765FDB9F1FF3F06D009F101035BB285F845300120E7E76B6A41 +S3250800A5E00BB90120E3E705F1240000F011FF18B126B101203060DAE70120D8E70120D6E7B4 +S3250800A600F0B585B0019290B10F460446C1B100F0E3FF064600BB019B002B5ED04FF050030D +S3250800A62083F31188BFF36F8FBFF34F8FFEE74FF0500383F31188BFF36F8FBFF34F8FFEE712 +S3250800A640036C002BE3D04FF0500383F31188BFF36F8FBFF34F8FFEE700263EE039462046B0 +S3250800A660FFF753FD013DA563236923B9FFF79CFA012005B0F0BD04F1100000F0C9FE0028E5 +S3250800A680F4D04FF0E0234FF08052C3F8042DBFF34F8FBFF36F8FE9E7FFF786FA0020E8E734 +S3250800A6A002A800F03FFF012621E0002384F8443029E0002384F845302BE02046FFF737FDC1 +S3250800A6C000F0F2FC09E02046FFF731FD00F0ECFC2046FFF7D2FC00283FD1FFF743FAA56B9E +S3250800A6E0002DBBD1019B002BD6D0002ED8D0FFF75BFA00F03FFCFFF735FA94F844305BB2A8 +S3250800A700B3F1FF3FD1D094F845305BB2B3F1FF3FCFD0FFF749FA01A902A800F00FFF002866 +S3250800A720D1D12046FFF7A9FC0028C6D0019904F1240000F00DFE2046FFF7F9FC00F0B4FC0B +S3250800A7400028CAD14FF0E0234FF08052C3F8042DBFF34F8FBFF36F8FBFE7002089E770B54E +S3250800A76084B0019158B10446036C8BB14FF0500383F31188BFF36F8FBFF34F8FFEE74FF002 +S3250800A780500383F31188BFF36F8FBFF34F8FFEE700F022FF054650B9019B5BB14FF0500385 +S3250800A7A083F31188BFF36F8FBFF34F8FFEE70026354655E0064653E0013BA36323683BB149 +S3250800A7C023694BB9FFF7F0F90126304604B070BD01F002F8A060F3E704F1100000F018FEAE +S3250800A7E00028EFD04FF0E0234FF08052C3F8042DBFF34F8FBFF36F8FE4E746B14FF0500391 +S3250800A80083F31188BFF36F8FBFF34F8FFEE7FFF7CBF9DAE702A800F085FE01252AE000230B +S3250800A82084F8443032E0002384F8453034E0FFF799F9A06800F0E0FE0646FFF7B5F93BE077 +S3250800A8402046FFF774FC00F02FFC09E02046FFF76EFC00F029FC2046FFF70FFC002842D19D +S3250800A860FFF780F9A36B002BA6D1019B002BC4D0002DCFD0FFF798F900F07CFBFFF772F935 +S3250800A88094F844305BB2B3F1FF3FC8D094F845305BB2B3F1FF3FC6D0FFF786F901A902A8D4 +S3250800A8A000F04CFE0028D1D12046FFF7E6FB0028C6D02368002BBAD0019904F1240000F0A8 +S3250800A8C047FD2046FFF733FC00F0EEFB0028C7D14FF0E0234FF08052C3F8042DBFF34F8F33 +S3250800A8E0BFF36F8FBCE70EB900266EE7FFF73AF92046FFF7ABFB0146A06800F011FFFFF745 +S3250800A90053F9F1E780B170B50C460546866800F05DFE864211D021462846FFF720FF80B115 +S3250800A920EB680133EB600CE04FF0500383F31188BFF36F8FBFF34F8FFEE7EB680133EB60B3 +S3250800A940012070BD2DE9F843B0B10D4690460446D9B1FFF72DFAEFF311874FF0500383F34D +S3250800A9601188BFF36F8FBFF34F8FA66BCEB9002087F31188BDE8F8834FF0500383F3118864 +S3250800A980BFF36F8FBFF34F8FFEE7036C002BE0D04FF0500383F31188BFF36F8FBFF34F8F59 +S3250800A9A0FEE794F844904FFA89F929462046FFF7ACFB731EA363B9F1FF3F06D009F10103B4 +S3250800A9C05BB284F844300120D2E723690BB90120CEE704F1100000F01BFD30B1B8F1000FC6 +S3250800A9E005D00120C8F80000C2E70120C0E70120BEE700000023072B0CD8074A52F8332035 +S3250800AA000AB10133F7E7044A42F8331002EBC30250607047704700BFD892002070B5044608 +S3250800AA200D461646FFF79EF894F844305BB2B3F1FF3F0DD094F845305BB2B3F1FF3F0BD036 +S3250800AA40FFF7B2F8A36B5BB12046FFF770FB70BD002384F84430EDE7002384F84530EFE769 +S3250800AA603246294604F1240000F0B6FCECE70000084B1B681B6823B9074B4FF0FF321A60E2 +S3250800AA807047044B1B68DB68DB685A68024B1A60704700BF1C930020C49700202DE9F04703 +S3250800AAA080460D4617469946089EDDF824A00A9C9200A521206B01F089F9236B07F18042B0 +S3250800AAC0013A03EB820727F00707002D61D04FF0000CBCF10F0F09D815F80C3004EB0C02F6 +S3250800AAE082F8343013B10CF1010CF2E7002384F84330372E00D93726E662E66400252565D5 +S3250800AB00201DFEF788FF04F11800FEF784FF2461C6F13806A6616462C4F8785184F87C51D4 +S3250800AB204FF49072294604F1580001F04FF91B4BE36503F168022266D03363660122002327 +S3250800AB40C4E93C2343F20E33A4F8F8304AF6CD33A4F8FA3041F23423A4F8FC304EF26D6339 +S3250800AB60A4F8FE304DF6EC63A4F800310523A4F802310B23A4F804314A4641463846FEF71E +S3250800AB80C3FF2060BAF1000F01D0CAF80040BDE8F087002384F83430ABE700BF449900206B +S3250800ABA038B5002407E004EB840293000E481844FEF726FF0134372CF5D90C4D2846FEF799 +S3250800ABC01FFF0B4C2046FEF71BFF0A48FEF718FF0948FEF715FF0948FEF712FF084B1D609E +S3250800ABE0084B1C6038BD00BF2493002098970020AC970020D0970020FC970020E897002062 +S3250800AC001C9300202093002010B50446FEF7AAFF224A136801331360214B1B685BB1214BE2 +S3250800AC201B686BB91E4B1B68DA6AE36A9A4207D81B4B1C6004E01A4B1C601368012B29D0E0 +S3250800AC40194A1368013313606364E06A174B1B68984201D9154B186000EB8000211D144BD7 +S3250800AC6003EB8000FEF7DAFEFEF79EFF0D4B1B687BB10B4B1B68DA6AE36A9A4209D24FF092 +S3250800AC80E0234FF08052C3F8042DBFF34F8FBFF36F8F10BDFFF784FFD2E700BF849700206D +S3250800ACA018930020E497002090970020949700202493002010B50446583001F0D9F894F8D2 +S3250800ACC07D3163B1012B11D0022B0ED04FF0500383F31188BFF36F8FBFF34F8FFEE7206B3B +S3250800ACE0FFF776F92046FFF773F910BD2046FFF76FF9FAE70F4B1B68D3B110B5FEF732FF5B +S3250800AD000D4BDB68DC68201DFEF7ACFE0B4A1368013B1360074A1368013B1360FEF744FF38 +S3250800AD202046FFF7C7FF034B1B68002BE6D110BD704700BF88970020FC97002084970020C0 +S3250800AD4008B5FFF7D7FF074B1B68012BF9D94FF0E0234FF08052C3F8042DBFF34F8FBFF308 +S3250800AD606F8FEEE72493002070B504460D46174B1E68174B18680430FEF774FEB4F1FF3F11 +S3250800AD800DD03444124B1B685C60A64210D9114B18680F4B19680431FEF74BFE70BD002D5F +S3250800ADA0EFD00B4B196804310B48FEF737FEF5E70A4B1868064B19680431FEF73AFE084B05 +S3250800ADC01B68A342EAD9064B1C60E7E7109800201893002020930020E89700201C930020CB +S3250800ADE0C497002030B587B00B9C8CB10C9DC5B14FF4C0750495049DB5F5C07F1AD04FF0E7 +S3250800AE00500383F31188BFF36F8FBFF34F8FFEE74FF0500383F31188BFF36F8FBFF34F8FBC +S3250800AE20FEE74FF0500383F31188BFF36F8FBFF34F8FFEE7049D0C9D2C63022485F87D411F +S3250800AE4000240394029505AC01940A9C0094FFF725FE0C98FFF7D8FE059807B030BD2DE932 +S3250800AE60F04385B00746884614461E469000FFF731F808B381464FF4C070FFF72BF805467B +S3250800AE80B0B1C0F83090E5B1002385F87D31039302950D9B01930C9B0093334622464146DC +S3250800AEA03846FFF7FBFD2846FFF7AEFE012005E04846FFF78DF8E6E74FF0FF3005B0BDE864 +S3250800AEC0F0834FF0FF30F9E710B588B000240594069407AA06A905A8FEF722FC059B0293FA +S3250800AEE0069B019300942346079A1A491A48FFF779FF1A4B186040B100F00EFD012806D076 +S3250800AF00B0F1FF3F1DD008B010BD0020F6E74FF0500383F31188BFF36F8FBFF34F8F104B99 +S3250800AF201B6858330F4A13600F4B4FF0FF321A600E4B01221A600E4B00221A60FEF7ACFE5B +S3250800AF40E1E74FF0500383F31188BFF36F8FBFF34F8FFEE788C8000841AD0008C097002090 +S3250800AF6018930020E8010020C4970020E497002010980020024A136801331360704700BF2D +S3250800AF808C970020014B1868704700BF10980020F8B53A4B1B68002B69D1394B1D680135FD +S3250800AFA01D60C5B9374B1B681B6843B14FF0500383F31188BFF36F8FBFF34F8FFEE7314ACB +S3250800AFC01168314B186810601960304A136801331360FFF74DFD2E4B1B68AB423DD9002703 +S3250800AFE02C4B1B68DB6A03EB83039A002A4B9B58012B00D90127294B1B68002B3CD001270B +S3250800B0003AE001271F4B1B681B6843B31D4B1B68DB68DC6863689D4226D3261D3046FEF7B7 +S3250800B02021FDA36A1BB104F11800FEF71BFDE36A1B4A1268934201D9194A136003EB8303CC +S3250800B0409A00314614481044FEF7E8FCE26A114B1B68DB6A9A42D4D2D4E70027D2E70C4B64 +S3250800B0604FF0FF321A60BBE7094A1360B8E70D4A13680133136000273846F8BD8C970020BB +S3250800B080109800201C93002020930020C8970020C4970020189300202493002014980020D0 +S3250800B0A094970020CC97002038B5354B1B6843B94FF0500383F31188BFF36F8FBFF34F8FE7 +S3250800B0C0FEE7FEF74FFD2E4B1A68013A1A601B68002B4FD12B4B1B680BB900244BE000248E +S3250800B0E0294B1B681BB3284BDB68DC6804F11800FEF7B8FC251D2846FEF7B4FCE06A234BC0 +S3250800B1001B68984201D9214B186000EB800029461F4B03EB8000FEF781FCE26A1D4B1B68AB +S3250800B120DB6A9A42DCD31C4B01221A60D8E70CB1FFF79EFC194B1C6884B9174B1C68D4B191 +S3250800B1404FF0E0234FF08052C3F8042DBFF34F8FBFF36F8F01240EE0013C07D0FFF718FF2E +S3250800B1600028F9D00C4B01221A60F5E70B4B00221A60E2E70024FEF717FD204638BD00BFFE +S3250800B1808C97002084970020D097002094970020249300201893002014980020CC97002060 +S3250800B1A010B5A8B10446104B1B6843B14FF0500383F31188BFF36F8FBFF34F8FFEE7FFF78B +S3250800B1C0D9FE00212046FFF7CFFDFFF76DFF48B94FF0E0234FF08052C3F8042DBFF34F8F0F +S3250800B1E0BFF36F8F10BD00BF8C970020214B1B681BB1214B01221A6070471F4B00221A6041 +S3250800B2001E4B1B6803EB83018A001D498A585AB90BB1013BF6E74FF0500383F31188BFF3B5 +S3250800B2206F8FBFF34F8FFEE703EB830082000A4450684068506003EB830C4FEA8C020832BE +S3250800B240114488420FD003EB830291000C4A0A445268D1680B4A116008490B6013685833BF +S3250800B260094A13607047406862469100044A0A445060E8E78C9700201498002094970020ED +S3250800B2802493002018930020E801002038B50446FEF768FCE4B1251D2846FEF7E3FBA36A40 +S3250800B2A01BB104F11800FEF7DDFB29462348FEF7B5FB94F87C31DBB2012B0CD0FEF774FC28 +S3250800B2C01F4B1B685BB91F4B1B68A3420ED038BD1C4B1C68DFE7002384F87C31EEE7FEF7F3 +S3250800B2E041FCFFF7C5FBFEF75FFCECE7144B1B68B3B1154B1B6843B14FF0500383F311886C +S3250800B300BFF36F8FBFF34F8FFEE74FF0E0234FF08052C3F8042DBFF34F8FBFF36F8FD6E7BE +S3250800B320064B1A68094B1B689A4203D1054B00221A60CCE7FFF75AFFC9E700BFE8970020A9 +S3250800B340E4970020189300208C9700208497002058B110B50C46094A11681831FEF769FB6D +S3250800B36001212046FFF700FD10BD4FF0500383F31188BFF36F8FBFF34F8FFEE718930020E6 +S3250800B38070B110B514460246114B1B688BB94FF0500383F31188BFF36F8FBFF34F8FFEE72E +S3250800B3A04FF0500383F31188BFF36F8FBFF34F8FFEE7084B186841F00041816119681831C8 +S3250800B3C01046FEF72BFB01212046FFF7CDFC10BD8C9700201893002038B570B10D46144611 +S3250800B3E00A4A11681831FEF719FB0CB14FF0FF3521462846FFF7B8FC38BD4FF0500383F374 +S3250800B4001188BFF36F8FBFF34F8FFEE71893002038B5C368DC6824B304F118052846FEF7ED +S3250800B42021FB184B1B682BBB251D2846FEF71AFBE06A154B1B68984201D9134B186000EBBA +S3250800B44080002946114B03EB8000FEF7E7FAE26A0F4B1B68DB6A9A4211D901200D4B18602A +S3250800B46038BD4FF0500383F31188BFF36F8FBFF34F8FFEE729460848FEF7D0FAE7E7002097 +S3250800B480EEE700BF8C97002094970020249300201893002014980020D097002038B51C4B33 +S3250800B4A01B6843B94FF0500383F31188BFF36F8FBFF34F8FFEE741F000410160C468F4B195 +S3250800B4C0FEF7D0FA251D2846FEF7CCFAE06A114B1B68984201D90F4B186000EB80002946AB +S3250800B4E00D4B03EB8000FEF799FAE26A0B4B1B68DB6A9A4202D90A4B01221A6038BD4FF0A9 +S3250800B500500383F31188BFF36F8FBFF34F8FFEE78C97002094970020249300201893002066 +S3250800B52014980020034B1B680360034B1B684360704700BFC897002010980020F8B5C8B1A6 +S3250800B5400C460546F9B1FEF70DFB1B4B19686B68C81A2268B2F1FF3F26D0184E36682F6801 +S3250800B560B74201D08B4224D9824215D80023236001241AE04FF0500383F31188BFF36F8F62 +S3250800B580BFF34F8FFEE74FF0500383F31188BFF36F8FBFF34F8FFEE75B1A134423602846A5 +S3250800B5A0FFF7C0FF002400E00024FEF7FDFA2046F8BD0124F9E700BF10980020C89700208E +S3250800B5C0014B01221A60704714980020014B1868704700BF18930020054B1B6833B1054BDD +S3250800B5E01B680BB1002070470220704701207047E49700208C97002000283ED038B504462B +S3250800B600C36A204A1268D26A93422ED28269002A05DB1C4A1268D26AC2F13802826161694F +S3250800B62003EB8303184A02EB8303994205D0154B1B68DB6AE362012038BD251D2846FEF7DB +S3250800B64011FA104B1B68D86AE062104B1B68984201D90E4B186000EB800029460A4B03EBEF +S3250800B6608000FEF7DBF90120E6E7C26C054B1B68DB6A9A4203D30020DEE7002070470120B0 +S3250800B680DAE700BF18930020249300209497002000283BD038B504461E4B1B68834208D03C +S3250800B6A04FF0500383F31188BFF36F8FBFF34F8FFEE7036D43B94FF0500383F31188BFF3F7 +S3250800B6C06F8FBFF34F8FFEE7013B0365C16AC26C91421DD00BB1002038BD051D2846FEF7D6 +S3250800B6E0C1F9E06CE062C0F13803A3610A4B1B68984201D9084B186000EB80002946074B81 +S3250800B70003EB8000FEF78AF90120E5E7002070470020E1E71893002094970020249300209C +S3250800B720002846D038B50446036D43B94FF0500383F31188BFF36F8FBFF34F8FFEE7C26C26 +S3250800B7408A4200D20A46E16A914201D0012B00D038BD184B1B68A34222D0E262A369002BD5 +S3250800B76002DBC2F13802A261626901EB8101124B03EB81039A42EBD1251D2846FEF772F93E +S3250800B780E06A0E4B1B68984201D90C4B186000EB80002946084B03EB8000FEF73FF9D7E76C +S3250800B7A04FF0500383F31188BFF36F8FBFF34F8FFEE7704718930020249300209497002011 +S3250800B7C0044A136898691368DB6A1268C3F138039361704718930020054B1B6823B1044BFC +S3250800B7E01A68136D01331365014B1868704700BF18930020064B1A6813682BB901230360C7 +S3250800B80023B9D368186870470023F8E7002070471898002008B54160006191420CD8D21AC1 +S3250800B82083699A4201D3012008BD011D094B1868FEF7FFF80020F7E79A4201D2994206D23A +S3250800B840011D054B1868FEF7F4F80020ECE70120EAE700BF1C9800201898002030B583B0AB +S3250800B860FEF780F9114B1B681BB1FEF79DF903B030BD0F4D2846FEF7C3F80E4C2046FEF747 +S3250800B880BFF80D4B1D600D4B1C60002300930C4B0C4A10210A20FEF7D4FC044B18600028C8 +S3250800B8A0E3D00949FFF7A6F8DFE700BF3C990020C0980020D4980020189800201C980020BF +S3250800B8C0EC9800202098002090C800082DE9F041079F41B94FF0500383F31188BFF36F8F46 +S3250800B8E0BFF34F8FFEE7064614461D4688468FB1FFF7B4FF3E60C7F81880FD61069B3B6274 +S3250800B900381DFEF788F82CB197F8283043F0040387F82830BDE8F08110B588B0FFF79EFFD4 +S3250800B920124B1B68CBB100240594069407AA06A905A8FDF701FF059B0293069B01930223B6 +S3250800B94000932346079A0A490A48FFF74BFA0A4B186010B1012008B010BD4FF0500383F320 +S3250800B9601188BFF36F8FBFF34F8FFEE73C99002098C8000809BD0008409900202DE9F04190 +S3250800B98082B00446884617461D462C20FEF7A2FA064658B1002380F828300190089B0093A3 +S3250800B9A02B463A4641462046FFF790FF304602B0BDE8F08110B584B084462C20039003989B +S3250800B9C02C2808D04FF0500383F31188BFF36F8FBFF34F8FFEE70398079860B10220079C57 +S3250800B9E084F828000194069800906046FFF76EFF079804B010BD4FF0500383F31188BFF356 +S3250800BA006F8FBFF34F8FFEE7B8B19C4603461848006858B300B585B000910192029305296D +S3250800BA201CDCFFF7D9FD022810D000231A4669460F480068FEF773FC15E04FF0500383F3D8 +S3250800BA401188BFF36F8FBFF34F8FFEE70023069A694607480068FEF762FC04E000236246EF +S3250800BA606946FEF766FD05B05DF804FB002070473C99002070B582B01B4B1B681A6862B305 +S3250800BA80DB681E68DC68251D2846FDF7EBFF236A2046984794F8283013F0040FECD0A36969 +S3250800BAA033449E4207D26360246129460E4B1868FDF7BFFFE0E7002100910B46324620465E +S3250800BAC0FFF7A2FF0028D7D14FF0500383F31188BFF36F8FBFF34F8FFEE7044A106802491A +S3250800BAE00860136002B070BD189800201C98002038B50546FFF746FA0446074B1B68834288 +S3250800BB0005D800232B60044B1C60204638BDFFF7B1FF01232B60F6E7E898002070B582B03D +S3250800BB2006460D4617490968C968CC68201DFDF799FF94F828C01CF0040F08D12CF0010CC4 +S3250800BB4084F828C0236A2046984702B070BDA16933462A4631442046FFF75CFE0028F1D0BB +S3250800BB60002100910B4632462046FFF74DFF0028E8D14FF0500383F31188BFF36F8FBFF3B0 +S3250800BB804F8FFEE71898002070B582B006460C46FFF7F0F901A8FFF7ABFF019B33BB054612 +S3250800BBA00CB9B04219D224B1124A12681268DAB901242246711B104B1868FEF72FFFFFF710 +S3250800BBC073FAA8B94FF0E0234FF08052C3F8042DBFF34F8FBFF36F8F0AE0FFF765FA29465C +S3250800BBE03046FFF79BFF03E01C46E2E7FFF75CFA02B070BD1C9800203C99002010B588B032 +S3250800BC0002E0049B002B0FDA002204A93D4B1868FEF7F6FC002873D0049B002BF1DA079923 +S3250800BC200698059B9847ECE7069C636913B1201DFDF718FF03A8FFF75BFF049B092BE3D803 +S3250800BC40DFE803F00505053037500505303794F8283043F0010384F82830059BA169024604 +S3250800BC6019442046FFF7D6FD0028CDD0236A2046984794F8283013F0040FC5D0A2690021D8 +S3250800BC8000910B46059802442046FFF7BDFE0028BAD14FF0500383F31188BFF36F8FBFF304 +S3250800BCA04F8FFEE794F8283023F0010384F82830AAE794F8283043F0010384F828300599C6 +S3250800BCC0A16131B10346024601442046FFF7A2FD9AE74FF0500383F31188BFF36F8FBFF31D +S3250800BCE04F8FFEE794F8283013F0020F04D023F0010384F8283087E72046FEF769F983E727 +S3250800BD0008B010BD3C99002000B583B001A8FFF771FD0199FFF738FFFFF770FFF6E740B1AC +S3250800BD2010B50446FDF71EFFE469FDF73DFF204610BD4FF0500383F31188BFF36F8FBFF322 +S3250800BD404F8FFEE710B584B014461A466FF00103009301900291039400236946024800682A +S3250800BD60FEF7E7FB04B010BD3C990020DFF834D0F9F7AEF80C480D490D4A002302E0D458C5 +S3250800BD80C4500433C4188C42F9D30A4A0A4C002301E013600432A242FBD300F09DF8F8F757 +S3250800BDA0FDFDFEE7000001200000002000060020B0C8000800060020489C0020FEE70000A0 +S3250800BDC0002301461A46184600F0C2B8830730B548D0541E002A3FD0CAB2034601E0013CAE +S3250800BDE03AD303F8012B9D07F9D1032C2DD9CDB245EA05250F2C45EA054536D9A4F110021C +S3250800BE0022F00F0C03F1200EE6444FEA121C03F1100242E9045542E9025510327245F8D166 +S3250800BE200CF1010214F00C0F03EB021204F00F0C13D0ACF1040323F003030433134442F85C +S3250800BE40045B9342FBD10CF003042CB1C9B21C4403F8011B9C42FBD130BD64461346002C3C +S3250800BE60F4D1F9E703461446BFE71A46A446E0E7154B1B68834225D0416C70B5054681B1C9 +S3250800BE8000268C593CB121462468284600F0FEF8002CF8D1696C0436802EF2D1284600F082 +S3250800BEA0F5F8A96B11B1284600F0F0F8E96C11B1284600F0EBF86B6B1BB12846BDE87040AE +S3250800BEC0184770BD704700BFE8010020014B1868704700BFE801002070B50D4E0D4D761B93 +S3250800BEE0B61006D0002455F8043B01349847A642F9D1094E094D761B00F0ECF9B61006D073 +S3250800BF00002455F8043B01349847A642F9D170BDA0C80008A0C80008A8C80008A0C80008A8 +S3250800BF2038B5074D074C2C1BA41005D0013C55F8043D9847002CF9D1BDE8384000F0D0B959 +S3250800BF40ACC80008A8C80008704700BF704700BF2DE9F047DFF87CA00646DAF800009846B7 +S3250800BF600F469146FFF7F0FF184B1C6824B365681F2D24DC5EB96B1C0235DAF80000636061 +S3250800BF8044F82570FFF7E2FF0020BDE8F08704EB85010123C1F88890D4F88821AB401A4388 +S3250800BFA0022EC4F88821C1F80881E4D1D4F88C211A43C4F88C21DEE7054C1C60D7E7DAF886 +S3250800BFC00000FFF7C3FF4FF0FF30DEE7189C0020889A0020EC010020024B13B10248FFF7F4 +S3250800BFE0EFBE70470000000021BF0008F8B5244F0C46064600F050F9BB685D68C4F57E6170 +S3250800C0000F3125F003054B1923F47F6323F00F03A3F58054B4F5805F07DB0021304600F0D6 +S3250800C02047F9BB682B44984204D0304600F03AF90020F8BD6142304600F03AF901300DD0BA +S3250800C040104ABB682D1B45F001055D60136830461B1B136000F026F90120F8BD00213046FF +S3250800C06000F026F9BA68831A0F2BDEDD43F001035360054B03491B68C01A0860D5E700BF29 +S3250800C080F00100201C9C0020F8050020002961D0F8B50C46064600F0FFF854F8042C7B4FBA +S3250800C0A0A4F1080522F0010105EB010CB868DCF80430604523F0030300F08B80D207CCF841 +S3250800C0C0043032D454F8082CAD1A1144AA6807F1080082426AD00CEB0304D4F804E0EC686A +S3250800C0E0D4601EF0010FA26000F0978041F001036B60CCF80010B1F5007F35D27868CB0824 +S3250800C1000122490901338A40024357F833107A6007EBC302083AC5E9021247F83350CD6043 +S3250800C1203046BDE8F84000F0BDB80CEB03025268D00710D4194407F10800DCF8083083429A +S3250800C14073D0DCF80C20DA60936041F001036B606950D0E7704741F00103B1F5007F44F8A4 +S3250800C160043CCCF80010C9D3B1F5206F4FEA512348D28B0903F1390003F13802C300F81843 +S3250800C180FB580838984259D05A6822F003028A4202D99B689842F7D1D868C5E902308560D1 +S3250800C1A0DD603046BDE8F84000F07CB80CEB03025268D20763D40B44DCE90212CA609160B4 +S3250800C1C043F001026A603046EB50BDE8F84000F069B80B44D10707D454F8082CAD1A134412 +S3250800C1E0D5E90212CA60916043F001026A60284ABD6012689A4293D8264B30461968FFF796 +S3250800C200F5FE8DE7142B0AD9542B1FD80B0B03F16F0003F16E02C300B1E719448DE703F114 +S3250800C2205C0003F15B02C300A9E741F00103C7E90455C5E902006B60695071E779689210A3 +S3250800C240012404FA02F20A437A60A6E7B3F5AA7F06D8CB0B03F1780003F17702C3008EE76F +S3250800C26040F25452934206D88B0C03F17D0003F17C02C30083E74FF47E737E227FE741F013 +S3250800C28001036B60CCF800104AE700BFF0010020FC050020449C00200148FFF755BE00BFBA +S3250800C2A0849A00200148FFF751BE00BF849A002038B5074D0022044608462A60F8F7E4FD92 +S3250800C2C0431C00D038BD2B68002BFBD0236038BD7C9A0020F8B500BFF8BC08BC9E46704776 +S3250800C2E0F8B500BFF8BC08BC9E46704700000000494E49545F54687265616400F0C200080C +S3250800C30000000000000000000000000000000000000400002F0000000000000000000000DC +S3250800C3204D41494E5F5761746368646F670000004D41494E5F55706461746554696D657252 +S3250800C340000000004D41494E5F4576656E745F466C616773000000004D41494E5F43414EA7 +S3250800C3605F52785F51756575650000004D41494E5F5468726561640058C300080000000023 +S3250800C3800000000000000000000000000000000044C3000800000000000000000000000080 +S3250800C3A06CC300080000000000000000000000000000000000040000210000000000000013 +S3250800C3C00000000030C3000800000000000000000000000020C30008000000000000000069 +S3250800C3E0000000005045434F5F4576656E745F466C616773000000005045434F5F557064AC +S3250800C40061746554696D6572000000005045434F5F54687265616400E4C300080000000046 +S3250800C42000000000000000000CC40008000000000000000000000000000000000004000012 +S3250800C440280000000000000000000000F8C3000800000000000000000000000056415248B2 +S3250800C4605F4D75746578000000000000010000000000000001000000010000000000000039 +S3250800C480000000C0000040411100000000000000000000000000C842110000000000000021 +S3250800C4A0000000000000C8421100000000000000000000000000C842010000000000B8414F +S3250800C4C0000020C2000048421100000000002041000000000000404111000000000000C01E +S3250800C4E0000000C0000000000900000000000000000070C20000C842090000000000000020 +S3250800C500000070C20000C8420900000000000000000048C200008C420900000000000000E7 +S3250800C5200000A0C0000060410900000000000000000020C100002041090000000000000098 +S3250800C540000000000000A0400900000000000000000048C200001643090000000000000078 +S3250800C5600000A0410000F0410900000000000000000000000000A0400900000000000000A9 +S3250800C580000000000000164308000000000000000000000001000000080000000000000023 +S3250800C5A000000000FFFFFFFF110000003333534002000000000080405CC40008030000007A +S3250800C5C00000000000000000414443445F4D757465780000C8C50008030000000000000037 +S3250800C5E000000000414E50495F4D757465780000414E50495F4576656E745F466C616773BE +S3250800C60000000000414E50495F54687265616400000020410000A040000020410000A040AB +S3250800C62000000000000004419A996D4100000441E4C50008030000000000000000000000CD +S3250800C640F0C5000800000000000000000000000004C600080000000000000000000000003D +S3250800C6600000000000040000100000000000000000000000000400488000000000000000CC +S3250800C6800000000001000000000000000000000001000000000800480080000000000000BA +S3250800C6A0000000000100000000000000000000000100000000040048080000000000000016 +S3250800C6C00000000001000000000000000000000001000000000400481000000000000000EE +S3250800C6E0000000000100000000000000000000000100000000000048008000000000000062 +S3250800C70000000000010000000000000000000000010000000004004840000000010000007C +S3250800C72000000000010000000000000001000000000000000004004820000000010000007C +S3250800C740000000000100000000000000010000000000000000080048004000000100000038 +S3250800C76000000000010000000000000000000000010000000000004800010000010000005F +S3250800C7800000000001000000000000000000000001000000535049445F4576656E745F4653 +S3250800C7A06C61677300000000535049445F4144435F4D75746578000038090020000000009A +S3250800C7C0CCC700080100000002000000A8C7000803000000000000000000000094C70008D0 +S3250800C7E000000000000000000000000054454D505F54687265616400ECC700080000000083 +S3250800C80000000000000000000000000000040000180000000000000000000000446566617E +S3250800C820756C74001CC800080000000000000000000000000000000000020000180000008F +S3250800C840000000000000000000000000000000000102030406070809A0860100400D03002B +S3250800C860801A060000350C0040420F0080841E0000093D0000127A000024F40000366E0187 +S3250800C8800048E801006CDC0249444C4500000000546D725100000000546D722053766300EE +S3250800C8A0D9BF000825330008013300080000000000FF0000F4060020EC0600200000000003 +S3250800C8C000000000000000000000000000000000000000000000000000000000000000004A +S3250800C8E000000000000000000000000000000000000000000060000000000000E0E9000001 +S3250800C9000000000000000000010000000000000001000000010000000000000000400000C6 +S3250800C9200000000000E80000000000000000000000000000000000000100000001000000FF +S3250800C9400000000000093D0001000000100000000000000000000000000000000000000072 +S3250800C9600100000000000000000000000000000020000000AAAAAAAA0000000044990020E3 +S3250800C980AC990020149A002000000000000000000000000000000000000000000000000056 +S3250800C9A0000000000000000000000000000000000000000000000000000000000000000069 +S3250800C9C0000000000000000000000000000000000000000000000000000000000000000049 +S3250800C9E0000000000000000000000000000000000000000000000000000000000000000029 +S3250800CA000000000000000000000000000000000001000000000000000E33CDAB34126DE6B5 +S3250800CA20ECDE05000B0000000000000000000000000000000000000000000000000000000E +S3250800CA400000000000000000000000000000000000000000000000000000000000000000C8 +S3250800CA600000000000000000000000000000000000000000000000000000000000000000A8 +S3250800CA80000000000000000000000000000000000000000000000000C8000020809A002066 +S3250800CAA00000000000000000F0010020F0010020F8010020F80100200002002000020020D0 +S3250800CAC0080200200802002010020020100200201802002018020020200200202002002098 +S3250800CAE0280200202802002030020020300200203802002038020020400200204002002078 +S3250800CB00480200204802002050020020500200205802002058020020600200206002002057 +S3250800CB20680200206802002070020020700200207802002078020020800200208002002037 +S3250800CB40880200208802002090020020900200209802002098020020A0020020A002002017 +S3250800CB60A8020020A8020020B0020020B0020020B8020020B8020020C0020020C0020020F7 +S3250800CB80C8020020C8020020D0020020D0020020D8020020D8020020E0020020E0020020D7 +S3250800CBA0E8020020E8020020F0020020F0020020F8020020F80200200003002000030020B5 +S3250800CBC008030020080300201003002010030020180300201803002020030020200300208F +S3250800CBE028030020280300203003002030030020380300203803002040030020400300206F +S3250800CC0048030020480300205003002050030020580300205803002060030020600300204E +S3250800CC2068030020680300207003002070030020780300207803002080030020800300202E +S3250800CC40880300208803002090030020900300209803002098030020A0030020A00300200E +S3250800CC60A8030020A8030020B0030020B0030020B8030020B8030020C0030020C0030020EE +S3250800CC80C8030020C8030020D0030020D0030020D8030020D8030020E0030020E0030020CE +S3250800CCA0E8030020E8030020F0030020F0030020F8030020F80300200004002000040020AC +S3250800CCC0080400200804002010040020100400201804002018040020200400202004002086 +S3250800CCE0280400202804002030040020300400203804002038040020400400204004002066 +S3250800CD00480400204804002050040020500400205804002058040020600400206004002045 +S3250800CD20680400206804002070040020700400207804002078040020800400208004002025 +S3250800CD40880400208804002090040020900400209804002098040020A0040020A004002005 +S3250800CD60A8040020A8040020B0040020B0040020B8040020B8040020C0040020C0040020E5 +S3250800CD80C8040020C8040020D0040020D0040020D8040020D8040020E0040020E0040020C5 +S3250800CDA0E8040020E8040020F0040020F0040020F8040020F80400200005002000050020A3 +S3250800CDC008050020080500201005002010050020180500201805002020050020200500207D +S3250800CDE028050020280500203005002030050020380500203805002040050020400500205D +S3250800CE0048050020480500205005002050050020580500205805002060050020600500203C +S3250800CE2068050020680500207005002070050020780500207805002080050020800500201C +S3250800CE40880500208805002090050020900500209805002098050020A0050020A0050020FC +S3250800CE60A8050020A8050020B0050020B0050020B8050020B8050020C0050020C0050020DC +S3250800CE80C8050020C8050020D0050020D0050020D8050020D8050020E0050020E0050020BC +S3150800CEA0E8050020E8050020FFFFFFFF000002005C +S5030536C1 +S7050800BD6DC8 diff --git a/PeltierControllerV3.ioc b/PeltierControllerV3.ioc index 9b86e0d..29785b2 100644 --- a/PeltierControllerV3.ioc +++ b/PeltierControllerV3.ioc @@ -82,16 +82,17 @@ Mcu.CPN=STM32L432KBU6 Mcu.Family=STM32L4 Mcu.IP0=ADC1 Mcu.IP1=CAN1 -Mcu.IP10=SYS -Mcu.IP2=DAC1 -Mcu.IP3=DMA -Mcu.IP4=FREERTOS -Mcu.IP5=I2C1 -Mcu.IP6=IWDG -Mcu.IP7=NVIC -Mcu.IP8=RCC -Mcu.IP9=SPI1 -Mcu.IPNb=11 +Mcu.IP10=SPI1 +Mcu.IP11=SYS +Mcu.IP2=CRC +Mcu.IP3=DAC1 +Mcu.IP4=DMA +Mcu.IP5=FREERTOS +Mcu.IP6=I2C1 +Mcu.IP7=IWDG +Mcu.IP8=NVIC +Mcu.IP9=RCC +Mcu.IPNb=12 Mcu.Name=STM32L432K(B-C)Ux Mcu.Package=UFQFPN32 Mcu.Pin0=PC14-OSC32_IN (PC14) @@ -111,9 +112,10 @@ Mcu.Pin20=PB4 (NJTRST) Mcu.Pin21=PB5 Mcu.Pin22=PB6 Mcu.Pin23=PB7 -Mcu.Pin24=VP_FREERTOS_VS_CMSIS_V2 -Mcu.Pin25=VP_IWDG_VS_IWDG -Mcu.Pin26=VP_SYS_VS_Systick +Mcu.Pin24=VP_CRC_VS_CRC +Mcu.Pin25=VP_FREERTOS_VS_CMSIS_V2 +Mcu.Pin26=VP_IWDG_VS_IWDG +Mcu.Pin27=VP_SYS_VS_Systick Mcu.Pin3=PA1 Mcu.Pin4=PA2 Mcu.Pin5=PA4 @@ -121,12 +123,12 @@ Mcu.Pin6=PA5 Mcu.Pin7=PA6 Mcu.Pin8=PA7 Mcu.Pin9=PB0 -Mcu.PinsNb=27 +Mcu.PinsNb=28 Mcu.ThirdPartyNb=0 Mcu.UserConstants= Mcu.UserName=STM32L432KBUx -MxCube.Version=6.4.0 -MxDb.Version=DB.6.0.40 +MxCube.Version=6.6.1 +MxDb.Version=DB.6.0.60 NVIC.ADC1_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true\:true NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false NVIC.CAN1_RX0_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true\:true @@ -246,7 +248,7 @@ ProjectManager.StackSize=0x400 ProjectManager.TargetToolchain=Makefile ProjectManager.ToolChainLocation= ProjectManager.UnderRoot=false -ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-MX_DMA_Init-DMA-false-HAL-true,3-SystemClock_Config-RCC-false-HAL-false,4-MX_ADC1_Init-ADC1-false-HAL-true,5-MX_CAN1_Init-CAN1-false-HAL-true,6-MX_DAC1_Init-DAC1-false-HAL-true,7-MX_SPI1_Init-SPI1-false-HAL-true,8-MX_I2C1_Init-I2C1-false-HAL-true,9-MX_IWDG_Init-IWDG-false-HAL-true +ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-MX_DMA_Init-DMA-false-HAL-true,3-SystemClock_Config-RCC-false-HAL-false,4-MX_ADC1_Init-ADC1-false-HAL-true,5-MX_CAN1_Init-CAN1-false-HAL-true,6-MX_DAC1_Init-DAC1-false-HAL-true,7-MX_SPI1_Init-SPI1-false-HAL-true,8-MX_I2C1_Init-I2C1-false-HAL-true,9-MX_IWDG_Init-IWDG-false-HAL-true,10-MX_CRC_Init-CRC-false-HAL-true RCC.ADCCLockSelection=RCC_ADCCLKSOURCE_SYSCLK RCC.ADCFreq_Value=80000000 RCC.AHBFreq_Value=80000000 @@ -311,6 +313,8 @@ SPI1.Direction=SPI_DIRECTION_2LINES SPI1.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate,DataSize,BaudRatePrescaler,CLKPhase SPI1.Mode=SPI_MODE_MASTER SPI1.VirtualType=VM_MASTER +VP_CRC_VS_CRC.Mode=CRC_Activate +VP_CRC_VS_CRC.Signal=CRC_VS_CRC VP_FREERTOS_VS_CMSIS_V2.Mode=CMSIS_V2 VP_FREERTOS_VS_CMSIS_V2.Signal=FREERTOS_VS_CMSIS_V2 VP_IWDG_VS_IWDG.Mode=IWDG_Activate diff --git a/STM32-for-VSCode.config.yaml b/STM32-for-VSCode.config.yaml index f200d75..820e685 100644 --- a/STM32-for-VSCode.config.yaml +++ b/STM32-for-VSCode.config.yaml @@ -67,6 +67,8 @@ excludes: # If a CubeMX makefile is present it will automatically include the include directories from that makefile. includeDirectories: - Core/** + - Middlewares/** + - Drivers/** # Files that should be included in the compilation. @@ -76,9 +78,12 @@ includeDirectories: # these should be escaped with a: \ or the name should be in double quotes e.g. "HARDWARE_DRIVER*.c" sourceFiles: - Core/** + - Middlewares/** + - Drivers/** + - startup_stm32l432xx.s # When no makefile is present it will show a warning pop-up. # However when compilation without the CubeMX Makefile is desired, this can be turned of. -suppressMakefileWarning: false +suppressMakefileWarning: true \ No newline at end of file diff --git a/STM32Make.make b/STM32Make.make index e8cb444..249c0f2 100644 --- a/STM32Make.make +++ b/STM32Make.make @@ -62,6 +62,8 @@ Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.c \ Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.c \ Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_can.c \ Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c \ +Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_crc.c \ +Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_crc_ex.c \ Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dac.c \ Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dac_ex.c \ Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c \ @@ -82,6 +84,8 @@ Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c \ Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.c \ Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c \ Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c \ +Middlewares/ST/EEPROM_Emul/Core/eeprom_emul.c \ +Middlewares/ST/EEPROM_Emul/Porting/STM32L4/flash_interface.c \ Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c \ Middlewares/Third_Party/FreeRTOS/Source/croutine.c \ Middlewares/Third_Party/FreeRTOS/Source/event_groups.c \ @@ -154,8 +158,6 @@ C_DEFS = \ # CXX defines CXX_DEFS = \ --DSTM32L432xx \ --DUSE_HAL_DRIVER # AS includes @@ -172,6 +174,8 @@ C_INCLUDES = \ -IDrivers/CMSIS/Include \ -IDrivers/STM32L4xx_HAL_Driver/Inc \ -IDrivers/STM32L4xx_HAL_Driver/Inc/Legacy \ +-IMiddlewares/ST/EEPROM_Emul/Core \ +-IMiddlewares/ST/EEPROM_Emul/Porting/STM32L4 \ -IMiddlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 \ -IMiddlewares/Third_Party/FreeRTOS/Source/include \ -IMiddlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F @@ -211,7 +215,7 @@ LIBDIR = \ # Additional LD Flags from config file -ADDITIONALLDFLAGS = -specs=nano.specs +ADDITIONALLDFLAGS = LDFLAGS = $(MCU) $(ADDITIONALLDFLAGS) -T$(LDSCRIPT) $(LIBDIR) $(LIBS) -Wl,-Map=$(BUILD_DIR)/$(TARGET).map,--cref -Wl,--gc-sections diff --git a/convertHEXtoSREC.bat b/convertHEXtoSREC.bat index 743857e..b631452 100644 --- a/convertHEXtoSREC.bat +++ b/convertHEXtoSREC.bat @@ -1,5 +1,7 @@ @echo off if %1.==. goto:FEHLER start "" "C:\Program Files\srecord\bin\srec_cat.exe" build/PeltierControllerV3.hex -Intel -o PeltierControllerV%1.srec -Motorola +goto:END :FEHLER -echo Das Script muss folgendermassen aufgerufen werden: %0 Versionsnummer \ No newline at end of file +echo Das Script muss folgendermassen aufgerufen werden: %0 Versionsnummer +:END \ No newline at end of file