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update new protocol and new hardware

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This commit is contained in:
pique_n
2022-06-10 15:40:49 +02:00
parent d6e9c78497
commit 75840c7d51
41 changed files with 1111 additions and 412 deletions
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2
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c
View File

@ -53,7 +53,7 @@
*/
#define STM32L4XX_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define STM32L4XX_HAL_VERSION_SUB1 (0x0DU) /*!< [23:16] sub1 version */
#define STM32L4XX_HAL_VERSION_SUB2 (0x02U) /*!< [15:8] sub2 version */
#define STM32L4XX_HAL_VERSION_SUB2 (0x03U) /*!< [15:8] sub2 version */
#define STM32L4XX_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define STM32L4XX_HAL_VERSION ((STM32L4XX_HAL_VERSION_MAIN << 24U)\
|(STM32L4XX_HAL_VERSION_SUB1 << 16U)\

20
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.c
View File

@ -3386,6 +3386,7 @@ HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t Conversio
HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc)
{
uint32_t tickstart;
__IO uint32_t wait_loop_index = 0UL;
/* ADC enable and wait for ADC ready (in case of ADC is disabled or */
/* enabling phase not yet completed: flag ADC ready not yet set). */
@ -3409,6 +3410,25 @@ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc)
/* Enable the ADC peripheral */
LL_ADC_Enable(hadc->Instance);
if((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_TEMPSENSOR) != 0UL)
{
/* Delay for temperature sensor buffer stabilization time */
/* Note: Value LL_ADC_DELAY_TEMPSENSOR_STAB_US used instead of */
/* LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US because needed */
/* in case of ADC enable after a system wake up */
/* from low power mode. */
/* Wait loop initialization and execution */
/* Note: Variable divided by 2 to compensate partially */
/* CPU processing cycles, scaling in us split to not */
/* exceed 32 bits register capacity and handle low frequency. */
wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
while(wait_loop_index != 0UL)
{
wait_loop_index--;
}
}
/* Wait for ADC effectively enabled */
tickstart = HAL_GetTick();

43
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_can.c
View File

@ -226,8 +226,8 @@
#ifdef HAL_CAN_MODULE_ENABLED
#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
#error "The CAN driver cannot be used with its legacy, Please enable only one CAN module at once"
#endif
#error "The CAN driver cannot be used with its legacy, Please enable only one CAN module at once"
#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
@ -555,7 +555,8 @@ __weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan)
* @param pCallback pointer to the Callback function
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CAN_RegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID, void (* pCallback)(CAN_HandleTypeDef *_hcan))
HAL_StatusTypeDef HAL_CAN_RegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID,
void (* pCallback)(CAN_HandleTypeDef *_hcan))
{
HAL_StatusTypeDef status = HAL_OK;
@ -675,7 +676,7 @@ HAL_StatusTypeDef HAL_CAN_RegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_Call
/**
* @brief Unregister a CAN CallBack.
* CAN callabck is redirected to the weak predefined callback
* CAN callback is redirected to the weak predefined callback
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for CAN module
* @param CallbackID ID of the callback to be unregistered
@ -835,7 +836,7 @@ HAL_StatusTypeDef HAL_CAN_UnRegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_Ca
* contains the filter configuration information.
* @retval None
*/
HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDef *sFilterConfig)
HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, const CAN_FilterTypeDef *sFilterConfig)
{
uint32_t filternbrbitpos;
CAN_TypeDef *can_ip = hcan->Instance;
@ -1188,7 +1189,7 @@ HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan)
* - 0 : Sleep mode is not active.
* - 1 : Sleep mode is active.
*/
uint32_t HAL_CAN_IsSleepActive(CAN_HandleTypeDef *hcan)
uint32_t HAL_CAN_IsSleepActive(const CAN_HandleTypeDef *hcan)
{
uint32_t status = 0U;
HAL_CAN_StateTypeDef state = hcan->State;
@ -1219,7 +1220,8 @@ uint32_t HAL_CAN_IsSleepActive(CAN_HandleTypeDef *hcan)
* This parameter can be a value of @arg CAN_Tx_Mailboxes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderTypeDef *pHeader, uint8_t aData[], uint32_t *pTxMailbox)
HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, const CAN_TxHeaderTypeDef *pHeader,
const uint8_t aData[], uint32_t *pTxMailbox)
{
uint32_t transmitmailbox;
HAL_CAN_StateTypeDef state = hcan->State;
@ -1250,15 +1252,6 @@ HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderType
/* Select an empty transmit mailbox */
transmitmailbox = (tsr & CAN_TSR_CODE) >> CAN_TSR_CODE_Pos;
/* Check transmit mailbox value */
if (transmitmailbox > 2U)
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_INTERNAL;
return HAL_ERROR;
}
/* Store the Tx mailbox */
*pTxMailbox = (uint32_t)1 << transmitmailbox;
@ -1376,7 +1369,7 @@ HAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMai
* the configuration information for the specified CAN.
* @retval Number of free Tx Mailboxes.
*/
uint32_t HAL_CAN_GetTxMailboxesFreeLevel(CAN_HandleTypeDef *hcan)
uint32_t HAL_CAN_GetTxMailboxesFreeLevel(const CAN_HandleTypeDef *hcan)
{
uint32_t freelevel = 0U;
HAL_CAN_StateTypeDef state = hcan->State;
@ -1419,7 +1412,7 @@ uint32_t HAL_CAN_GetTxMailboxesFreeLevel(CAN_HandleTypeDef *hcan)
* - 1 : Pending transmission request on at least one of the selected
* Tx Mailbox.
*/
uint32_t HAL_CAN_IsTxMessagePending(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes)
uint32_t HAL_CAN_IsTxMessagePending(const CAN_HandleTypeDef *hcan, uint32_t TxMailboxes)
{
uint32_t status = 0U;
HAL_CAN_StateTypeDef state = hcan->State;
@ -1451,7 +1444,7 @@ uint32_t HAL_CAN_IsTxMessagePending(CAN_HandleTypeDef *hcan, uint32_t TxMailboxe
* This parameter can be one value of @arg CAN_Tx_Mailboxes.
* @retval Timestamp of message sent from Tx Mailbox.
*/
uint32_t HAL_CAN_GetTxTimestamp(CAN_HandleTypeDef *hcan, uint32_t TxMailbox)
uint32_t HAL_CAN_GetTxTimestamp(const CAN_HandleTypeDef *hcan, uint32_t TxMailbox)
{
uint32_t timestamp = 0U;
uint32_t transmitmailbox;
@ -1485,7 +1478,8 @@ uint32_t HAL_CAN_GetTxTimestamp(CAN_HandleTypeDef *hcan, uint32_t TxMailbox)
* @param aData array where the payload of the Rx frame will be stored.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[])
HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo,
CAN_RxHeaderTypeDef *pHeader, uint8_t aData[])
{
HAL_CAN_StateTypeDef state = hcan->State;
@ -1526,7 +1520,8 @@ HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo,
}
else
{
pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos;
pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) &
hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos;
}
pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR);
pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos;
@ -1575,7 +1570,7 @@ HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo,
* This parameter can be a value of @arg CAN_receive_FIFO_number.
* @retval Number of messages available in Rx FIFO.
*/
uint32_t HAL_CAN_GetRxFifoFillLevel(CAN_HandleTypeDef *hcan, uint32_t RxFifo)
uint32_t HAL_CAN_GetRxFifoFillLevel(const CAN_HandleTypeDef *hcan, uint32_t RxFifo)
{
uint32_t filllevel = 0U;
HAL_CAN_StateTypeDef state = hcan->State;
@ -2343,7 +2338,7 @@ __weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan)
* the configuration information for the specified CAN.
* @retval HAL state
*/
HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef *hcan)
HAL_CAN_StateTypeDef HAL_CAN_GetState(const CAN_HandleTypeDef *hcan)
{
HAL_CAN_StateTypeDef state = hcan->State;
@ -2378,7 +2373,7 @@ HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef *hcan)
* the configuration information for the specified CAN.
* @retval CAN Error Code
*/
uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan)
uint32_t HAL_CAN_GetError(const CAN_HandleTypeDef *hcan)
{
/* Return CAN error code */
return hcan->ErrorCode;

482
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c
View File

@ -438,10 +438,14 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t
/* Private functions for I2C transfer IRQ handler */
static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
uint32_t ITSources);
static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
uint32_t ITSources);
static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
uint32_t ITSources);
static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
uint32_t ITSources);
static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
uint32_t ITSources);
static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
uint32_t ITSources);
@ -2647,9 +2651,6 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
{
uint32_t tickstart;
uint32_t xfermode;
/* Check the parameters */
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
@ -2669,9 +2670,6 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
/* Process Locked */
__HAL_LOCK(hi2c);
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
hi2c->State = HAL_I2C_STATE_BUSY_TX;
hi2c->Mode = HAL_I2C_MODE_MEM;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
@ -2680,30 +2678,29 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->XferISR = I2C_Master_ISR_IT;
hi2c->XferISR = I2C_Mem_ISR_IT;
hi2c->Devaddress = DevAddress;
if (hi2c->XferCount > MAX_NBYTE_SIZE)
/* If Memory address size is 8Bit */
if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
xfermode = I2C_RELOAD_MODE;
/* Prefetch Memory Address */
hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
/* Reset Memaddress content */
hi2c->Memaddress = 0xFFFFFFFFU;
}
/* If Memory address size is 16Bit */
else
{
hi2c->XferSize = hi2c->XferCount;
xfermode = I2C_AUTOEND_MODE;
}
/* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
/* Prepare Memaddress buffer for LSB part */
hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
}
/* Send Slave Address and Memory Address */
if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart)
!= HAL_OK)
{
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_ERROR;
}
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@ -2741,9 +2738,6 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
{
uint32_t tickstart;
uint32_t xfermode;
/* Check the parameters */
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
@ -2763,9 +2757,6 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre
/* Process Locked */
__HAL_LOCK(hi2c);
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
hi2c->State = HAL_I2C_STATE_BUSY_RX;
hi2c->Mode = HAL_I2C_MODE_MEM;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
@ -2774,29 +2765,29 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->XferISR = I2C_Master_ISR_IT;
hi2c->XferISR = I2C_Mem_ISR_IT;
hi2c->Devaddress = DevAddress;
if (hi2c->XferCount > MAX_NBYTE_SIZE)
/* If Memory address size is 8Bit */
if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
xfermode = I2C_RELOAD_MODE;
/* Prefetch Memory Address */
hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
/* Reset Memaddress content */
hi2c->Memaddress = 0xFFFFFFFFU;
}
/* If Memory address size is 16Bit */
else
{
hi2c->XferSize = hi2c->XferCount;
xfermode = I2C_AUTOEND_MODE;
}
/* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
/* Prepare Memaddress buffer for LSB part */
hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
}
/* Send Slave Address and Memory Address */
if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
{
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_ERROR;
}
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@ -2809,7 +2800,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre
/* possible to enable all of these */
/* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
I2C_Enable_IRQ(hi2c, (I2C_XFER_TX_IT | I2C_XFER_RX_IT));
return HAL_OK;
}
@ -2833,8 +2824,6 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre
HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
{
uint32_t tickstart;
uint32_t xfermode;
HAL_StatusTypeDef dmaxferstatus;
/* Check the parameters */
@ -2856,9 +2845,6 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
/* Process Locked */
__HAL_LOCK(hi2c);
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
hi2c->State = HAL_I2C_STATE_BUSY_TX;
hi2c->Mode = HAL_I2C_MODE_MEM;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
@ -2867,28 +2853,36 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->XferISR = I2C_Master_ISR_DMA;
hi2c->XferISR = I2C_Mem_ISR_DMA;
hi2c->Devaddress = DevAddress;
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
xfermode = I2C_RELOAD_MODE;
}
else
{
hi2c->XferSize = hi2c->XferCount;
xfermode = I2C_AUTOEND_MODE;
}
/* Send Slave Address and Memory Address */
if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart)
!= HAL_OK)
/* If Memory address size is 8Bit */
if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
{
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_ERROR;
}
/* Prefetch Memory Address */
hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
/* Reset Memaddress content */
hi2c->Memaddress = 0xFFFFFFFFU;
}
/* If Memory address size is 16Bit */
else
{
/* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
/* Prepare Memaddress buffer for LSB part */
hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
}
if (hi2c->hdmatx != NULL)
{
@ -2923,12 +2917,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
if (dmaxferstatus == HAL_OK)
{
/* Send Slave Address */
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
/* Update XferCount value */
hi2c->XferCount -= hi2c->XferSize;
/* Send Slave Address and Memory Address */
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@ -2936,11 +2926,11 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
/* Note : The I2C interrupts must be enabled after unlocking current process
to avoid the risk of I2C interrupt handle execution before current
process unlock */
/* Enable ERR and NACK interrupts */
I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
/* Enable DMA Request */
hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
/* Enable ERR, TC, STOP, NACK, TXI interrupt */
/* possible to enable all of these */
/* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
}
else
{
@ -2980,8 +2970,6 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
{
uint32_t tickstart;
uint32_t xfermode;
HAL_StatusTypeDef dmaxferstatus;
/* Check the parameters */
@ -3003,9 +2991,6 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
/* Process Locked */
__HAL_LOCK(hi2c);
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
hi2c->State = HAL_I2C_STATE_BUSY_RX;
hi2c->Mode = HAL_I2C_MODE_MEM;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
@ -3014,25 +2999,35 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->XferISR = I2C_Master_ISR_DMA;
hi2c->XferISR = I2C_Mem_ISR_DMA;
hi2c->Devaddress = DevAddress;
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
xfermode = I2C_RELOAD_MODE;
}
else
{
hi2c->XferSize = hi2c->XferCount;
xfermode = I2C_AUTOEND_MODE;
}
/* Send Slave Address and Memory Address */
if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
/* If Memory address size is 8Bit */
if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
{
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_ERROR;
/* Prefetch Memory Address */
hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
/* Reset Memaddress content */
hi2c->Memaddress = 0xFFFFFFFFU;
}
/* If Memory address size is 16Bit */
else
{
/* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
/* Prepare Memaddress buffer for LSB part */
hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
}
if (hi2c->hdmarx != NULL)
@ -3068,11 +3063,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
if (dmaxferstatus == HAL_OK)
{
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
/* Update XferCount value */
hi2c->XferCount -= hi2c->XferSize;
/* Send Slave Address and Memory Address */
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@ -3080,11 +3072,11 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
/* Note : The I2C interrupts must be enabled after unlocking current process
to avoid the risk of I2C interrupt handle execution before current
process unlock */
/* Enable ERR and NACK interrupts */
I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
/* Enable DMA Request */
hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
/* Enable ERR, TC, STOP, NACK, TXI interrupt */
/* possible to enable all of these */
/* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
}
else
{
@ -3327,6 +3319,10 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16
/* Note : The I2C interrupts must be enabled after unlocking current process
to avoid the risk of I2C interrupt handle execution before current
process unlock */
/* Enable ERR, TC, STOP, NACK, TXI interrupt */
/* possible to enable all of these */
/* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
return HAL_OK;
@ -4878,6 +4874,143 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin
return HAL_OK;
}
/**
* @brief Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with Interrupt.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param ITFlags Interrupt flags to handle.
* @param ITSources Interrupt sources enabled.
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
uint32_t ITSources)
{
uint32_t direction = I2C_GENERATE_START_WRITE;
uint32_t tmpITFlags = ITFlags;
/* Process Locked */
__HAL_LOCK(hi2c);
if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
{
/* Clear NACK Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
/* Set corresponding Error Code */
/* No need to generate STOP, it is automatically done */
/* Error callback will be send during stop flag treatment */
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
/* Flush TX register */
I2C_Flush_TXDR(hi2c);
}
else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
{
/* Remove RXNE flag on temporary variable as read done */
tmpITFlags &= ~I2C_FLAG_RXNE;
/* Read data from RXDR */
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
hi2c->XferSize--;
hi2c->XferCount--;
}
else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
{
if (hi2c->Memaddress == 0xFFFFFFFFU)
{
/* Write data to TXDR */
hi2c->Instance->TXDR = *hi2c->pBuffPtr;
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
hi2c->XferSize--;
hi2c->XferCount--;
}
else
{
/* Write LSB part of Memory Address */
hi2c->Instance->TXDR = hi2c->Memaddress;
/* Reset Memaddress content */
hi2c->Memaddress = 0xFFFFFFFFU;
}
}
else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
{
if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
{
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
}
else
{
hi2c->XferSize = hi2c->XferCount;
I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
}
}
else
{
/* Wrong size Status regarding TCR flag event */
/* Call the corresponding callback to inform upper layer of End of Transfer */
I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
}
}
else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
{
if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
{
direction = I2C_GENERATE_START_READ;
}
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
I2C_RELOAD_MODE, direction);
}
else
{
hi2c->XferSize = hi2c->XferCount;
/* Set NBYTES to write and generate RESTART */
I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
I2C_AUTOEND_MODE, direction);
}
}
else
{
/* Nothing to do */
}
if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
{
/* Call I2C Master complete process */
I2C_ITMasterCplt(hi2c, tmpITFlags);
}
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_OK;
}
/**
* @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
@ -5159,6 +5292,145 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui
return HAL_OK;
}
/**
* @brief Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with DMA.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param ITFlags Interrupt flags to handle.
* @param ITSources Interrupt sources enabled.
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
uint32_t ITSources)
{
uint32_t direction = I2C_GENERATE_START_WRITE;
/* Process Locked */
__HAL_LOCK(hi2c);
if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
{
/* Clear NACK Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
/* Set corresponding Error Code */
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
/* No need to generate STOP, it is automatically done */
/* But enable STOP interrupt, to treat it */
/* Error callback will be send during stop flag treatment */
I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
/* Flush TX register */
I2C_Flush_TXDR(hi2c);
}
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TXIS) != RESET) && \
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
{
/* Write LSB part of Memory Address */
hi2c->Instance->TXDR = hi2c->Memaddress;
/* Reset Memaddress content */
hi2c->Memaddress = 0xFFFFFFFFU;
}
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
{
/* Enable only Error interrupt */
I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
if (hi2c->XferCount != 0U)
{
/* Prepare the new XferSize to transfer */
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
}
else
{
hi2c->XferSize = hi2c->XferCount;
I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
}
/* Update XferCount value */
hi2c->XferCount -= hi2c->XferSize;
/* Enable DMA Request */
if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
{
hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
}
else
{
hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
}
}
else
{
/* Wrong size Status regarding TCR flag event */
/* Call the corresponding callback to inform upper layer of End of Transfer */
I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
}
}
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
{
if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
{
direction = I2C_GENERATE_START_READ;
}
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
I2C_RELOAD_MODE, direction);
}
else
{
hi2c->XferSize = hi2c->XferCount;
/* Set NBYTES to write and generate RESTART */
I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
I2C_AUTOEND_MODE, direction);
}
/* Update XferCount value */
hi2c->XferCount -= hi2c->XferSize;
/* Enable DMA Request */
if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
{
hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
}
else
{
hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
}
}
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
{
/* Call I2C Master complete process */
I2C_ITMasterCplt(hi2c, ITFlags);
}
else
{
/* Nothing to do */
}
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_OK;
}
/**
* @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
@ -6575,11 +6847,11 @@ static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t T
{
/* Generate Stop */
hi2c->Instance->CR2 |= I2C_CR2_STOP;
/* Update Tick with new reference */
tickstart = HAL_GetTick();
}
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
{
/* Check for the Timeout */
@ -6588,10 +6860,10 @@ static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t T
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
status = HAL_ERROR;
}
}
@ -6696,14 +6968,14 @@ static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uin
/* Declaration of tmp to prevent undefined behavior of volatile usage */
uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
(((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
(uint32_t)Mode | (uint32_t)Request) & (~0x80000000U));
(((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
(uint32_t)Mode | (uint32_t)Request) & (~0x80000000U));
/* update CR2 register */
MODIFY_REG(hi2c->Instance->CR2, \
((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \
(I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | \
I2C_CR2_START | I2C_CR2_STOP)), tmp);
I2C_CR2_START | I2C_CR2_STOP)), tmp);
}
/**
@ -6764,6 +7036,12 @@ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
}
if (InterruptRequest == I2C_XFER_ERROR_IT)
{
/* Enable ERR and NACK interrupts */
tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
}
if (InterruptRequest == I2C_XFER_CPLT_IT)
{
/* Enable STOP interrupts */

8
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c
View File

@ -187,7 +187,7 @@ void HAL_PWR_DisableBkUpAccess(void)
=========================================
[..]
(+) Entry:
The Sleep mode / Low-power Sleep mode is entered through HAL_PWR_EnterSLEEPMode() API
The Sleep mode / Low-power Sleep mode is entered thru HAL_PWR_EnterSLEEPMode() API
in specifying whether or not the regulator is forced to low-power mode and if exit is interrupt or event-triggered.
(++) PWR_MAINREGULATOR_ON: Sleep mode (regulator in main mode).
(++) PWR_LOWPOWERREGULATOR_ON: Low-power sleep (regulator in low power mode).
@ -209,7 +209,7 @@ void HAL_PWR_DisableBkUpAccess(void)
===============================
[..]
(+) Entry:
The Stop 0, Stop 1 or Stop 2 modes are entered through the following API's:
The Stop 0, Stop 1 or Stop 2 modes are entered thru the following API's:
(++) HAL_PWREx_EnterSTOP0Mode() for mode 0 or HAL_PWREx_EnterSTOP1Mode() for mode 1 or for porting reasons HAL_PWR_EnterSTOPMode().
(++) HAL_PWREx_EnterSTOP2Mode() for mode 2.
(+) Regulator setting (applicable to HAL_PWR_EnterSTOPMode() only):
@ -243,7 +243,7 @@ void HAL_PWR_DisableBkUpAccess(void)
and Standby circuitry.
(++) Entry:
(+++) The Standby mode is entered through HAL_PWR_EnterSTANDBYMode() API.
(+++) The Standby mode is entered thru HAL_PWR_EnterSTANDBYMode() API.
SRAM1 and register contents are lost except for registers in the Backup domain and
Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register.
To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetention() API
@ -264,7 +264,7 @@ void HAL_PWR_DisableBkUpAccess(void)
SRAM and registers contents are lost except for backup domain registers.
(+) Entry:
The Shutdown mode is entered through HAL_PWREx_EnterSHUTDOWNMode() API.
The Shutdown mode is entered thru HAL_PWREx_EnterSHUTDOWNMode() API.
(+) Exit:
(++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event,

4
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c
View File

@ -272,7 +272,7 @@ HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
/**
* @brief Enable battery charging.
* When VDD is present, charge the external battery on VBAT through an internal resistor.
* When VDD is present, charge the external battery on VBAT thru an internal resistor.
* @param ResistorSelection specifies the resistor impedance.
* This parameter can be one of the following values:
* @arg @ref PWR_BATTERY_CHARGING_RESISTOR_5 5 kOhms resistor
@ -974,7 +974,7 @@ HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM)
/* Configure EXTI 35 to 38 interrupts if so required:
scan through PVMType to detect which PVMx is set and
scan thru PVMType to detect which PVMx is set and
configure the corresponding EXTI line accordingly. */
switch (sConfigPVM->PVMType)
{

124
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c
View File

@ -1012,29 +1012,6 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
/* Disable all PLL outputs to save power if no PLLs on */
#if defined(RCC_PLLSAI1_SUPPORT) && defined(RCC_CR_PLLSAI2RDY)
if(READ_BIT(RCC->CR, (RCC_CR_PLLSAI1RDY | RCC_CR_PLLSAI2RDY)) == 0U)
{
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, RCC_PLLSOURCE_NONE);
}
#elif defined(RCC_PLLSAI1_SUPPORT)
if(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == 0U)
{
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, RCC_PLLSOURCE_NONE);
}
#else
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, RCC_PLLSOURCE_NONE);
#endif /* RCC_PLLSAI1_SUPPORT && RCC_CR_PLLSAI2RDY */
#if defined(RCC_PLLSAI2_SUPPORT)
__HAL_RCC_PLLCLKOUT_DISABLE(RCC_PLL_SYSCLK | RCC_PLL_48M1CLK | RCC_PLL_SAI3CLK);
#elif defined(RCC_PLLSAI1_SUPPORT)
__HAL_RCC_PLLCLKOUT_DISABLE(RCC_PLL_SYSCLK | RCC_PLL_48M1CLK | RCC_PLL_SAI2CLK);
#else
__HAL_RCC_PLLCLKOUT_DISABLE(RCC_PLL_SYSCLK | RCC_PLL_48M1CLK);
#endif /* RCC_PLLSAI2_SUPPORT */
/* Get Start Tick*/
tickstart = HAL_GetTick();
@ -1046,6 +1023,14 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
return HAL_TIMEOUT;
}
}
/* Unselect main PLL clock source and disable main PLL outputs to save power */
#if defined(RCC_PLLSAI2_SUPPORT)
RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLSRC | RCC_PLL_SYSCLK | RCC_PLL_48M1CLK | RCC_PLL_SAI3CLK);
#elif defined(RCC_PLLSAI1_SUPPORT)
RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLSRC | RCC_PLL_SYSCLK | RCC_PLL_48M1CLK | RCC_PLL_SAI2CLK);
#else
RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLSRC | RCC_PLL_SYSCLK | RCC_PLL_48M1CLK);
#endif /* RCC_PLLSAI2_SUPPORT */
}
else
{
@ -1144,6 +1129,18 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
}
}
/*----------------- HCLK Configuration prior to SYSCLK----------------------*/
/* Apply higher HCLK prescaler request here to ensure CPU clock is not of of spec when SYSCLK is increased */
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
{
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
if(RCC_ClkInitStruct->AHBCLKDivider > READ_BIT(RCC->CFGR, RCC_CFGR_HPRE))
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
}
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
{
@ -1163,22 +1160,12 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
/* Compute target PLL output frequency */
if(RCC_GetSysClockFreqFromPLLSource() > 80000000U)
{
/* If lowest HCLK prescaler, apply intermediate step with HCLK prescaler 2 necessary before to go over 80Mhz */
if(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1)
{
/* Intermediate step with HCLK prescaler 2 necessary before to go over 80Mhz */
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2);
hpre = RCC_SYSCLK_DIV2;
}
else if((((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) && (RCC_ClkInitStruct->AHBCLKDivider == RCC_SYSCLK_DIV1))
{
/* Intermediate step with HCLK prescaler 2 necessary before to go over 80Mhz */
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2);
hpre = RCC_SYSCLK_DIV2;
}
else
{
/* nothing to do */
}
}
#endif
}
@ -1216,9 +1203,12 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
/* Overshoot management when going down from PLL as SYSCLK source and frequency above 80Mhz */
if(HAL_RCC_GetSysClockFreq() > 80000000U)
{
/* Intermediate step with HCLK prescaler 2 necessary before to go under 80Mhz */
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2);
hpre = RCC_SYSCLK_DIV2;
/* If lowest HCLK prescaler, apply intermediate step with HCLK prescaler 2 necessary before to go under 80Mhz */
if(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1)
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2);
hpre = RCC_SYSCLK_DIV2;
}
}
#endif
@ -1238,25 +1228,26 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
}
}
/*-------------------------- HCLK Configuration --------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
{
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
}
#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || \
defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
else
/* Is intermediate HCLK prescaler 2 applied internally, resume with HCLK prescaler 1 */
if(hpre == RCC_SYSCLK_DIV2)
{
/* Is intermediate HCLK prescaler 2 applied internally, complete with HCLK prescaler 1 */
if(hpre == RCC_SYSCLK_DIV2)
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV1);
}
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV1);
}
#endif
/* Decreasing the number of wait states because of lower CPU frequency */
/*----------------- HCLK Configuration after SYSCLK-------------------------*/
/* Apply lower HCLK prescaler request here to ensure CPU clock is not of of spec when SYSCLK is set */
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
{
if(RCC_ClkInitStruct->AHBCLKDivider < READ_BIT(RCC->CFGR, RCC_CFGR_HPRE))
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
}
}
/* Allow decreasing of the number of wait states (because of lower CPU frequency expected) */
if(FLatency < __HAL_FLASH_GET_LATENCY())
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
@ -1886,23 +1877,7 @@ static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange)
*/
static uint32_t RCC_GetSysClockFreqFromPLLSource(void)
{
uint32_t msirange = 0U;
uint32_t pllvco, pllsource, pllr, pllm, sysclockfreq; /* no init needed */
if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_MSI)
{
/* Get MSI range source */
if(READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == 0U)
{ /* MSISRANGE from RCC_CSR applies */
msirange = READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> RCC_CSR_MSISRANGE_Pos;
}
else
{ /* MSIRANGE from RCC_CR applies */
msirange = READ_BIT(RCC->CR, RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos;
}
/*MSI frequency range in HZ*/
msirange = MSIRangeTable[msirange];
}
uint32_t msirange, pllvco, pllsource, pllr, pllm, sysclockfreq; /* no init needed */
/* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE) * PLLN / PLLM
SYSCLK = PLL_VCO / PLLR
@ -1920,8 +1895,21 @@ static uint32_t RCC_GetSysClockFreqFromPLLSource(void)
break;
case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */
/* Get MSI range source */
if(READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == 0U)
{ /* MSISRANGE from RCC_CSR applies */
msirange = READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> RCC_CSR_MSISRANGE_Pos;
}
else
{ /* MSIRANGE from RCC_CR applies */
msirange = READ_BIT(RCC->CR, RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos;
}
/*MSI frequency range in HZ*/
pllvco = MSIRangeTable[msirange];
break;
default:
pllvco = msirange;
/* unexpected */
pllvco = 0;
break;
}
pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ;

2
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c
View File

@ -3311,7 +3311,7 @@ static uint32_t RCCEx_GetSAIxPeriphCLKFreq(uint32_t PeriphClk, uint32_t InputFre
uint32_t pllp = 0U;
#endif /* RCC_PLLP_SUPPORT */
/* Handle SAIx */
/* Handle SAIs */
if(PeriphClk == RCC_PERIPHCLK_SAI1)
{
srcclk = __HAL_RCC_GET_SAI1_SOURCE();

94
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c
View File

@ -205,11 +205,11 @@ all interrupt callbacks are set to the corresponding weak functions:
/** @addtogroup TIM_Private_Functions
* @{
*/
static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
uint32_t TIM_ICFilter);
@ -225,7 +225,7 @@ static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma);
static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
TIM_SlaveConfigTypeDef *sSlaveConfig);
const TIM_SlaveConfigTypeDef *sSlaveConfig);
/**
* @}
*/
@ -278,6 +278,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
assert_param(IS_TIM_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
@ -525,7 +526,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
* @param Length The length of data to be transferred from memory to peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length)
{
uint32_t tmpsmcr;
@ -539,7 +540,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat
}
else if (htim->State == HAL_TIM_STATE_READY)
{
if ((pData == NULL) && (Length > 0U))
if ((pData == NULL) || (Length == 0U))
{
return HAL_ERROR;
}
@ -661,6 +662,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim)
assert_param(IS_TIM_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
@ -1050,7 +1052,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
* @param Length The length of data to be transferred from memory to TIM peripheral
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
uint16_t Length)
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t tmpsmcr;
@ -1065,7 +1068,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
}
else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
{
if ((pData == NULL) && (Length > 0U))
if ((pData == NULL) || (Length == 0U))
{
return HAL_ERROR;
}
@ -1328,6 +1331,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
assert_param(IS_TIM_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
@ -1717,7 +1721,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
* @param Length The length of data to be transferred from memory to TIM peripheral
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
uint16_t Length)
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t tmpsmcr;
@ -1732,7 +1737,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe
}
else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
{
if ((pData == NULL) && (Length > 0U))
if ((pData == NULL) || (Length == 0U))
{
return HAL_ERROR;
}
@ -1994,6 +1999,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
assert_param(IS_TIM_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
@ -2387,7 +2393,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY)
&& (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY))
{
if ((pData == NULL) && (Length > 0U))
if ((pData == NULL) || (Length == 0U))
{
return HAL_ERROR;
}
@ -2643,6 +2649,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePul
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_OPM_MODE(OnePulseMode));
assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
@ -3046,6 +3053,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini
assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
if (htim->State == HAL_TIM_STATE_RESET)
{
@ -3555,7 +3563,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch
else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
&& (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
{
if ((pData1 == NULL) && (Length > 0U))
if ((pData1 == NULL) || (Length == 0U))
{
return HAL_ERROR;
}
@ -3580,7 +3588,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch
else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
&& (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
{
if ((pData2 == NULL) && (Length > 0U))
if ((pData2 == NULL) || (Length == 0U))
{
return HAL_ERROR;
}
@ -3609,7 +3617,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch
&& (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
&& (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
{
if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U))
if ((((pData1 == NULL) || (pData2 == NULL))) || (Length == 0U))
{
return HAL_ERROR;
}
@ -4054,7 +4062,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
TIM_OC_InitTypeDef *sConfig,
const TIM_OC_InitTypeDef *sConfig,
uint32_t Channel)
{
HAL_StatusTypeDef status = HAL_OK;
@ -4152,7 +4160,7 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
{
HAL_StatusTypeDef status = HAL_OK;
@ -4254,7 +4262,7 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
TIM_OC_InitTypeDef *sConfig,
const TIM_OC_InitTypeDef *sConfig,
uint32_t Channel)
{
HAL_StatusTypeDef status = HAL_OK;
@ -4556,7 +4564,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength)
{
HAL_StatusTypeDef status;
@ -4614,7 +4622,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
uint32_t BurstLength, uint32_t DataLength)
{
HAL_StatusTypeDef status = HAL_OK;
@ -5269,7 +5277,7 @@ HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventS
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
TIM_ClearInputConfigTypeDef *sClearInputConfig,
const TIM_ClearInputConfigTypeDef *sClearInputConfig,
uint32_t Channel)
{
HAL_StatusTypeDef status = HAL_OK;
@ -5435,7 +5443,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
* contains the clock source information for the TIM peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig)
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t tmpsmcr;
@ -5621,7 +5629,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_S
* (Disable, Reset, Gated, Trigger, External clock mode 1).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig)
{
/* Check the parameters */
assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
@ -5662,7 +5670,7 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveC
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim,
TIM_SlaveConfigTypeDef *sSlaveConfig)
const TIM_SlaveConfigTypeDef *sSlaveConfig)
{
/* Check the parameters */
assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
@ -5704,7 +5712,7 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim,
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval Captured value
*/
uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel)
{
uint32_t tmpreg = 0U;
@ -6492,7 +6500,7 @@ HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Ca
* @param htim TIM Base handle
* @retval HAL state
*/
HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim)
{
return htim->State;
}
@ -6502,7 +6510,7 @@ HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
* @param htim TIM Output Compare handle
* @retval HAL state
*/
HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim)
{
return htim->State;
}
@ -6512,7 +6520,7 @@ HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
* @param htim TIM handle
* @retval HAL state
*/
HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim)
{
return htim->State;
}
@ -6522,7 +6530,7 @@ HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
* @param htim TIM IC handle
* @retval HAL state
*/
HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim)
{
return htim->State;
}
@ -6532,7 +6540,7 @@ HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
* @param htim TIM OPM handle
* @retval HAL state
*/
HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim)
{
return htim->State;
}
@ -6542,7 +6550,7 @@ HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
* @param htim TIM Encoder Interface handle
* @retval HAL state
*/
HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim)
{
return htim->State;
}
@ -6552,7 +6560,7 @@ HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
* @param htim TIM handle
* @retval Active channel
*/
HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim)
HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim)
{
return htim->Channel;
}
@ -6570,7 +6578,7 @@ HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim)
* @arg TIM_CHANNEL_6: TIM Channel 6
* @retval TIM Channel state
*/
HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channel)
{
HAL_TIM_ChannelStateTypeDef channel_state;
@ -6587,7 +6595,7 @@ HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, ui
* @param htim TIM handle
* @retval DMA burst state
*/
HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim)
HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim)
{
/* Check the parameters */
assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
@ -6930,7 +6938,7 @@ static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma)
* @param Structure TIM Base configuration structure
* @retval None
*/
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
{
uint32_t tmpcr1;
tmpcr1 = TIMx->CR1;
@ -6978,7 +6986,7 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
uint32_t tmpccmrx;
uint32_t tmpccer;
@ -7053,7 +7061,7 @@ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
* @param OC_Config The output configuration structure
* @retval None
*/
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
uint32_t tmpccmrx;
uint32_t tmpccer;
@ -7129,7 +7137,7 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
uint32_t tmpccmrx;
uint32_t tmpccer;
@ -7203,7 +7211,7 @@ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
uint32_t tmpccmrx;
uint32_t tmpccer;
@ -7264,7 +7272,7 @@ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
* @retval None
*/
static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
TIM_OC_InitTypeDef *OC_Config)
const TIM_OC_InitTypeDef *OC_Config)
{
uint32_t tmpccmrx;
uint32_t tmpccer;
@ -7317,7 +7325,7 @@ static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
* @retval None
*/
static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
TIM_OC_InitTypeDef *OC_Config)
const TIM_OC_InitTypeDef *OC_Config)
{
uint32_t tmpccmrx;
uint32_t tmpccer;
@ -7371,7 +7379,7 @@ static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
* @retval None
*/
static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
TIM_SlaveConfigTypeDef *sSlaveConfig)
const TIM_SlaveConfigTypeDef *sSlaveConfig)
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t tmpsmcr;

25
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c
View File

@ -137,7 +137,7 @@ static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Cha
* @param sConfig TIM Hall Sensor configuration structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig)
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeDef *sConfig)
{
TIM_OC_InitTypeDef OC_Config;
@ -153,6 +153,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSen
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
@ -503,7 +504,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32
else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
&& (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
{
if ((pData == NULL) && (Length > 0U))
if ((pData == NULL) || (Length == 0U))
{
return HAL_ERROR;
}
@ -868,7 +869,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe
* @param Length The length of data to be transferred from memory to TIM peripheral
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
uint16_t Length)
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t tmpsmcr;
@ -883,7 +885,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
}
else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
{
if ((pData == NULL) && (Length > 0U))
if ((pData == NULL) || (Length == 0U))
{
return HAL_ERROR;
}
@ -1349,7 +1351,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chann
* @param Length The length of data to be transferred from memory to TIM peripheral
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
uint16_t Length)
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t tmpsmcr;
@ -1364,7 +1367,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
}
else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
{
if ((pData == NULL) && (Length > 0U))
if ((pData == NULL) || (Length == 0U))
{
return HAL_ERROR;
}
@ -1963,7 +1966,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint3
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
TIM_MasterConfigTypeDef *sMasterConfig)
const TIM_MasterConfigTypeDef *sMasterConfig)
{
uint32_t tmpcr2;
uint32_t tmpsmcr;
@ -2036,7 +2039,7 @@ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
{
/* Keep this variable initialized to 0 as it is used to configure BDTR register */
uint32_t tmpbdtr = 0U;
@ -2101,7 +2104,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
*/
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim,
uint32_t BreakInput,
TIMEx_BreakInputConfigTypeDef *sBreakInputConfig)
const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig)
{
HAL_StatusTypeDef status = HAL_OK;
@ -2625,7 +2628,7 @@ __weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)
* @param htim TIM Hall Sensor handle
* @retval HAL state
*/
HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim)
{
return htim->State;
}
@ -2640,7 +2643,7 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
* @arg TIM_CHANNEL_3: TIM Channel 3
* @retval TIM Complementary channel state
*/
HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN)
HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim, uint32_t ChannelN)
{
HAL_TIM_ChannelStateTypeDef channel_state;