Bug Fixes
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42
PeltierControllerV3 Debug.cfg
Normal file
42
PeltierControllerV3 Debug.cfg
Normal file
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# This is an genericBoard board with a single STM32L432KBUx chip
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#
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# Generated by STM32CubeIDE
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# Take care that such file, as generated, may be overridden without any early notice. Please have a look to debug launch configuration setup(s)
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source [find interface/stlink-dap.cfg]
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set WORKAREASIZE 0x4000
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transport select "dapdirect_swd"
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set CHIPNAME STM32L432KBUx
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set BOARDNAME genericBoard
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# Enable debug when in low power modes
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set ENABLE_LOW_POWER 1
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# Stop Watchdog counters when halt
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set STOP_WATCHDOG 1
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# STlink Debug clock frequency
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set CLOCK_FREQ 8000
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# Reset configuration
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# use hardware reset, connect under reset
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# connect_assert_srst needed if low power mode application running (WFI...)
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reset_config srst_only srst_nogate connect_assert_srst
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set CONNECT_UNDER_RESET 1
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set CORE_RESET 0
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# ACCESS PORT NUMBER
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set AP_NUM 0
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# GDB PORT
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set GDB_PORT 3333
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# BCTM CPU variables
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source [find target/stm32l4x.cfg]
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