diff --git a/Changelog.md b/Changelog.md
index d28e462..681d1f4 100644
--- a/Changelog.md
+++ b/Changelog.md
@@ -1,3 +1,7 @@
+## 1.2.2.
+* Bugfixes
+  * Workaround for ISE tools implementing memory as FFs in case of 1 stream
+
 ## 1.2.1
 * Bugfixes
   * Optimized timing between input FIFO and DMA
diff --git a/hdl/psi_ms_daq_axi.vhd b/hdl/psi_ms_daq_axi.vhd
index 529faba..8445945 100644
--- a/hdl/psi_ms_daq_axi.vhd
+++ b/hdl/psi_ms_daq_axi.vhd
@@ -398,7 +398,7 @@ begin
 			AxiDataWidth_g			=> AxiDataWidth_g,
 			AxiMaxBeats_g			=> AxiMaxBurstBeats_g,
 			AxiMaxOpenTrasactions_g	=> AxiMaxOpenTrasactions_g,
-			MaxOpenCommands_g		=> Streams_g,
+			MaxOpenCommands_g		=> max(2, Streams_g), -- ISE tools implement memory as FFs for one stream. Reason is unkown, so we always implement two streams for resource optimization reasons.
 			DataFifoDepth_g			=> 1024,
 			AxiFifoDepth_g			=> AxiFifoDepth_g,
 			RamBehavior_g			=> "RBW" -- Okay for Xilinx chips