diff --git a/doc/psi_multi_stream_daq.docx b/doc/psi_multi_stream_daq.docx index 5115efe..16f7ad4 100644 Binary files a/doc/psi_multi_stream_daq.docx and b/doc/psi_multi_stream_daq.docx differ diff --git a/doc/psi_multi_stream_daq.pdf b/doc/psi_multi_stream_daq.pdf index 4b61b39..4125272 100644 Binary files a/doc/psi_multi_stream_daq.pdf and b/doc/psi_multi_stream_daq.pdf differ diff --git a/hdl/psi_ms_daq_axi.vhd b/hdl/psi_ms_daq_axi.vhd index 78ef90f..828392a 100644 --- a/hdl/psi_ms_daq_axi.vhd +++ b/hdl/psi_ms_daq_axi.vhd @@ -174,12 +174,13 @@ architecture rtl of psi_ms_daq_axi is signal MemSm_Done : std_logic; -- Configuration - signal Cfg_StrEna : std_logic_vector(Streams_g - 1 downto 0); - signal Cfg_GlbEna : std_logic; - signal Cfg_PostTrig : t_aslv32(Streams_g - 1 downto 0); - signal Cfg_Arm : std_logic_vector(Streams_g - 1 downto 0); - signal Cfg_RecMode : t_aslv2(Streams_g - 1 downto 0); - + signal Cfg_StrEna : std_logic_vector(Streams_g - 1 downto 0); + signal Cfg_GlbEna : std_logic; + signal Cfg_PostTrig : t_aslv32(Streams_g - 1 downto 0); + signal Cfg_Arm : std_logic_vector(Streams_g - 1 downto 0); + signal Cfg_RecMode : t_aslv2(Streams_g - 1 downto 0); + signal Cfg_ToDisable : std_logic_vector(Streams_g -1 downto 0); + signal Cfg_FrameTo : std_logic_vector(Streams_g -1 downto 0); -- Status signal Stat_StrIrq : std_logic_vector(Streams_g - 1 downto 0); signal Stat_StrLastWin : WinType_a(Streams_g - 1 downto 0); @@ -204,7 +205,7 @@ begin -------------------------------------------- -- Register Interface - -------------------------------------------- + -------------------------------------------- i_reg : entity work.psi_ms_daq_reg_axi generic map( Streams_g => Streams_g, @@ -255,6 +256,8 @@ begin IsArmed => Stat_IsArmed, IsRecording => Stat_IsRecording, RecMode => Cfg_RecMode, + ToDisable => Cfg_ToDisable, + FrameTo => Cfg_FrameTo, ClkMem => M_Axi_Aclk, RstMem => M_Axi_Areset, CtxStr_Cmd => CtxStr_Cmd, @@ -270,7 +273,7 @@ begin -------------------------------------------- -- Input Logic Instantiation - -------------------------------------------- + -------------------------------------------- g_input : for str in 0 to Streams_g - 1 generate signal InRst : std_logic; signal StrInput : std_logic_vector(StreamWidth_c(str) - 1 downto 0); @@ -303,6 +306,8 @@ begin Arm => Cfg_Arm(str), IsArmed => Stat_IsArmed(str), IsRecording => Stat_IsRecording(str), + ToDisable => Cfg_ToDisable(str), + FrameTo => Cfg_FrameTo(str), ClkMem => M_Axi_Aclk, RstMem => InRst, Daq_Vld => InpDma_Vld(str), @@ -359,7 +364,7 @@ begin -------------------------------------------- -- DMA Engine - -------------------------------------------- + -------------------------------------------- i_dma : entity work.psi_ms_daq_daq_dma generic map( Streams_g => Streams_g @@ -387,7 +392,7 @@ begin -------------------------------------------- -- Memory Interface - -------------------------------------------- + -------------------------------------------- i_memif : entity work.psi_ms_daq_axi_if generic map( AxiDataWidth_g => AxiDataWidth_g, @@ -443,4 +448,3 @@ begin ); end; - diff --git a/hdl/psi_ms_daq_input.vhd b/hdl/psi_ms_daq_input.vhd index 53ce32c..d014c0d 100644 --- a/hdl/psi_ms_daq_input.vhd +++ b/hdl/psi_ms_daq_input.vhd @@ -51,7 +51,9 @@ entity psi_ms_daq_input is Mode : in RecMode_t; -- $$ proc=daq $$ Arm : in std_logic; -- $$ proc=stream $$ IsArmed : out std_logic; -- $$ proc=stream $$ - IsRecording : out std_logic; -- $$ proc=stream $$ + IsRecording : out std_logic; -- $$ proc=stream $$ + ToDisable : in std_logic; -- $$ proc=stream $$ + FrameTo : in std_logic; -- $$ proc=stream $$ -- DAQ control signals ClkMem : in std_logic; -- $$ type=clk; freq=200e6; proc=daq,stream $$ @@ -104,6 +106,7 @@ architecture rtl of psi_ms_daq_input is HasTlastSync : std_logic_vector(0 to 1); IsArmed : std_logic; RecEna : std_logic; + FrameInProgr : std_logic; end record; signal r, r_next : two_process_r; @@ -143,6 +146,8 @@ architecture rtl of psi_ms_daq_input is signal Arm_Sync : std_logic; signal RstReg_Sync : std_logic; signal RstAcq_Sync : std_logic; + signal ToDisable_Sync : std_logic; + signal FrameTo_Sync : std_logic; begin -------------------------------------------- @@ -233,8 +238,17 @@ begin end if; end if; - -- Detect Timeout + -- Frame in progress if Str_Vld = '1' then + if Str_Trig = '1' then + v.FrameInProgr := '0'; + else + v.FrameInProgr := '1'; + end if; + end if; + + -- Detect Timeout + if Str_Vld = '1' or ToDisable_Sync = '1' or (FrameTo_Sync = '1' or r.FrameInProgr = '0') then v.TimeoutCnt := 0; else if r.TimeoutCnt = TimeoutLimit_c then @@ -336,6 +350,7 @@ begin r.IsArmed <= '0'; r.RecEna <= '0'; r.ArmReg <= '0'; + r.FrameInProgr <= '0'; end if; end if; end process; @@ -389,17 +404,21 @@ begin -- *** Register Interface clock crossings *** i_cc_reg_status : entity work.psi_common_status_cc generic map( - width_g => 34 + width_g => 36 ) port map( a_clk_i => ClkReg, a_rst_i => '0', a_dat_i(31 downto 0) => PostTrigSpls, a_dat_i(33 downto 32) => Mode, + a_dat_i(34) => ToDisable, + a_dat_i(35) => FrameTo, b_clk_i => Str_Clk, b_rst_i => Str_Rst, b_dat_o(31 downto 0) => PostTrigSpls_Sync, - b_dat_o(33 downto 32) => Mode_Sync + b_dat_o(33 downto 32) => Mode_Sync, + b_dat_o(34) => ToDisable_Sync, + b_dat_o(35) => FrameTo_Sync ); i_cc_status : entity work.psi_common_bit_cc @@ -450,7 +469,7 @@ begin ); Str_Rst <= RstReg_Sync or RstAcq_Sync; - -- *** Acquisition Clock Crossing *** + -- *** Acquisition Clock Crossing *** -- Clock crossing for reset and TLAST counter i_cc : entity work.psi_common_status_cc generic map( @@ -567,4 +586,3 @@ begin end process; end; - diff --git a/hdl/psi_ms_daq_reg_axi.vhd b/hdl/psi_ms_daq_reg_axi.vhd index 302925f..1d10561 100644 --- a/hdl/psi_ms_daq_reg_axi.vhd +++ b/hdl/psi_ms_daq_reg_axi.vhd @@ -27,7 +27,7 @@ entity psi_ms_daq_reg_axi is AxiSlaveIdWidth_g : integer ); port( - -- AXI Control Signals + -- AXI Control Signals S_Axi_Aclk : in std_logic; S_Axi_Aresetn : in std_logic; -- AXI Read address channel @@ -76,6 +76,8 @@ entity psi_ms_daq_reg_axi is IsRecording : in std_logic_vector(Streams_g - 1 downto 0); PostTrig : out t_aslv32(Streams_g - 1 downto 0); RecMode : out t_aslv2(Streams_g - 1 downto 0); + ToDisable : out std_logic_vector(Streams_g - 1 downto 0); + FrameTo : out std_logic_vector(Streams_g - 1 downto 0); IrqOut : out std_logic; -- Memory Interfae Clock domain control singals ClkMem : in std_logic; @@ -97,18 +99,20 @@ end entity; architecture rtl of psi_ms_daq_reg_axi is -- Two process method type two_process_r is record - Reg_Gcfg_Ena : std_logic; - Reg_Gcfg_IrqEna : std_logic; - Reg_IrqVec : std_logic_vector(Streams_g - 1 downto 0); - Reg_IrqEna : std_logic_vector(Streams_g - 1 downto 0); - Reg_StrEna : std_logic_vector(Streams_g - 1 downto 0); - Reg_PostTrig : t_aslv32(Streams_g - 1 downto 0); - Reg_Mode_Recm : t_aslv2(Streams_g - 1 downto 0); - Reg_Mode_Arm : std_logic_vector(Streams_g - 1 downto 0); - Irq : std_logic; - RegRdval : std_logic_vector(31 downto 0); - AddrReg : std_logic_vector(15 downto 0); - MaxLvlClr : std_logic_vector(Streams_g - 1 downto 0); + Reg_Gcfg_Ena : std_logic; + Reg_Gcfg_IrqEna : std_logic; + Reg_IrqVec : std_logic_vector(Streams_g - 1 downto 0); + Reg_IrqEna : std_logic_vector(Streams_g - 1 downto 0); + Reg_StrEna : std_logic_vector(Streams_g - 1 downto 0); + Reg_PostTrig : t_aslv32(Streams_g - 1 downto 0); + Reg_Mode_Recm : t_aslv2(Streams_g - 1 downto 0); + Reg_Mode_Arm : std_logic_vector(Streams_g - 1 downto 0); + Reg_Mode_ToDisable : std_logic_vector(Streams_g - 1 downto 0); + Reg_Mode_FrameTo : std_logic_vector(Streams_g - 1 downto 0); + Irq : std_logic; + RegRdval : std_logic_vector(31 downto 0); + AddrReg : std_logic_vector(15 downto 0); + MaxLvlClr : std_logic_vector(Streams_g - 1 downto 0); end record; signal r, r_next : two_process_r; @@ -228,9 +232,15 @@ begin if AccWr(1) = '1' then v.Reg_Mode_Arm(Stream_v) := AccWrData(8); end if; + if AccWr(3) = '1' then + v.Reg_Mode_ToDisable(Stream_v) := AccWrData(24); + v.Reg_Mode_FrameTo(Stream_v) := AccWrData(25); + end if; v.RegRdval(1 downto 0) := r.Reg_Mode_Recm(Stream_v); v.RegRdval(8) := IsArmed(Stream_v); v.RegRdval(16) := IsRecording(Stream_v); + v.RegRdval(24) := r.Reg_Mode_ToDisable(Stream_v); + v.RegRdval(25) := r.Reg_Mode_FrameTo(Stream_v); end if; -- LASTWINn @@ -280,10 +290,12 @@ begin end process; -- *** Registered Outputs *** - IrqOut <= r.Irq; - PostTrig <= r.Reg_PostTrig; - Arm <= r.Reg_Mode_Arm; - RecMode <= r.Reg_Mode_Recm; + IrqOut <= r.Irq; + PostTrig <= r.Reg_PostTrig; + Arm <= r.Reg_Mode_Arm; + RecMode <= r.Reg_Mode_Recm; + ToDisable <= r.Reg_Mode_ToDisable; + FrameTo <= r.Reg_Mode_FrameTo; -------------------------------------------- -- Sequential Process @@ -293,15 +305,17 @@ begin if rising_edge(S_Axi_Aclk) then r <= r_next; if A_Axi_Areset = '1' then - r.Reg_Gcfg_Ena <= '0'; - r.Reg_Gcfg_IrqEna <= '0'; - r.Reg_IrqVec <= (others => '0'); - r.Reg_IrqEna <= (others => '0'); - r.Reg_StrEna <= (others => '0'); - r.Irq <= '0'; - r.Reg_PostTrig <= (others => (others => '0')); - r.Reg_Mode_Recm <= (others => (others => '0')); - r.Reg_Mode_Arm <= (others => '0'); + r.Reg_Gcfg_Ena <= '0'; + r.Reg_Gcfg_IrqEna <= '0'; + r.Reg_IrqVec <= (others => '0'); + r.Reg_IrqEna <= (others => '0'); + r.Reg_StrEna <= (others => '0'); + r.Irq <= '0'; + r.Reg_PostTrig <= (others => (others => '0')); + r.Reg_Mode_Recm <= (others => (others => '0')); + r.Reg_Mode_Arm <= (others => '0'); + r.Reg_Mode_ToDisable <= (others => '0'); + r.Reg_Mode_FrameTo <= (others => '0'); end if; end if; end process; @@ -329,7 +343,7 @@ begin -------------------------------------------- -- Component Instantiations - -------------------------------------------- + -------------------------------------------- -- *** AXI Interface *** i_axi : entity work.psi_common_axi_slave_ipif