404 lines
26 KiB
VHDL
404 lines
26 KiB
VHDL
-- ---------------------------------------------------------------------------
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-- Paul Scherrer Institute (PSI)
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-- ---------------------------------------------------------------------------
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-- Unit : evr320_tmem.vhd
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-- Author : Patric Bucher, Benoit Stef
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-- ---------------------------------------------------------------------------
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-- Copyright (c) PSI, Section DSV
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-- ---------------------------------------------------------------------------
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-- Comment : TMEM address decoding for register and memory access to evr320.
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-- ---------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.math_real.all;
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library tosca2;
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use tosca2.tosca2_glb_pkg.all;
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use work.evr320_pkg.all;
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entity evr320_tmem is
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port(
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-- ------------------------------------------------------------------------
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-- TOSCA2 TMEM Interface (xuser clock domain, 100-250MHz)
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-- ------------------------------------------------------------------------
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xuser_CLK : in std_logic;
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xuser_RESET : in std_logic;
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xuser_TMEM_ENA : in std_logic;
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xuser_TMEM_WE : in std_logic_vector( 7 downto 0);
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xuser_TMEM_ADD : in std_logic_vector(13 downto 3);
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xuser_TMEM_DATW : in std_logic_vector(63 downto 0);
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xuser_TMEM_DATR : out std_logic_vector(63 downto 0);
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---------------------------------------------------------------------------
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-- EVR320 Memory/Parameter Interface
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---------------------------------------------------------------------------
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evr_params_o : out typ_evr320_params;
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evr_frequency_i : in std_logic_vector(31 downto 0);
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evr_evt_rec_status_i : in typ_evt_rec_status;
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evr_evt_rec_control_o : out typ_evt_rec_ctrl;
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evr_latency_measure_stat_i : in typ_rec_latency_measure_stat;
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evr_latency_measure_ctrl_o : out typ_rec_latency_measure_ctrl;
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mgt_status_i : in std_logic_vector(31 downto 0);
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mgt_reset_o : out std_logic;
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mem_clk_o : out std_logic;
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mem_addr_o : out std_logic_vector(10 downto 0);
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mem_data_i : in std_logic_vector(63 downto 0);
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---------------------------------------------------------------------------
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-- EVR320 pulse output paremters
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---------------------------------------------------------------------------
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evr_clk_i : in std_logic;
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evr_rst_i : in std_logic;
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evr_pulse_delay_o : out typ_arr_delay;
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evr_pulse_width_o : out typ_arr_width
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);
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end evr320_tmem;
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architecture rtl of evr320_tmem is
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-- ---------------------------------------------------------------------------
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-- Constants
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-- ---------------------------------------------------------------------------
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constant reserved : std_logic_vector(63 downto 0) := X"0000_0000_0000_0000";
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constant c_LOW : std_logic_vector(63 downto 0) := X"0000_0000_0000_0000";
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constant NUM_REG64 : integer := 16;
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constant TMEM_ADDR_LSB : integer := 3; -- 64 bit
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constant REG_ADDR_WIDTH : integer := integer(ceil(log2(real(NUM_REG64)))) + TMEM_ADDR_LSB;
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constant REG_ADDR_MSB : integer := REG_ADDR_WIDTH - 1;
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constant MEM_ADDR_START : std_logic_vector(7 downto 0) := X"10";
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-- --------------------------------------------------------------------------
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-- Signal definitions
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-- --------------------------------------------------------------------------
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-- xuser tmem signals
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signal xuser_TMEM_WE_reg : std_logic_vector( 7 downto 0) := (others => '0');
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signal xuser_TMEM_ENA_reg : std_logic := '0';
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signal xuser_TMEM_ADD_reg : std_logic_vector(13 downto 3) := (others => '0');
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signal xuser_TMEM_DATW_reg : std_logic_vector(63 downto 0) := (others => '0');
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-- evr params
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signal mgt_status_evr : std_logic_vector(15 downto 0) := (others => '0');
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signal mgt_status_evr_sync : std_logic_vector(15 downto 0) := (others => '0');
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signal mgt_reset : std_logic := '0';
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signal event_enable : std_logic_vector( 3 downto 0) := (others => '0');
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signal event_numbers : typ_arr8(3 downto 0) := (others => (others => '0'));
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signal event_numbers_concat : std_logic_vector(31 downto 0);
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signal cs_min_cnt : std_logic_vector(31 downto 0) := c_CHECKSUM_MIN_EVT;
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signal cs_min_time : std_logic_vector(31 downto 0) := c_CHECKSUM_MIN_TIME;
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signal evr_frequency_sync : std_logic_vector(31 downto 0) := (others => '0');
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signal evr_frequency : std_logic_vector(31 downto 0) := (others => '0');
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-- event recorder
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signal er_status : typ_evt_rec_status := c_INIT_EVT_REC_STATUS;
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signal er_status_sync : typ_evt_rec_status := c_INIT_EVT_REC_STATUS;
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signal er_event_enable : std_logic := '0';
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signal er_event_number : std_logic_vector( 7 downto 0) := c_SOS_EVENT_DEFAULT;
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signal er_data_ack : std_logic_vector( 3 downto 0) := (others => '0');
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signal er_error_ack : std_logic_vector( 3 downto 0) := (others => '0');
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signal er_handshake_status : std_logic_vector(31 downto 0) := (others => '0');
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signal er_control_concat : std_logic_vector(31 downto 0) := (others => '0');
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-- latency measurement
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signal lat_counter_arm : std_logic := '0';
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signal lat_event_nr : std_logic_vector(7 downto 0) := x"26"; -- default SOS event
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signal lat_counter_val : std_logic_vector(31 downto 0) := (others=>'0');
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-- signal evr_force : std_logic_vector(3 downto 0) := (others => '0');
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-- signal evr_force_rd : std_logic_vector(3 downto 0) := (others => '0'); -- readback
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-- signal evr_force_pulse : typ_arr4(3 downto 0) := (others => (others => '0'));
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-- event pulse config
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signal evr_puls_width_cfg_s : typ_arr_width :=((others=>(others=>'0')));
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signal evr_puls_delay_cfg_s : typ_arr_delay :=((others=>(others=>'0')));
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-- ----------------------------------------------------------------------------
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-- ----------------------------------------------------------------------------
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-- //////////////////// Main Body /////////////////////////
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-- ----------------------------------------------------------------------------
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-- ----------------------------------------------------------------------------
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begin
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-- --------------------------------------------------------------------------
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-- static signal assignments
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-- --------------------------------------------------------------------------
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event_numbers_concat <= event_numbers(3) & event_numbers(2) & event_numbers(1) & event_numbers(0);
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er_handshake_status <= X"0000" & bit2byte(er_status.data_error) & bit2byte(er_status.data_valid);
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er_control_concat <= X"0000" & er_event_number & bit2byte(er_event_enable);
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lat_counter_val <= evr_latency_measure_stat_i.counter_val;
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-- --------------------------------------------------------------------------
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-- TODO: proper CDC
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-- Synchronisation to xuser_CLK
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-- --------------------------------------------------------------------------
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prc_sync_xuser: process (xuser_CLK)
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begin
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if rising_edge(xuser_CLK) then
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---
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xuser_TMEM_WE_reg <= xuser_TMEM_WE;
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xuser_TMEM_ENA_reg <= xuser_TMEM_ENA;
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xuser_TMEM_DATW_reg <= xuser_TMEM_DATW;
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xuser_TMEM_ADD_reg <= xuser_TMEM_ADD;
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---
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mgt_status_evr_sync <= "000000" & mgt_status_i(c_RXRESETDONE) & mgt_status_i(c_RXLOSSOFSYNC) & "000000" & mgt_status_i(c_RXRESETDONE) & mgt_status_i(c_RXPLLLKDET);
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mgt_status_evr <= mgt_status_evr_sync;
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---
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er_status_sync <= evr_evt_rec_status_i;
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er_status <= er_status_sync;
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---
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evr_frequency_sync <= evr_frequency_i;
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evr_frequency <= evr_frequency_sync;
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---
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end if;
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end process;
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-- --------------------------------------------------------------------------
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-- Read operation
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-- --------------------------------------------------------------------------
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read_tmem_evr: process(xuser_CLK)
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begin
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if (rising_edge(xuser_CLK)) then
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lat_counter_arm <= '0';
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if (xuser_TMEM_ENA_reg = '1') then
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if (xuser_TMEM_ADD_reg(13 downto REG_ADDR_WIDTH) = c_LOW(13 downto REG_ADDR_WIDTH)) then
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case xuser_TMEM_ADD_reg(REG_ADDR_MSB downto TMEM_ADDR_LSB) is
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when X"0" => xuser_TMEM_DATR <= event_numbers_concat & X"0000" & mgt_status_evr; -- 64bit / ByteAddr 000
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when X"1" => xuser_TMEM_DATR <= reserved(63 downto 32) & X"0000_00" & bit2byte(mgt_reset); -- 64bit / ByteAddr 008 --> 0x00C = not implemented in ifc1210
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when X"2" => xuser_TMEM_DATR <= reserved(63 downto 32) & bit2byte(event_enable); -- 64bit / ByteAddr 010 --> 0x014 = Bit0 SW Trigger Event 0, Bit8 SW Trigger Event 1, ... evr_force
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when X"3" => xuser_TMEM_DATR <= evr_frequency & reserved(31 downto 0); -- 64bit / ByteAddr 018 --> 0x018 = Implementation Options + c_EVR_Location_vec
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when X"4" => xuser_TMEM_DATR <= cs_min_time & cs_min_cnt; -- 64bit / ByteAddr 020
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when X"5" => xuser_TMEM_DATR <= reserved(63 downto 0); -- 64bit / ByteAddr 028
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when X"6" => xuser_TMEM_DATR <= lat_counter_val & X"000000" & lat_event_nr; -- 64bit / ByteAddr 030
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when X"7" => xuser_TMEM_DATR <= reserved(63 downto 32) & lat_counter_val; lat_counter_arm <= '1'; -- 64bit / ByteAddr 038
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when X"8" => xuser_TMEM_DATR <= er_handshake_status & er_control_concat; -- 64bit / ByteAddr 040
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when X"9" => xuser_TMEM_DATR <= reserved(63 downto 32) & er_status.usr_events_counter; -- 64bit / ByteAddr 048
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when X"A" => xuser_TMEM_DATR <= evr_puls_delay_cfg_s(4) & evr_puls_delay_cfg_s(3) & evr_puls_delay_cfg_s(2) & evr_puls_delay_cfg_s(1) ; -- 64bit / ByteAddr 050
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when X"B" => xuser_TMEM_DATR <= evr_puls_width_cfg_s(4) & evr_puls_width_cfg_s(3) & evr_puls_width_cfg_s(2) & evr_puls_width_cfg_s(1) ; --64 bit / ByteAddr 054
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when X"C" => xuser_TMEM_DATR <= reserved(63 downto 32) & evr_puls_width_cfg_s(0) & evr_puls_delay_cfg_s(0); -- 64bit / ByteAddr 058
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when others => xuser_TMEM_DATR <= (others => '0');
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end case;
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else --> 0x0080-0x4000
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xuser_TMEM_DATR <= mem_data_i;
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end if;
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end if;
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end if;
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end process;
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-- --------------------------------------------------------------------------
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-- Write operation - Byte control
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-- --------------------------------------------------------------------------
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write_tmem_evr: process(xuser_CLK)
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begin
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if rising_edge(xuser_CLK) then
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-- default assignments
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er_data_ack <= er_data_ack(2 downto 0) & '0';
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er_error_ack <= er_error_ack(2 downto 0) & '0';
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if (xuser_TMEM_ENA_reg = '1' and xuser_TMEM_ADD_reg(13 downto REG_ADDR_WIDTH) = c_LOW(13 downto REG_ADDR_WIDTH)) then
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-----------------------------------------------------------------------------------------------------------------
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if xuser_TMEM_ADD_reg(6 downto 3) = X"0" then --ByteAddr 000
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-- if xuser_TMEM_WE_reg(0) = '1' then -read only- <= xuser_TMEM_DATW_reg( 7 downto 0); end if;
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-- if xuser_TMEM_WE_reg(1) = '1' then -read only- <= xuser_TMEM_DATW_reg(15 downto 8); end if;
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-- if xuser_TMEM_WE_reg(2) = '1' then -read only- <= xuser_TMEM_DATW_reg(23 downto 16); end if;
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-- if xuser_TMEM_WE_reg(3) = '1' then -read only- <= xuser_TMEM_DATW_reg(31 downto 24); end if;
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if xuser_TMEM_WE_reg(4) = '1' then event_numbers(0) <= xuser_TMEM_DATW_reg(39 downto 32); end if;
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if xuser_TMEM_WE_reg(5) = '1' then event_numbers(1) <= xuser_TMEM_DATW_reg(47 downto 40); end if;
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if xuser_TMEM_WE_reg(6) = '1' then event_numbers(2) <= xuser_TMEM_DATW_reg(55 downto 48); end if;
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if xuser_TMEM_WE_reg(7) = '1' then event_numbers(3) <= xuser_TMEM_DATW_reg(63 downto 56); end if;
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end if;
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-----------------------------------------------------------------------------------------------------------------
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if xuser_TMEM_ADD_reg(6 downto 3) = X"1" then --ByteAddr 008
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if xuser_TMEM_WE_reg(0) = '1' then mgt_reset <= xuser_TMEM_DATW_reg(0); end if;
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-- if xuser_TMEM_WE_reg(1) = '1' then -reserved- <= xuser_TMEM_DATW_reg(15 downto 8); end if;
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-- if xuser_TMEM_WE_reg(2) = '1' then -reserved- <= xuser_TMEM_DATW_reg(23 downto 16); end if;
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-- if xuser_TMEM_WE_reg(3) = '1' then -reserved- <= xuser_TMEM_DATW_reg(31 downto 24); end if;
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-- if xuser_TMEM_WE_reg(4) = '1' then -reserved- <= xuser_TMEM_DATW_reg(39 downto 32); end if;
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-- if xuser_TMEM_WE_reg(5) = '1' then -reserved- <= xuser_TMEM_DATW_reg(47 downto 40); end if;
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-- if xuser_TMEM_WE_reg(6) = '1' then -reserved- <= xuser_TMEM_DATW_reg(55 downto 48); end if;
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-- if xuser_TMEM_WE_reg(7) = '1' then -reserved- <= xuser_TMEM_DATW_reg(63 downto 56); end if;
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end if;
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-----------------------------------------------------------------------------------------------------------------
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if xuser_TMEM_ADD_reg(6 downto 3) = X"2" then --ByteAddr 010
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if xuser_TMEM_WE_reg(0) = '1' then event_enable(0) <= xuser_TMEM_DATW_reg( 0); end if;
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if xuser_TMEM_WE_reg(1) = '1' then event_enable(1) <= xuser_TMEM_DATW_reg( 8); end if;
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if xuser_TMEM_WE_reg(2) = '1' then event_enable(2) <= xuser_TMEM_DATW_reg(16); end if;
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if xuser_TMEM_WE_reg(3) = '1' then event_enable(3) <= xuser_TMEM_DATW_reg(24); end if;
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-- if xuser_TMEM_WE_reg(4) = '1' then -reserved- <= xuser_TMEM_DATW_reg(39 downto 32); end if;
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-- if xuser_TMEM_WE_reg(5) = '1' then -reserved- <= xuser_TMEM_DATW_reg(47 downto 40); end if;
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-- if xuser_TMEM_WE_reg(6) = '1' then -reserved- <= xuser_TMEM_DATW_reg(55 downto 48); end if;
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-- if xuser_TMEM_WE_reg(7) = '1' then -reserved- <= xuser_TMEM_DATW_reg(63 downto 56); end if;
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end if;
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-----------------------------------------------------------------------------------------------------------------
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if xuser_TMEM_ADD_reg(6 downto 3) = X"4" then --ByteAddr 020
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if xuser_TMEM_WE_reg(0) = '1' then cs_min_cnt ( 7 downto 0) <= xuser_TMEM_DATW_reg( 7 downto 0); end if;
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if xuser_TMEM_WE_reg(1) = '1' then cs_min_cnt (15 downto 8) <= xuser_TMEM_DATW_reg(15 downto 8); end if;
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if xuser_TMEM_WE_reg(2) = '1' then cs_min_cnt (23 downto 16) <= xuser_TMEM_DATW_reg(23 downto 16); end if;
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if xuser_TMEM_WE_reg(3) = '1' then cs_min_cnt (31 downto 24) <= xuser_TMEM_DATW_reg(31 downto 24); end if;
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if xuser_TMEM_WE_reg(4) = '1' then cs_min_time( 7 downto 0) <= xuser_TMEM_DATW_reg(39 downto 32); end if;
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if xuser_TMEM_WE_reg(5) = '1' then cs_min_time(15 downto 8) <= xuser_TMEM_DATW_reg(47 downto 40); end if;
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if xuser_TMEM_WE_reg(6) = '1' then cs_min_time(23 downto 16) <= xuser_TMEM_DATW_reg(55 downto 48); end if;
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if xuser_TMEM_WE_reg(7) = '1' then cs_min_time(31 downto 24) <= xuser_TMEM_DATW_reg(63 downto 56); end if;
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end if;
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-----------------------------------------------------------------------------------------------------------------
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if xuser_TMEM_ADD_reg(6 downto 3) = X"6" then --ByteAddr 030 Latency Measurement
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if xuser_TMEM_WE_reg(0) = '1' then lat_event_nr ( 7 downto 0) <= xuser_TMEM_DATW_reg( 7 downto 0); end if;
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-- if xuser_TMEM_WE_reg(1) = '1' then -reserved- (15 downto 8) <= xuser_TMEM_DATW_reg(15 downto 8); end if;
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-- if xuser_TMEM_WE_reg(2) = '1' then -reserved- (23 downto 16) <= xuser_TMEM_DATW_reg(23 downto 16); end if;
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-- if xuser_TMEM_WE_reg(3) = '1' then -reserved- (31 downto 24) <= xuser_TMEM_DATW_reg(31 downto 24); end if;
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-- if xuser_TMEM_WE_reg(4) = '1' then -reserved- ( 7 downto 0) <= xuser_TMEM_DATW_reg(39 downto 32); end if;
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-- if xuser_TMEM_WE_reg(5) = '1' then -reserved- (15 downto 8) <= xuser_TMEM_DATW_reg(47 downto 40); end if;
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-- if xuser_TMEM_WE_reg(6) = '1' then -reserved- (23 downto 16) <= xuser_TMEM_DATW_reg(55 downto 48); end if;
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-- if xuser_TMEM_WE_reg(7) = '1' then -reserved- (31 downto 24) <= xuser_TMEM_DATW_reg(63 downto 56); end if;
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end if;
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-----------------------------------------------------------------------------------------------------------------
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if xuser_TMEM_ADD_reg(6 downto 3) = X"8" then --ByteAddr 040
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if xuser_TMEM_WE_reg(0) = '1' then er_event_enable <= xuser_TMEM_DATW_reg(0); end if;
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if xuser_TMEM_WE_reg(1) = '1' then er_event_number <= xuser_TMEM_DATW_reg(15 downto 8); end if;
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-- if xuser_TMEM_WE_reg(2) = '1' then -reserved- <= xuser_TMEM_DATW_reg(23 downto 16); end if;
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-- if xuser_TMEM_WE_reg(3) = '1' then -reserved- <= xuser_TMEM_DATW_reg(31 downto 24); end if;
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-- if xuser_TMEM_WE_reg(4) = '1' then -read only- <= xuser_TMEM_DATW_reg(39 downto 32); end if;
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-- if xuser_TMEM_WE_reg(5) = '1' then -read only- <= xuser_TMEM_DATW_reg(47 downto 40); end if;
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if xuser_TMEM_WE_reg(6) = '1' and xuser_TMEM_DATW_reg(48) = '1' then er_data_ack <= (others => '1'); end if;
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if xuser_TMEM_WE_reg(7) = '1' and xuser_TMEM_DATW_reg(56) = '1' then er_error_ack <= (others => '1'); end if;
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end if;
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-----------------------------------------------------------------------------------------------------------------
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if xuser_TMEM_ADD_reg(6 downto 3) = X"A" then --ByteAddr 050
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if xuser_TMEM_WE_reg(1 downto 0) = "11" then evr_puls_delay_cfg_s(1) <= xuser_TMEM_DATW_reg(15 downto 0); end if; -- usr evt 0 del
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if xuser_TMEM_WE_reg(3 downto 2) = "11" then evr_puls_delay_cfg_s(2) <= xuser_TMEM_DATW_reg(31 downto 16); end if; -- usr evt 1 del
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if xuser_TMEM_WE_reg(5 downto 4) = "11" then evr_puls_delay_cfg_s(3) <= xuser_TMEM_DATW_reg(47 downto 32); end if; -- usr evt 2 del
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if xuser_TMEM_WE_reg(7 downto 6) = "11" then evr_puls_delay_cfg_s(4) <= xuser_TMEM_DATW_reg(63 downto 48); end if; -- usr evt 3 del
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end if;
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-----------------------------------------------------------------------------------------------------------------
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if xuser_TMEM_ADD_reg(6 downto 3) = X"B" then --ByteAddr 058
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if xuser_TMEM_WE_reg(1 downto 0) = "11" then evr_puls_width_cfg_s(1) <= xuser_TMEM_DATW_reg(15 downto 0); end if; -- usr evt 0 width
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if xuser_TMEM_WE_reg(3 downto 2) = "11" then evr_puls_width_cfg_s(2) <= xuser_TMEM_DATW_reg(31 downto 16); end if; -- usr evt 1 width
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if xuser_TMEM_WE_reg(5 downto 4) = "11" then evr_puls_width_cfg_s(3) <= xuser_TMEM_DATW_reg(47 downto 32); end if; -- usr evt 2 width
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if xuser_TMEM_WE_reg(7 downto 6) = "11" then evr_puls_width_cfg_s(4) <= xuser_TMEM_DATW_reg(63 downto 48); end if; -- usr evt 3 width
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end if;
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-----------------------------------------------------------------------------------------------------------------
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if xuser_TMEM_ADD_reg(6 downto 3) = X"C" then --ByteAddr 060
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if xuser_TMEM_WE_reg(1 downto 0) = "11" then evr_puls_delay_cfg_s(0) <= xuser_TMEM_DATW_reg(15 downto 0); end if; -- sos evt del
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if xuser_TMEM_WE_reg(3 downto 2) = "11" then evr_puls_width_cfg_s(0) <= xuser_TMEM_DATW_reg(31 downto 16); end if; -- sos evt width
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end if;
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end if;
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end if;
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end process;
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|
|
|
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-- --------------------------------------------------------------------------
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-- Port mapping
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-- --------------------------------------------------------------------------
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mem_clk_o <= xuser_CLK;
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mem_addr_o <= std_logic_vector(unsigned(xuser_TMEM_ADD) - unsigned(MEM_ADDR_START));
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--event recorder had to be also added to cdc
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evr_evt_rec_control_o <= (er_event_number, er_event_enable, er_data_ack(3), er_error_ack(3));
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mgt_reset_o <= mgt_reset;
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|
|
|
-- --------------------------------------------------------------------------
|
|
-- add CDC output
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|
-- --------------------------------------------------------------------------
|
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block_cdc_evr_puls_param : block
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signal input_s, output_s : std_logic_vector(10 * 16 - 1 downto 0);
|
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begin
|
|
-- ------------------------------------------------------------------------
|
|
-- Assemble Input
|
|
-- ------------------------------------------------------------------------
|
|
--** pulse delay parameters **
|
|
input_s(15 downto 0) <= evr_puls_delay_cfg_s(0);
|
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input_s(31 downto 16) <= evr_puls_delay_cfg_s(1);
|
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input_s(47 downto 32) <= evr_puls_delay_cfg_s(2);
|
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input_s(63 downto 48) <= evr_puls_delay_cfg_s(3);
|
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input_s(79 downto 64) <= evr_puls_delay_cfg_s(4);
|
|
--** pulse width parameters **
|
|
input_s(95 downto 80) <= evr_puls_width_cfg_s(0);
|
|
input_s(111 downto 96) <= evr_puls_width_cfg_s(1);
|
|
input_s(127 downto 112) <= evr_puls_width_cfg_s(2);
|
|
input_s(143 downto 128) <= evr_puls_width_cfg_s(3);
|
|
input_s(159 downto 144) <= evr_puls_width_cfg_s(4);
|
|
|
|
-- Instance
|
|
inst_cdc_fast_stat : entity work.psi_common_status_cc
|
|
generic map(width_g => input_s'length)
|
|
port map(a_clk_i => xuser_CLK,
|
|
a_rst_i => xuser_RESET,
|
|
a_dat_i => input_s,
|
|
b_clk_i => evr_clk_i,
|
|
b_rst_i => evr_rst_i,
|
|
b_dat_o => output_s);
|
|
-- ------------------------------------------------------------------------
|
|
-- Disassemble Output
|
|
-- ------------------------------------------------------------------------
|
|
--** pulse delay parameters **
|
|
evr_pulse_delay_o(0) <= output_s(15 downto 0);
|
|
evr_pulse_delay_o(1) <= output_s(31 downto 16);
|
|
evr_pulse_delay_o(2) <= output_s(47 downto 32);
|
|
evr_pulse_delay_o(3) <= output_s(63 downto 48);
|
|
evr_pulse_delay_o(4) <= output_s(79 downto 64);
|
|
--** pulse width parameters **
|
|
evr_pulse_width_o(0) <= output_s(95 downto 80);
|
|
evr_pulse_width_o(1) <= output_s(111 downto 96);
|
|
evr_pulse_width_o(2) <= output_s(127 downto 112);
|
|
evr_pulse_width_o(3) <= output_s(143 downto 128);
|
|
evr_pulse_width_o(4) <= output_s(159 downto 144);
|
|
end block;
|
|
|
|
block_cdc_evr_code_param : block
|
|
signal input_s, output_s : std_logic_vector(108 downto 0);
|
|
begin
|
|
-- ------------------------------------------------------------------------
|
|
-- Assemble Input
|
|
-- ------------------------------------------------------------------------
|
|
--** event numbers **
|
|
input_s( 7 downto 0) <= event_numbers(0);
|
|
input_s(15 downto 8) <= event_numbers(1);
|
|
input_s(23 downto 16) <= event_numbers(2);
|
|
input_s(31 downto 24) <= event_numbers(3);
|
|
--** event pulse enable **
|
|
input_s(35 downto 32) <= event_enable;
|
|
--** time counter **
|
|
input_s(67 downto 36) <= cs_min_time;
|
|
input_s(99 downto 68) <= cs_min_cnt;
|
|
--** latency counter **
|
|
input_s(100) <= lat_counter_arm;
|
|
input_s(108 downto 101) <= lat_event_nr;
|
|
|
|
-- Instance
|
|
inst_cdc_fast_stat : entity work.psi_common_status_cc
|
|
generic map(width_g => input_s'length)
|
|
port map(a_clk_i => xuser_CLK,
|
|
a_rst_i => xuser_RESET,
|
|
a_rst_o => open,
|
|
a_dat_i => input_s,
|
|
b_clk_i => evr_clk_i,
|
|
b_rst_i => evr_rst_i,
|
|
b_rst_o => open,
|
|
b_dat_o => output_s);
|
|
-- ------------------------------------------------------------------------
|
|
-- Disassemble Output
|
|
-- ------------------------------------------------------------------------
|
|
--** event numbers **
|
|
evr_params_o.event_numbers(0) <= output_s( 7 downto 0) ;
|
|
evr_params_o.event_numbers(1) <= output_s(15 downto 8) ;
|
|
evr_params_o.event_numbers(2) <= output_s(23 downto 16);
|
|
evr_params_o.event_numbers(3) <= output_s(31 downto 24);
|
|
--** event pulse enable **
|
|
evr_params_o.event_enable <= output_s(35 downto 32);
|
|
--** time counter **
|
|
evr_params_o.cs_min_time <= output_s(67 downto 36);
|
|
evr_params_o.cs_min_cnt <= output_s(99 downto 68);
|
|
--** latency counter **
|
|
evr_latency_measure_ctrl_o.counter_arm <= output_s(100) ;
|
|
evr_latency_measure_ctrl_o.event_nr <= output_s(108 downto 101) ;
|
|
end block;
|
|
|
|
end rtl;
|
|
-- ----------------------------------------------------------------------------
|
|
-- ////////////////////////////////////////////////////////////////////////////
|
|
-- ----------------------------------------------------------------------------
|