------------------------------------------------------------------------------ -- Paul Scherrer Institute (PSI) ------------------------------------------------------------------------------ -- Unit : v6vlx_gtxe1_101MHz27_1Gbps0127.vhd -- Author : Goran Marinkovic, Section Diagnostic -- : Waldemar Koprek, Section Diagnostic -- : Patric Bucher, Section DSV -- Version : $Revision: 1.1 $ ------------------------------------------------------------------------------ -- Copyright© PSI, Section Diagnostic ------------------------------------------------------------------------------ -- Comment : Virtex-6 GTXE1 primitive configured for HIPA 50.63282 MHz ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library unisim; use unisim.vcomponents.all; use work.v6vlx_gtxe1_pkg.all; entity v6vlx_gtxe1_101MHz27_1Gbps0127 is generic( g_MGT_LOCATION : string ); port ( i_mgt : in gtxe_in_type; o_mgt : out gtxe_out_type ); end v6vlx_gtxe1_101MHz27_1Gbps0127; architecture RTL of v6vlx_gtxe1_101MHz27_1Gbps0127 is --**************************** Signal Declarations **************************** -- ground and tied_to_vcc_i signals signal tied_to_ground_i : std_logic; signal tied_to_ground_vec_i : std_logic_vector(63 downto 0); signal tied_to_vcc_i : std_logic; --***************************** Main Body of Code ***************************** signal slv_mgtrefclk : std_logic_vector(1 downto 0); signal debug_refclk : std_logic_vector(1 downto 0); --************************** Attribute Declarations *************************** attribute LOC : string; attribute LOC of gtxe1_i : label is g_MGT_LOCATION; begin --------------------------- Static signal Assignments --------------------- tied_to_ground_i <= '0'; tied_to_ground_vec_i(63 downto 0) <= (others => '0'); tied_to_vcc_i <= '1'; slv_mgtrefclk <= "0" & i_mgt.ctrl.CLKIN; o_mgt.ctrl.REFCLKOUT <= debug_refclk(1); --------------------------------- GTX Instance ----------------------------- gtxe1_i :GTXE1 generic map ( --_______________________ Simulation-Only Attributes ___________________ SIM_RECEIVER_DETECT_PASS => (TRUE), SIM_GTXRESET_SPEEDUP => (1), --(GTX_SIM_GTXRESET_SPEEDUP), SIM_TX_ELEC_IDLE_LEVEL => ("X"), SIM_VERSION => ("2.0"), SIM_TXREFCLK_SOURCE => ("000"), SIM_RXREFCLK_SOURCE => ("000"), ----------------------------TX PLL---------------------------- TX_CLK_SOURCE => "RXPLL", -- TX_OVERSAMPLE_MODE => FALSE, -- TXPLL_COM_CFG => X"21680A", -- TXPLL_CP_CFG => X"0D", -- TXPLL_DIVSEL_FB => 4, -- 1.2GHz < Fpll < 2.7GHz TXPLL_DIVSEL_OUT => 4, -- TXPLL_DIVSEL_REF => 1, -- RXPLL_DIVSEL_FB * RXPLL_DIVSEL45_FB TXPLL_DIVSEL45_FB => 5, -- Fpll = Fclkin ----------------------------------- TXPLL_LKDET_CFG => "111", -- RXPLL_DIVSEL_REF TX_CLK25_DIVIDER => 4, -- TXPLL_SATA => "00", -- Fpll * 2 TX_TDCC_CFG => "00", -- Flinerate = ------------------ PMA_CAS_CLK_EN => FALSE, -- RXPLL_DIVSEL_OUT(FALSE) POWER_SAVE => "0000110100", -- [4] '1' = bypass trasmit delay aligner, [5] '1' = bypass receive delay aligner -------------------------TX Interface------------------------- GEN_TXUSRCLK => (TRUE), -- TX_DATA_WIDTH => (20), -- TX_USRCLK_CFG => (X"00"), -- TXOUTCLK_CTRL => ("TXOUTCLKPMA_DIV2"), -- TXOUTCLK_DLY => ("0000000000"), -- --------------TX Buffering and Phase Alignment---------------- TX_PMADATA_OPT => ('0'), -- PMA_TX_CFG => (x"80082"), -- TX_BUFFER_USE => (TRUE), -- TX_BYTECLK_CFG => (x"00"), -- TX_EN_RATE_RESET_BUF => (TRUE), -- TX_XCLK_SEL => ("TXOUT"), -- TX_DLYALIGN_CTRINC => ("0100"), -- TX_DLYALIGN_LPFINC => ("0110"), -- TX_DLYALIGN_MONSEL => ("000"), -- TX_DLYALIGN_OVRDSETTING => ("10000000"), -- -------------------------TX Gearbox--------------------------- -- GEARBOX_ENDEC => ("000"), -- TXGEARBOX_USE => (FALSE), -- -- ----------------TX Driver and OOB Signalling------------------ -- TX_DRIVE_MODE => ("DIRECT"), -- TX_IDLE_ASSERT_DELAY => ("100"), -- TX_IDLE_DEASSERT_DELAY => ("010"), -- TXDRIVE_LOOPBACK_HIZ => (FALSE), -- TXDRIVE_LOOPBACK_PD => (FALSE), -- -- --------------TX Pipe Control for PCI Express/SATA------------ -- COM_BURST_VAL => ("1111"), -- -- ------------------TX Attributes for PCI Express--------------- -- TX_DEEMPH_0 => ("11010"), -- TX_DEEMPH_1 => ("10000"), -- TX_MARGIN_FULL_0 => ("1001110"), -- TX_MARGIN_FULL_1 => ("1001001"), -- TX_MARGIN_FULL_2 => ("1000101"), -- TX_MARGIN_FULL_3 => ("1000010"), -- TX_MARGIN_FULL_4 => ("1000000"), -- TX_MARGIN_LOW_0 => ("1000110"), -- TX_MARGIN_LOW_1 => ("1000100"), -- TX_MARGIN_LOW_2 => ("1000010"), -- TX_MARGIN_LOW_3 => ("1000000"), -- TX_MARGIN_LOW_4 => ("1000000"), -- ----------------------------RX PLL---------------------------- RX_OVERSAMPLE_MODE => FALSE, -- 1.2GHz < Fpll < 2.7GHz RXPLL_COM_CFG => (x"21680a"), -- RXPLL_CP_CFG => (x"0D"), -- RXPLL_DIVSEL_FB * RXPLL_DIVSEL45_FB RXPLL_DIVSEL_FB => 4, -- Fpll = Fclkin ----------------------------------- RXPLL_DIVSEL_OUT => 4, -- RXPLL_DIVSEL_REF RXPLL_DIVSEL_REF => 1, -- RXPLL_DIVSEL45_FB => 5, -- Fpll * 2 RXPLL_LKDET_CFG => ("111"), -- Flinerate = ------------------ RX_CLK25_DIVIDER => 4, -- RXPLL_DIVSEL_OUT -------------------------RX Interface------------------------- GEN_RXUSRCLK => (TRUE), -- RX_DATA_WIDTH => (20), -- RXRECCLK_CTRL => ("RXRECCLKPMA_DIV2"), -- RXRECCLK_DLY => ("0000000000"), -- RXUSRCLK_DLY => (x"0000"), -- ----------RX Driver,OOB signalling,Coupling and Eq.,CDR------- AC_CAP_DIS => (FALSE), -- CDR_PH_ADJ_TIME => ("10100"), -- OOBDETECT_THRESHOLD => ("011"), -- PMA_CDR_SCAN => (x"640404C"), -- PMA_RX_CFG => (x"05ce008"), -- RCV_TERM_GND => (FALSE), -- RCV_TERM_VTTRX => (TRUE), -- RX_EN_IDLE_HOLD_CDR => (FALSE), -- RX_EN_IDLE_RESET_FR => (FALSE), -- RX_EN_IDLE_RESET_PH => (FALSE), -- TX_DETECT_RX_CFG => (x"1832"), -- TERMINATION_CTRL => ("00000"), -- TERMINATION_OVRD => (FALSE), -- CM_TRIM => ("01"), -- PMA_RXSYNC_CFG => (x"00"), -- PMA_CFG => (x"0040000040000000003"), -- BGTEST_CFG => ("00"), -- BIAS_CFG => (x"00000"), -- --------------RX Decision Feedback Equalizer(DFE)------------- DFE_CAL_TIME => ("01100"), -- DFE_CFG => ("00011011"), -- RX_EN_IDLE_HOLD_DFE => (TRUE), -- RX_EYE_OFFSET => (x"4C"), -- RX_EYE_SCANMODE => ("00"), -- -------------------------PRBS Detection----------------------- RXPRBSERR_LOOPBACK => ('0'), -- ------------------Comma Detection and Alignment--------------- ALIGN_COMMA_WORD => (2), --(1), COMMA_10B_ENABLE => ("1111111111"), -- COMMA_DOUBLE => (FALSE), -- DEC_MCOMMA_DETECT => (TRUE), --(FALSE), DEC_PCOMMA_DETECT => (TRUE), --(FALSE), DEC_VALID_COMMA_ONLY => (FALSE), -- MCOMMA_10B_VALUE => ("1010000011"), -- MCOMMA_DETECT => (TRUE), -- PCOMMA_10B_VALUE => ("0101111100"), -- PCOMMA_DETECT => (TRUE), -- RX_DECODE_SEQ_MATCH => (FALSE), -- RX_SLIDE_AUTO_WAIT => (5), -- RX_SLIDE_MODE => ("PMA"), -- SHOW_REALIGN_COMMA => (FALSE), -- -----------------RX Loss-of-sync State Machine---------------- RX_LOS_INVALID_INCR => (8), -- RX_LOS_THRESHOLD => (128), -- RX_LOSS_OF_SYNC_FSM => (TRUE), --(FALSE), -------------------------RX Gearbox--------------------------- RXGEARBOX_USE => (FALSE), -- -------------RX Elastic Buffer and Phase alignment------------ RX_BUFFER_USE => (FALSE), -- RX_EN_IDLE_RESET_BUF => (FALSE), -- RX_EN_MODE_RESET_BUF => (TRUE), -- RX_EN_RATE_RESET_BUF => (TRUE), -- RX_EN_REALIGN_RESET_BUF => (FALSE), -- RX_EN_REALIGN_RESET_BUF2 => (FALSE), -- RX_FIFO_ADDR_MODE => ("FAST"), -- RX_IDLE_HI_CNT => ("1000"), -- RX_IDLE_LO_CNT => ("0000"), -- RX_XCLK_SEL => ("RXUSR"), -- RX_DLYALIGN_CTRINC => ("1110"), -- RX_DLYALIGN_EDGESET => ("00010"), -- RX_DLYALIGN_LPFINC => ("1110"), -- RX_DLYALIGN_MONSEL => ("000"), -- RX_DLYALIGN_OVRDSETTING => ("10000000"), -- ------------------------Clock Correction---------------------- -- CLK_COR_ADJ_LEN => (1), -- CLK_COR_DET_LEN => (1), -- CLK_COR_INSERT_IDLE_FLAG => (FALSE), -- CLK_COR_KEEP_IDLE => (FALSE), -- CLK_COR_MAX_LAT => (16), -- CLK_COR_MIN_LAT => (14), -- CLK_COR_PRECEDENCE => (TRUE), -- CLK_COR_REPEAT_WAIT => (0), -- CLK_COR_SEQ_1_1 => ("0000000000"), -- CLK_COR_SEQ_1_2 => ("0000000000"), -- CLK_COR_SEQ_1_3 => ("0000000000"), -- CLK_COR_SEQ_1_4 => ("0000000000"), -- CLK_COR_SEQ_1_ENABLE => ("1111"), -- CLK_COR_SEQ_2_1 => ("0000000000"), -- CLK_COR_SEQ_2_2 => ("0000000000"), -- CLK_COR_SEQ_2_3 => ("0000000000"), -- CLK_COR_SEQ_2_4 => ("0000000000"), -- CLK_COR_SEQ_2_ENABLE => ("1111"), -- CLK_COR_SEQ_2_USE => (FALSE), -- CLK_CORRECT_USE => (FALSE), -- -- ------------------------Channel Bonding---------------------- -- CHAN_BOND_1_MAX_SKEW => (1), -- CHAN_BOND_2_MAX_SKEW => (1), -- CHAN_BOND_KEEP_ALIGN => (FALSE), -- CHAN_BOND_SEQ_1_1 => ("0000000000"), -- CHAN_BOND_SEQ_1_2 => ("0000000000"), -- CHAN_BOND_SEQ_1_3 => ("0000000000"), -- CHAN_BOND_SEQ_1_4 => ("0000000000"), -- CHAN_BOND_SEQ_1_ENABLE => ("1111"), -- CHAN_BOND_SEQ_2_1 => ("0000000000"), -- CHAN_BOND_SEQ_2_2 => ("0000000000"), -- CHAN_BOND_SEQ_2_3 => ("0000000000"), -- CHAN_BOND_SEQ_2_4 => ("0000000000"), -- CHAN_BOND_SEQ_2_CFG => ("00000"), -- CHAN_BOND_SEQ_2_ENABLE => ("1111"), -- CHAN_BOND_SEQ_2_USE => (FALSE), -- CHAN_BOND_SEQ_LEN => (1), -- PCI_EXPRESS_MODE => (FALSE), -- -- -------------RX Attributes for PCI Express/SATA/SAS---------- -- SAS_MAX_COMSAS => (52), -- SAS_MIN_COMSAS => (40), -- SATA_BURST_VAL => ("100"), -- SATA_IDLE_VAL => ("100"), SATA_MAX_BURST => (9), SATA_MAX_INIT => (27), SATA_MAX_WAKE => (9), SATA_MIN_BURST => (5), SATA_MIN_INIT => (15), SATA_MIN_WAKE => (5), TRANS_TIME_FROM_P2 => (x"03c"), TRANS_TIME_NON_P2 => (x"19"), -- TRANS_TIME_RATE => (x"ff"), -- TRANS_TIME_TO_P2 => (x"064") -- ) port map ( ------------------------ Loopback and Powerdown Ports ---------------------- LOOPBACK => i_mgt.CTRL.LOOPBACK, --tied_to_ground_vec_i(2 downto 0), RXPOWERDOWN => "00", -- TXPOWERDOWN => "00", -- -------------- Receive Ports - 64b66b and 64b67b Gearbox Ports ------------- RXDATAVALID => open, -- RXGEARBOXSLIP => tied_to_ground_i, -- RXHEADER => open, -- RXHEADERVALID => open, -- RXSTARTOFSEQ => open, -- ----------------------- Receive Ports - 8b10b Decoder ---------------------- RXCHARISCOMMA => o_mgt.rx.RXCHARISCOMMA, -- RXCHARISK => o_mgt.rx.RXCHARISK, -- RXDEC8B10BUSE => '1', --tied_to_ground_i, RXDISPERR => o_mgt.rx.RXDISPERR, --rxdisperr_i, RXNOTINTABLE => o_mgt.rx.RXNOTINTABLE, -- RXRUNDISP => o_mgt.rx.RXRUNDISP, -- USRCODEERR => tied_to_ground_i, -- ------------------- Receive Ports - Channel Bonding Ports ------------------ RXCHANBONDSEQ => open, -- RXCHBONDI => tied_to_ground_vec_i(3 downto 0), -- RXCHBONDLEVEL => tied_to_ground_vec_i(2 downto 0), -- RXCHBONDMASTER => tied_to_ground_i, -- RXCHBONDO => open, -- RXCHBONDSLAVE => tied_to_ground_i, -- RXENCHANSYNC => tied_to_ground_i, -- ------------------- Receive Ports - Clock Correction Ports ----------------- RXCLKCORCNT => open, -- --------------- Receive Ports - Comma Detection and Alignment -------------- RXBYTEISALIGNED => o_mgt.rx.RXBYTEISALIGNED, --RXBYTEISALIGNED_OUT, RXBYTEREALIGN => o_mgt.rx.RXBYTEREALIGN, --RXBYTEREALIGN_OUT, RXCOMMADET => o_mgt.rx.RXCOMMADET, --RXCOMMADET_OUT, RXCOMMADETUSE => '1', --tied_to_vcc_i, RXENMCOMMAALIGN => i_mgt.rx.RXENMCOMMAALIGN, --tied_to_ground_i, RXENPCOMMAALIGN => i_mgt.rx.RXENPCOMMAALIGN, --tied_to_ground_i, RXSLIDE => i_mgt.rx.RXSLIDE, ----------------------- Receive Ports - PRBS Detection --------------------- PRBSCNTRESET => tied_to_ground_i, -- RXENPRBSTST => tied_to_ground_vec_i(2 downto 0), -- RXPRBSERR => open, -- ------------------- Receive Ports - RX Data Path interface ----------------- RXDATA => o_mgt.rx.RXDATA, --rxdata_i, RXRECCLK => o_mgt.rx.RXRECCLK, --RXRECCLK_OUT, RXRECCLKPCS => open, RXRESET => i_mgt.rx.RXRESET, --tied_to_ground_i, RXUSRCLK => i_mgt.rx.RXUSRCLK, --tied_to_ground_i, RXUSRCLK2 => i_mgt.rx.RXUSRCLK2, --RXUSRCLK2_IN, ------------ Receive Ports - RX Decision Feedback Equalizer(DFE) ----------- DFECLKDLYADJ => tied_to_ground_vec_i(5 downto 0), -- DFECLKDLYADJMON => open, -- DFEDLYOVRD => tied_to_ground_i, -- DFEEYEDACMON => open, -- DFESENSCAL => open, -- DFETAP1 => tied_to_ground_vec_i(4 downto 0), -- DFETAP1MONITOR => open, -- DFETAP2 => tied_to_ground_vec_i(4 downto 0), -- DFETAP2MONITOR => open, -- DFETAP3 => tied_to_ground_vec_i(3 downto 0), -- DFETAP3MONITOR => open, -- DFETAP4 => tied_to_ground_vec_i(3 downto 0), -- DFETAP4MONITOR => open, -- DFETAPOVRD => tied_to_vcc_i, -- ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------ GATERXELECIDLE => tied_to_vcc_i, -- IGNORESIGDET => tied_to_vcc_i, -- RXCDRRESET => i_mgt.rx.RXCDRRESET, -- RXELECIDLE => o_mgt.rx.RXELECIDLE, --open, RXEQMIX(9 downto 3) => tied_to_ground_vec_i(6 downto 0), -- RXEQMIX(2 downto 0) => "000", --RXEQMIX_IN, RXN => i_mgt.rx.RXP, --RXN_IN, RXP => i_mgt.rx.RXN, --RXP_IN, -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports ------- RXBUFRESET => tied_to_ground_i, -- RXBUFSTATUS => open, -- RXCHANISALIGNED => open, -- RXCHANREALIGN => open, -- RXDLYALIGNDISABLE => i_mgt.rx.RXDLYALIGNDISABLE, -- RXDLYALIGNMONENB => i_mgt.rx.RXDLYALIGNMONENB, -- RXDLYALIGNMONITOR => o_mgt.rx.RXDLYALIGNMONITOR, -- RXDLYALIGNOVERRIDE => i_mgt.rx.RXDLYALIGNOVERRIDE, -- RXDLYALIGNRESET => i_mgt.rx.RXDLYALIGNRESET, -- RXDLYALIGNSWPPRECURB => tied_to_vcc_i, -- RXDLYALIGNUPDSW => tied_to_ground_i, -- RXENPMAPHASEALIGN => i_mgt.rx.RXENPMAPHASEALIGN, --RXENPMAPHASEALIGN_IN, RXPMASETPHASE => i_mgt.rx.RXPMASETPHASE, --RXPMASETPHASE_IN, RXSTATUS => open, --------------- Receive Ports - RX Loss-of-sync State Machine -------------- RXLOSSOFSYNC => o_mgt.rx.RXLOSSOFSYNC, -- ---------------------- Receive Ports - RX Oversampling --------------------- RXENSAMPLEALIGN => tied_to_ground_i, -- RXOVERSAMPLEERR => open, -- ------------------------ Receive Ports - RX PLL Ports ---------------------- GREFCLKRX => '0', -- GTXRXRESET => i_mgt.ctrl.GTXRESET, --GTXRXRESET_IN, MGTREFCLKRX => slv_mgtrefclk, --MGTREFCLKRX_IN, NORTHREFCLKRX => "00", -- PERFCLKRX => '0', -- PLLRXRESET => i_mgt.ctrl.PLLRXRESET, --PLLRXRESET_IN, RXPLLLKDET => o_mgt.ctrl.RXPLLLKDET , --RXPLLLKDET_OUT, RXPLLLKDETEN => '1', -- RXPLLPOWERDOWN => '0', -- RXPLLREFSELDY => "000", -- GREFCLKRX RXRATE => "00", -- RXRATEDONE => open, -- RXRESETDONE => o_mgt.ctrl.RXRESETDONE , --RXRESETDONE_OUT, SOUTHREFCLKRX => "00", -- -------------- Receive Ports - RX Pipe Control for PCI Express ------------- -- PHYSTATUS => open, -- RXVALID => open, -- ----------------- Receive Ports - RX Polarity Control Ports ---------------- -- RXPOLARITY => tied_to_ground_i, -- --------------------- Receive Ports - RX Ports for SATA -------------------- -- COMINITDET => open, -- COMSASDET => open, -- COMWAKEDET => open, -- ---------------------------------------------------------------------------- ------------- Shared Ports - Dynamic Reconfiguration Port (DRP) ------------ -- ---------------------------------------------------------------------------- DADDR => tied_to_ground_vec_i(7 downto 0), -- DCLK => tied_to_ground_i, -- DEN => tied_to_ground_i, -- DI => tied_to_ground_vec_i(15 downto 0), -- DRDY => open, -- DRPDO => open, -- DWE => tied_to_ground_i, -- ---------------------------------------------------------------------------- -------------- Transmit Ports - 64b66b and 64b67b Gearbox Ports ------------ ---------------------------------------------------------------------------- TXGEARBOXREADY => open, -- TXHEADER => tied_to_ground_vec_i(2 downto 0), -- TXSEQUENCE => tied_to_ground_vec_i(6 downto 0), -- TXSTARTSEQ => tied_to_ground_i, -- ---------------- Transmit Ports - 8b10b Encoder Control Ports -------------- TXBYPASS8B10B => i_mgt.tx.TXBYPASS8B10B, --tied_to_ground_vec_i(3 downto 0), TXCHARDISPMODE => i_mgt.tx.TXCHARDISPMODE, --txchardispmode_i, TXCHARDISPVAL => i_mgt.tx.TXCHARDISPVAL , --txchardispval_i, TXCHARISK => i_mgt.tx.TXCHARISK , --tied_to_ground_vec_i(3 downto 0), TXENC8B10BUSE => '1', --tied_to_ground_i, TXKERR => o_mgt.tx.TXKERR , --open, TXRUNDISP => o_mgt.tx.TXRUNDISP, --open, ------------------------- Transmit Ports - GTX Ports ----------------------- GTXTEST => "1000000000000", -- MGTREFCLKFAB => debug_refclk, -- TSTCLK0 => tied_to_ground_i, -- TSTCLK1 => tied_to_ground_i, -- TSTIN => "11111111111111111111", -- TSTOUT => open, -- ------------------ Transmit Ports - TX Data Path interface ----------------- TXDATA => i_mgt.tx.TXDATA, --txdata_i, TXOUTCLK => o_mgt.tx.TXOUTCLK, --TXOUTCLK_OUT, TXOUTCLKPCS => open, -- TXRESET => i_mgt.tx.TXRESET, --tied_to_ground_i, TXUSRCLK => i_mgt.tx.TXUSRCLK, --tied_to_ground_i, TXUSRCLK2 => i_mgt.tx.TXUSRCLK2, --TXUSRCLK2_IN, ---------------- Transmit Ports - TX Driver and OOB signaling -------------- TXBUFDIFFCTRL => "100", -- TXDIFFCTRL => i_mgt.tx.TXDIFFCTRL, --TXDIFFCTRL_IN, TXINHIBIT => tied_to_ground_i, -- TXN => o_mgt.tx.TXP, --TXN_OUT, TXP => o_mgt.tx.TXN, --TXP_OUT, TXPOSTEMPHASIS => i_mgt.tx.TXPOSTEMPHASIS, --TXPOSTEMPHASIS_IN, --------------- Transmit Ports - TX Driver and OOB signalling -------------- TXPREEMPHASIS => i_mgt.tx.TXPREEMPHASIS, --TXPREEMPHASIS_IN, ----------- Transmit Ports - TX Elastic Buffer and Phase Alignment --------- TXBUFSTATUS => open, -------- Transmit Ports - TX Elastic Buffer and Phase Alignment Ports ------ TXDLYALIGNDISABLE => tied_to_vcc_i, -- TXDLYALIGNMONENB => tied_to_ground_i, -- TXDLYALIGNMONITOR => open, -- TXDLYALIGNOVERRIDE => tied_to_ground_i, -- TXDLYALIGNRESET => tied_to_ground_i, -- TXDLYALIGNUPDSW => tied_to_vcc_i, -- TXENPMAPHASEALIGN => tied_to_ground_i, -- TXPMASETPHASE => tied_to_ground_i, -- ----------------------- Transmit Ports - TX PLL Ports ---------------------- GREFCLKTX => '0', -- GTXTXRESET => i_mgt.ctrl.GTXRESET, --GTXTXRESET_IN, MGTREFCLKTX => slv_mgtrefclk, --MGTREFCLKTX_IN, NORTHREFCLKTX => "00", -- PERFCLKTX => '0', -- PLLTXRESET => i_mgt.ctrl.PLLTXRESET, --PLLTXRESET_IN, SOUTHREFCLKTX => "00", -- TXPLLLKDET => o_mgt.ctrl.TXPLLLKDET, --TXPLLLKDET_OUT, TXPLLLKDETEN => '1', -- TXPLLPOWERDOWN => '0', -- TXPLLREFSELDY => "000", -- TXRATE => "00", -- TXRATEDONE => open, -- TXRESETDONE => o_mgt.ctrl.TXRESETDONE, --TXRESETDONE_OUT, --------------------- Transmit Ports - TX PRBS Generator ------------------- -- TXENPRBSTST => tied_to_ground_vec_i(2 downto 0), -- TXPRBSFORCEERR => tied_to_ground_i, -- -------------------- Transmit Ports - TX Polarity Control ------------------ -- TXPOLARITY => tied_to_ground_i, -- ----------------- Transmit Ports - TX Ports for PCI Express ---------------- -- TXDEEMPH => tied_to_ground_i, -- TXDETECTRX => tied_to_ground_i, -- TXELECIDLE => tied_to_ground_i, -- TXMARGIN => tied_to_ground_vec_i(2 downto 0), -- TXPDOWNASYNCH => tied_to_ground_i, -- TXSWING => tied_to_ground_i, -- --------------------- Transmit Ports - TX Ports for SATA ------------------- -- COMFINISH => open, -- TXCOMINIT => tied_to_ground_i, -- TXCOMSAS => tied_to_ground_i, -- TXCOMWAKE => tied_to_ground_i -- ); end RTL;