Typo in MGT data lines instantiation #3

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2020-10-22T09:09:32+02:00

bucher_p1 commented

2020-10-22 09:09:32 +02:00

(Migrated from git.psi.ch)

Mail von Till 19-10-2020:
I have noticed that the RXN/RXP, TXN/TXP polarities are swapped in

https://git.psi.ch/GFA/Libraries/Firmware/VHDL/evr320/blob/master/hdl/v6vlx_gtxe1_142MHz8_2Gbps856.vhd#L355
https://git.psi.ch/GFA/Libraries/Firmware/VHDL/evr320/blob/master/hdl/v6vlx_gtxe1_142MHz8_2Gbps856.vhd#L444
https://git.psi.ch/GFA/Libraries/Firmware/VHDL/evr320/blob/master/hdl/v6vlx_gtxe1_101MHz27_1Gbps0127.vhd#L355
https://git.psi.ch/GFA/Libraries/Firmware/VHDL/evr320/blob/master/hdl/v6vlx_gtxe1_101MHz27_1Gbps0127.vhd#L444

is there a particular reason for this?

Thanks

Till

Hi Till,

I have never noticed it.
Luckily, it is not affecting the functionality. The data lines only need to be pulled to the top for ISE to set the location of the MGT (or use a ucf constraint).
The functionality is fix in hardware and must be correct in the schematic. I will correct the typo.
btw, this is similar with the reference clock, unless you select a reachable clock and map it to any clock ref input of the mgt, the tool takes care to which port (north, south, etc.) it has to go.

Thanks and best regards
Patric

Mail von Till 19-10-2020: I have noticed that the RXN/RXP, TXN/TXP polarities are swapped in https://git.psi.ch/GFA/Libraries/Firmware/VHDL/evr320/blob/master/hdl/v6vlx_gtxe1_142MHz8_2Gbps856.vhd#L355 https://git.psi.ch/GFA/Libraries/Firmware/VHDL/evr320/blob/master/hdl/v6vlx_gtxe1_142MHz8_2Gbps856.vhd#L444 https://git.psi.ch/GFA/Libraries/Firmware/VHDL/evr320/blob/master/hdl/v6vlx_gtxe1_101MHz27_1Gbps0127.vhd#L355 https://git.psi.ch/GFA/Libraries/Firmware/VHDL/evr320/blob/master/hdl/v6vlx_gtxe1_101MHz27_1Gbps0127.vhd#L444 is there a particular reason for this? Thanks - Till --------------------- Hi Till, I have never noticed it. Luckily, it is not affecting the functionality. The data lines only need to be pulled to the top for ISE to set the location of the MGT (or use a ucf constraint). The functionality is fix in hardware and must be correct in the schematic. I will correct the typo. btw, this is similar with the reference clock, unless you select a reachable clock and map it to any clock ref input of the mgt, the tool takes care to which port (north, south, etc.) it has to go. Thanks and best regards Patric

bucher_p1 commented

2020-10-22 09:10:32 +02:00

(Migrated from git.psi.ch)

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Reference: AEK_8220_Libraries/firmware_vhdl_evr320#3