The latency counter should be reset when reading from (64-bit) register #7. However, I observed that the counter was also reset when reading from register #6. This is due to a bug in TOSCA2's xuser/TMEM interface, see here.
The latency counter should be reset when reading from (64-bit) register #7. However, I observed that the counter was also reset when reading from register #6. This is due to a bug in TOSCA2's xuser/TMEM interface, [see here](https://git.psi.ch/GFA/Libraries/BoardSupport/IFC1210/tosca2/issues/13).
Blocking a user prevents them from interacting with repositories, such as opening or commenting on pull requests or issues. Learn more about blocking a user.
The latency counter should be reset when reading from (64-bit) register #7. However, I observed that the counter was also reset when reading from register #6. This is due to a bug in TOSCA2's xuser/TMEM interface, see here.