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Latency counter is reset "mysteriously" #2

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opened 2020-10-04 16:06:00 +02:00 by straumann_t · 0 comments
straumann_t commented 2020-10-04 16:06:00 +02:00 (Migrated from git.psi.ch)
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The latency counter should be reset when reading from (64-bit) register #7. However, I observed that the counter was also reset when reading from register #6. This is due to a bug in TOSCA2's xuser/TMEM interface, see here.

The latency counter should be reset when reading from (64-bit) register #7. However, I observed that the counter was also reset when reading from register #6. This is due to a bug in TOSCA2's xuser/TMEM interface, [see here](https://git.psi.ch/GFA/Libraries/BoardSupport/IFC1210/tosca2/issues/13).
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Reference: AEK_8220_Libraries/firmware_vhdl_evr320#2
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