EVR STABLE: add generic to discard for hipa this statement EVR STABLE

hdl/evr320_decoder.vhd

@@ -24,8 +24,10 @@ use work.evr320_pkg.all;
 entity evr320_decoder is
    generic
    (
+      FACILITY                    : string  := "SFEL";      -- "HIPA" | "SFEL"
       EVENT_RECORDER              : boolean := false;
-      MEM_DATA_WIDTH              : integer := 32
+      MEM_DATA_WIDTH              : integer := 32;
+      EXP_REC_CLK_FREQ            : natural := 142_800_000  -- in Hz 
    );
    port
    (
@@ -73,6 +75,7 @@ architecture behavioral of evr320_decoder is
    -----------------------------------------------------------------------------
    -- Constant
    -----------------------------------------------------------------------------
+   --
    constant HIGH                  : std_logic := '1';
    constant LOW                   : std_logic := '0';
    constant LOW_slv               : std_logic_vector(15 downto  0) := (others => '0');
@@ -221,7 +224,9 @@ architecture behavioral of evr320_decoder is
 --   attribute fsm_safe_state : string;
 --   attribute fsm_safe_state of frame_fsm      : signal is "default_state";
 --   attribute fsm_safe_state of mem_fsm        : signal is "default_state";
-
+  
+   constant evr_stable_time_int_c : natural := EXP_REC_CLK_FREQ/100;
+   constant evr_stable_time_slv_c : std_logic_vector(cs_timeout_cnt'range):= std_logic_vector(to_unsigned(evr_stable_time_int_c, cs_timeout_cnt'length));
 begin
 
    -----------------------------------------------------------------------------
@@ -230,9 +235,10 @@ begin
    debug_clk                      <= i_mgt_rx_clk;
    debug( 15 downto   0)          <= i_mgt_rx_data;
    debug( 17 downto  16)          <= i_mgt_rx_charisk;
-   debug( 23 downto  18)          <= (others=>'0');
+   debug(18)                      <= evr_stable;--new
-   debug( 31 downto  24)          <= (others => '0');
+   debug(26 downto 19)            <= i_evr_params.event_numbers(1);
-   debug( 35 downto  32)          <= "0001" when (frame_fsm = frame_idle    ) else
+   debug(34 downto 27)            <= i_evr_params.event_numbers(2);
+   debug(38 downto  35)          <= "0001" when (frame_fsm = frame_idle    ) else
                                      "0010" when (frame_fsm = frame_addr_gap) else
                                      "0011" when (frame_fsm = frame_addr    ) else
                                      "0100" when (frame_fsm = frame_data_gap) else
@@ -242,7 +248,7 @@ begin
                                      "1000" when (frame_fsm = frame_chk2_gap) else
                                      "1001" when (frame_fsm = frame_chk2    ) else
                                      "0000";
-   debug( 39 downto  36)          <= (others => '0');
+   debug( 39)                     <=  '0';
    debug( 40)                     <= usr_events( 0)( 3);
    debug( 41)                     <= usr_events( 1)( 3);
    debug( 42)                     <= usr_events( 2)( 3);
@@ -267,7 +273,7 @@ begin
    end generate dbg_evt_rec;
 
    dbg_no_evt_rec: if not(EVENT_RECORDER) generate
-      debug(127 downto  64)       <= (others => '0');
+      
    end generate dbg_no_evt_rec;
    
 
@@ -289,6 +295,7 @@ begin
    
    -----------------------------------------------------------------------------
    -- evr stable state
+   -- TODO: Perform the sync according to k28.5
    -----------------------------------------------------------------------------
    prc_evr_stable : process(i_mgt_rx_clk)
    begin
@@ -296,9 +303,9 @@ begin
          if (i_mgt_rst = '1') then
             evr_stable            <= '0';
          else
-            if ((std_logic_vector(cs_min_cnt) > i_evr_params.cs_min_cnt) and 
+            if ((std_logic_vector(cs_min_cnt) > i_evr_params.cs_min_cnt)    and 
-                (std_logic_vector(cs_min_time) > i_evr_params.cs_min_time) and 
+                (std_logic_vector(cs_min_time) > i_evr_params.cs_min_time)  and 
-                (std_logic_vector(cs_timeout_cnt) < X"15CA20")) then
+                (std_logic_vector(cs_timeout_cnt) < evr_stable_time_slv_c)) then -- make generics depending on recovery_clock
                evr_stable      <= '1';
             else
                evr_stable      <= '0';
@@ -317,13 +324,21 @@ begin
          if (i_mgt_rst = '1') then
             usr_events            <= (others => (others => '0'));
          else
-            for i in 0 to 3 loop
+           for i in 0 to 3 loop
-               if ((i_evr_params.event_enable(i) = '1') and (i_mgt_rx_charisk( 0) = '0') and (i_mgt_rx_data( 7 downto  0) = i_evr_params.event_numbers(i)) and (evr_stable = '1')) then
+           if FACILITY = "HIPA" then
+              if ((i_evr_params.event_enable(i) = '1') and (i_mgt_rx_charisk( 0) = '0') and (i_mgt_rx_data( 7 downto  0) = i_evr_params.event_numbers(i))) then
                   usr_events(i)   <= "1111";
                else
                   usr_events(i)   <= usr_events(i)( 2 downto  0) & '0';
                end if;
-            end loop;
+          else
+            if ((i_evr_params.event_enable(i) = '1') and (i_mgt_rx_charisk( 0) = '0') and (i_mgt_rx_data( 7 downto  0) = i_evr_params.event_numbers(i))and (evr_stable = '1')) then
+                  usr_events(i)   <= "1111";
+               else
+                  usr_events(i)   <= usr_events(i)( 2 downto  0) & '0';
+               end if;
+           end if;
+           end loop;
          end if;
       end if;
    end process;

hdl/evr320_ifc1210_wrapper.vhd

@@ -53,6 +53,9 @@ entity evr320_ifc1210_wrapper is
     mgt_tx_p         : out std_logic;   -- MGT TX P
     mgt_status_o     : out std_logic_vector(31 downto 0); -- MGT Status
     mgt_control_i    : in  std_logic_vector(31 downto 0); -- MGT Control      
+    mgt_rx_data_o    : out std_logic_Vector(15 downto 0); -- for debug purpose
+    mgt_rx_charisk_o : out std_logic_vector(1 downto 0);  -- for debug purpose
+    
     ---------------------------------------------------------------------------
     -- User interface MGT clock
     ---------------------------------------------------------------------------
@@ -163,8 +166,10 @@ begin
   -- --------------------------------------------------------------------------
   evr320_decoder_inst : entity work.evr320_decoder
     generic map(
-      EVENT_RECORDER => g_EVENT_RECORDER,
+      FACILITY          => g_FACILITY,
-      MEM_DATA_WIDTH => c_TOSCA2_DATA_WIDTH)
+      EVENT_RECORDER    => g_EVENT_RECORDER,
+      MEM_DATA_WIDTH    => c_TOSCA2_DATA_WIDTH,
+      EXP_REC_CLK_FREQ  => 50_632_820)
     port map(
       -- Debug interface
       debug_clk             => debug_clk,
@@ -219,7 +224,8 @@ begin
       o_mgt_rx_data    => mgt_rx_data,
       o_mgt_rx_charisk => mgt_rx_charisk
     );
-
+   mgt_rx_charisk_o <= mgt_rx_charisk;
+   mgt_rx_data_o    <= mgt_rx_data;
   -- --------------------------------------------------------------------------
   -- TMEM 
   -- -------------------------------------------------------------------------- 
@@ -277,7 +283,7 @@ begin
     signal event_nr_sync, event_nr : std_logic_vector(7 downto 0);
     signal event_detected          : std_logic_vector(3 downto 0);
     signal event_detected_sync     : std_logic_vector(1 downto 0);
-    constant MAX_COUNT             : unsigned(31 downto 0) := to_unsigned(g_XUSER_CLK_FREQ / 100, 32); -- MAX 10ms
+    constant MAX_COUNT             : unsigned(31 downto 0) := to_unsigned(g_XUSER_CLK_FREQ / 10, 32); -- MAX 100ms ~ 10Hz
   begin
 
     -- Process: filter events for matching event_nr register:
@@ -337,23 +343,14 @@ begin
   -- Add delay output
   -- --------------------------------------------------------------------------
   output_delay_block : block
-    signal rst0_s, rst1_s      : std_logic; -- double stage sync for reset
+    --signal rst0_s, rst1_s      : std_logic; -- double stage sync for reset
     signal usr_evt_shaped_s    : std_logic_vector(4 downto 0);
     signal usr_events_adj_s    : std_logic_vector(4 downto 0);
     signal usr_events_concat_s : std_logic_vector(4 downto 0);
 
   begin
-    --*** double stage sync for reset ***--
+    
-    proc_rst : process(clk_evr)
+    evr_rst_s           <= mgt_status(15); -- RXLOSSOFSYNC
-    begin
-      if rising_edge(clk_evr) then
-        rst0_s <= xuser_RESET;
-        rst1_s <= rst0_s;
-      end if;
-    end process;
-
-    evr_rst_s <= rst1_s;
-
     usr_events_concat_s <= usr_events_s & sos_event_s;
 
     gene_adj_out : for i in 0 to 4 generate
@@ -366,7 +363,7 @@ begin
                     MaxDuration_g => MaxDuration_c,
                     RstPol_g      => '1')
         port map(clk_i   => clk_evr,
-                 rst_i   => rst1_s,
+                 rst_i   => evr_rst_s,
                  width_i => usr_event_width_s(i),
                  hold_i  => (others => '0'),
                  dat_i   => usr_events_concat_s(i),
@@ -380,7 +377,7 @@ begin
                     RamBehavior_g   => "RBW",
                     Hold_g          => True)
         port map( clk_i => clk_evr,
-                  rst_i => rst1_s,
+                  rst_i => evr_rst_s,
                   dat_i(0) => usr_evt_shaped_s(i),
                   str_i => '1',
                   del_i => usr_event_delay_s(i),

hdl/evr320_tmem.vhd

@@ -131,6 +131,7 @@ begin
   lat_counter_val       <= evr_latency_measure_stat_i.counter_val;
   
   -- --------------------------------------------------------------------------
+  -- TODO: proper CDC
   -- Synchronisation to xuser_CLK                                                      
   -- --------------------------------------------------------------------------
   prc_sync_xuser: process (xuser_CLK)
@@ -295,10 +296,9 @@ begin
   -- --------------------------------------------------------------------------
   mem_clk_o                   <= xuser_CLK;
   mem_addr_o                  <= std_logic_vector(unsigned(xuser_TMEM_ADD) - unsigned(MEM_ADDR_START));
-  evr_params_o                <= (event_numbers, event_enable, cs_min_cnt, cs_min_time);
+  --event recorder had to be also added to cdc
   evr_evt_rec_control_o       <= (er_event_number, er_event_enable, er_data_ack(3), er_error_ack(3));
   mgt_reset_o                 <= mgt_reset;
-  evr_latency_measure_ctrl_o  <= (lat_event_nr, lat_counter_arm);
 
   -- --------------------------------------------------------------------------
   -- add CDC output
@@ -347,6 +347,55 @@ begin
     evr_pulse_width_o(3) <= output_s(143 downto 128);
     evr_pulse_width_o(4) <= output_s(159 downto 144);
   end block;
+  
+  block_cdc_evr_code_param : block
+    signal input_s, output_s : std_logic_vector(108 downto 0);
+  begin
+    -- ------------------------------------------------------------------------
+    -- Assemble Input
+    -- ------------------------------------------------------------------------
+    --** event  numbers **
+    input_s( 7 downto 0)     <= event_numbers(0);
+    input_s(15 downto 8)     <= event_numbers(1);
+    input_s(23 downto 16)    <= event_numbers(2);
+    input_s(31 downto 24)    <= event_numbers(3);
+    --** event pulse enable **
+    input_s(35 downto 32)    <= event_enable;
+    --** time counter **
+    input_s(67 downto 36)    <= cs_min_time;
+    input_s(99 downto 68)    <= cs_min_cnt;
+    --** latency counter **
+    input_s(100)             <= lat_counter_arm;
+    input_s(108 downto 101)  <= lat_event_nr;
+
+    -- Instance
+    inst_cdc_fast_stat : entity work.psi_common_status_cc
+      generic map(DataWidth_g => input_s'length)
+      port map(ClkA   => xuser_CLK,
+              RstInA  => xuser_RESET,
+              RstOutA => open,
+              DataA   => input_s,
+              ClkB    => evr_clk_i,
+              RstInB  => evr_rst_i,
+              RstOutB => open,
+              DataB   => output_s);
+    -- ------------------------------------------------------------------------
+    -- Disassemble Output
+    -- ------------------------------------------------------------------------
+    --** event  numbers **
+    evr_params_o.event_numbers(0) <=  output_s( 7 downto 0) ;  
+    evr_params_o.event_numbers(1) <=  output_s(15 downto 8) ;  
+    evr_params_o.event_numbers(2) <=  output_s(23 downto 16);  
+    evr_params_o.event_numbers(3) <=  output_s(31 downto 24);  
+    --** event pulse enable **                         
+    evr_params_o.event_enable     <=  output_s(35 downto 32);
+    --** time counter **
+    evr_params_o.cs_min_time      <=  output_s(67 downto 36); 
+    evr_params_o.cs_min_cnt       <=  output_s(99 downto 68);  
+    --** latency counter **
+    evr_latency_measure_ctrl_o.counter_arm  <= output_s(100)            ;
+    evr_latency_measure_ctrl_o.event_nr     <= output_s(108 downto 101) ;
+  end block;                                                            
 
 end rtl;
 -- ----------------------------------------------------------------------------

hdl/v6vlx_gtxe1_101MHz27_1Gbps0127.vhd

@@ -7,7 +7,7 @@
 --         : Patric Bucher, Section DSV
 -- Version : $Revision: 1.1 $
 ------------------------------------------------------------------------------
--- Copyright© PSI, Section Diagnostic
+-- Copyright<EFBFBD> PSI, Section Diagnostic
 ------------------------------------------------------------------------------
 -- Comment : Virtex-6 GTXE1 primitive configured for HIPA 50.63282 MHz
 ------------------------------------------------------------------------------
@@ -384,7 +384,7 @@ begin
       RXPLLLKDET                      =>      o_mgt.ctrl.RXPLLLKDET ,                         --RXPLLLKDET_OUT,
       RXPLLLKDETEN                    =>      '1',                                            --
       RXPLLPOWERDOWN                  =>      '0',                                            --
-      RXPLLREFSELDY                   =>      "000",                                          -- GREFCLKRX
+      RXPLLREFSELDY                   =>      "000",                                          --GREFCLKRX
       RXRATE                          =>      "00",                                           --
       RXRATEDONE                      =>      open,                                           --
       RXRESETDONE                     =>      o_mgt.ctrl.RXRESETDONE ,                        --RXRESETDONE_OUT,

hdl/v6vlx_gtxe1_wrapper.vhd

@@ -7,7 +7,7 @@
 --         : Patric Bucher, Section DSV
 -- Version : $Revision: 1.1 $
 ------------------------------------------------------------------------------
--- Copyright© PSI, Section Diagnostic
+-- Copyright<EFBFBD> PSI, Section Diagnostic
 ------------------------------------------------------------------------------
 -- Comment : Wrapper vor Virtex-6 GTX ready to use in HIPA and SwissFEL (SFEL)
 ------------------------------------------------------------------------------
@@ -137,8 +137,8 @@ begin
   o_mgt_status(16)             <= sl_rx0_slide;
   o_mgt_status(17)             <= sl_gtxe_rx_sync_done;
   o_mgt_status(19 downto 18)   <= o_mgt.rx.RXNOTINTABLE(1 downto 0);  -- Byte 1 + Byte 0
-  o_mgt_status(21 downto 20)   <= o_mgt.rx.RXDISPERR(1 downto 0);     -- Byte 1 + Byte 0
+  o_mgt_status(23 downto 20)   <= o_mgt.rx.RXDISPERR(3 downto 0);     -- Byte 1 + Byte 0
-  o_mgt_status(31 downto 22)   <= B"00_0000_0000";                    -- undefined
+  o_mgt_status(31 downto 24)   <= B"0000_0000";                    -- undefined
   
 
   -- GTXE RX IF ---------------------------------------------------------------------