AEK_8220_Libraries/firmware_vhdl_evr320
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Updated to the newest libraries

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This commit is contained in:
koprek_w
2023-09-11 11:28:47 +02:00
parent 5bf9caae3a
commit 4826a093f4
3 changed files with 2033 additions and 2012 deletions
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99
hdl/evr320_decoder.vhd
View File

@ -24,8 +24,10 @@ use work.evr320_pkg.all;
entity evr320_decoder is
generic
(
FACILITY : string := "SFEL"; -- "HIPA" | "SFEL"
EVENT_RECORDER : boolean := false;
MEM_DATA_WIDTH : integer := 32
MEM_DATA_WIDTH : integer := 32;
EXP_REC_CLK_FREQ : natural := 142_800_000 -- in Hz
);
port
(
@ -73,6 +75,7 @@ architecture behavioral of evr320_decoder is
-----------------------------------------------------------------------------
-- Constant
-----------------------------------------------------------------------------
--
constant HIGH : std_logic := '1';
constant LOW : std_logic := '0';
constant LOW_slv : std_logic_vector(15 downto 0) := (others => '0');
@ -180,7 +183,6 @@ architecture behavioral of evr320_decoder is
signal mem_data_wren : std_logic := '0';
signal mem_data_wr_addr : std_logic_vector(10 downto 0) := (others => '0');
signal mem_data_wr_byte : std_logic_vector( 7 downto 0) := (others => '0');
signal mem_data : std_logic_vector(11+8-1 downto 0);
-- Data memory read
signal mem_data_dpram : std_logic_vector(MEM_DATA_WIDTH - 1 downto 0) := (others => '0');
signal mem_data_event0 : std_logic_vector(MEM_DATA_WIDTH - 1 downto 0) := (others => '0');
@ -223,6 +225,8 @@ architecture behavioral of evr320_decoder is
-- attribute fsm_safe_state of frame_fsm : signal is "default_state";
-- attribute fsm_safe_state of mem_fsm : signal is "default_state";
constant evr_stable_time_int_c : natural := EXP_REC_CLK_FREQ/100;
constant evr_stable_time_slv_c : std_logic_vector(cs_timeout_cnt'range):= std_logic_vector(to_unsigned(evr_stable_time_int_c, cs_timeout_cnt'length));
begin
-----------------------------------------------------------------------------
@ -231,9 +235,10 @@ begin
debug_clk <= i_mgt_rx_clk;
debug( 15 downto 0) <= i_mgt_rx_data;
debug( 17 downto 16) <= i_mgt_rx_charisk;
debug( 23 downto 18) <= (others=>'0');
debug( 31 downto 24) <= (others => '0');
debug( 35 downto 32) <= "0001" when (frame_fsm = frame_idle ) else
debug(18) <= evr_stable;--new
debug(26 downto 19) <= i_evr_params.event_numbers(1);
debug(34 downto 27) <= i_evr_params.event_numbers(2);
debug(38 downto 35) <= "0001" when (frame_fsm = frame_idle ) else
"0010" when (frame_fsm = frame_addr_gap) else
"0011" when (frame_fsm = frame_addr ) else
"0100" when (frame_fsm = frame_data_gap) else
@ -243,7 +248,7 @@ begin
"1000" when (frame_fsm = frame_chk2_gap) else
"1001" when (frame_fsm = frame_chk2 ) else
"0000";
debug( 39 downto 36) <= (others => '0');
debug( 39) <= '0';
debug( 40) <= usr_events( 0)( 3);
debug( 41) <= usr_events( 1)( 3);
debug( 42) <= usr_events( 2)( 3);
@ -268,7 +273,7 @@ begin
end generate dbg_evt_rec;
dbg_no_evt_rec: if not(EVENT_RECORDER) generate
debug(127 downto 64) <= (others => '0');
end generate dbg_no_evt_rec;
@ -290,6 +295,7 @@ begin
-----------------------------------------------------------------------------
-- evr stable state
-- TODO: Perform the sync according to k28.5
-----------------------------------------------------------------------------
prc_evr_stable : process(i_mgt_rx_clk)
begin
@ -297,9 +303,9 @@ begin
if (i_mgt_rst = '1') then
evr_stable <= '0';
else
if ((std_logic_vector(cs_min_cnt) > i_evr_params.cs_min_cnt) and
(std_logic_vector(cs_min_time) > i_evr_params.cs_min_time) and
(std_logic_vector(cs_timeout_cnt) < X"15CA20")) then
if ((std_logic_vector(cs_min_cnt) > i_evr_params.cs_min_cnt) and
(std_logic_vector(cs_min_time) > i_evr_params.cs_min_time) and
(std_logic_vector(cs_timeout_cnt) < evr_stable_time_slv_c)) then -- make generics depending on recovery_clock
evr_stable <= '1';
else
evr_stable <= '0';
@ -318,13 +324,21 @@ begin
if (i_mgt_rst = '1') then
usr_events <= (others => (others => '0'));
else
for i in 0 to 3 loop
if ((i_evr_params.event_enable(i) = '1') and (i_mgt_rx_charisk( 0) = '0') and (i_mgt_rx_data( 7 downto 0) = i_evr_params.event_numbers(i)) and (evr_stable = '1')) then
for i in 0 to 3 loop
if FACILITY = "HIPA" then
if ((i_evr_params.event_enable(i) = '1') and (i_mgt_rx_charisk( 0) = '0') and (i_mgt_rx_data( 7 downto 0) = i_evr_params.event_numbers(i))) then
usr_events(i) <= "1111";
else
usr_events(i) <= usr_events(i)( 2 downto 0) & '0';
end if;
end loop;
else
if ((i_evr_params.event_enable(i) = '1') and (i_mgt_rx_charisk( 0) = '0') and (i_mgt_rx_data( 7 downto 0) = i_evr_params.event_numbers(i))and (evr_stable = '1')) then
usr_events(i) <= "1111";
else
usr_events(i) <= usr_events(i)( 2 downto 0) & '0';
end if;
end if;
end loop;
end if;
end if;
end process;
@ -710,9 +724,6 @@ begin
mem_data_wr_addr <= frame_data_rd_addr;
mem_data_wr_byte <= frame_data_rd_byte;
-- concatenate - this avoids an internal error in ghdl v0.37!
mem_data <= mem_data_wr_addr & mem_data_wr_byte;
-----------------------------------------------------------------------------
-- Address delay for read data mux
-----------------------------------------------------------------------------
@ -857,45 +868,45 @@ begin
-------------------------------------------------------------------------
strm_fifo_inst : entity work.psi_common_async_fifo
generic map (
Width_g => 11+8,
Depth_g => 2048,
AlmFullOn_g => false,
AlmFullLevel_g => 2,
AlmEmptyOn_g => false,
AlmEmptyLevel_g => 2,
RamStyle_g => "WBR",
RamBehavior_g => "block" -- auto, distributed
width_g => 11+8,
depth_g => 2048,
afull_on_g => false,
afull_lvl_g => 2,
aempty_on_g => false,
aempty_level_g => 2,
ram_style_g => "WBR",
ram_behavior_g => "block" -- auto, distributed
)
port map (
-- Control Ports
InClk => i_mgt_rx_clk,
InRst => i_mgt_rst,
OutClk => i_stream_clk,
OutRst => '0',
in_clk_i => i_mgt_rx_clk,
in_rst_i => i_mgt_rst,
out_clk_i => i_stream_clk,
out_rst_i => '0',
-- Input Data
InData => mem_data,
InVld => mem_data_wren,
InRdy => open,
in_dat_i => mem_data_wr_addr & mem_data_wr_byte,
in_vld_i => mem_data_wren,
in_rdy_o => open,
-- Output Data
OutData => stream_raw,
OutVld => o_stream_valid,
OutRdy => '1',
out_dat_o => stream_raw,
out_vld_o => o_stream_valid,
out_rdy_i => '1',
-- Input Status
InFull => open,
InEmpty => open,
InAlmFull => open,
InAlmEmpty => open,
InLevel => open,
in_full_o => open,
in_empty_o => open,
in_afull_o => open,
in_aempty_o => open,
in_lvl_o => open,
-- Output Status
OutFull => open,
OutEmpty => open,
OutAlmFull => open,
OutAlmEmpty => open,
OutLevel => open
out_full_o => open,
out_empty_o => open,
out_afull_o => open,
out_aempty_o => open,
out_lvl_o => open
);
o_stream_data <= stream_raw(7 downto 0);

89
hdl/evr320_ifc1210_wrapper.vhd
View File

@ -53,12 +53,15 @@ entity evr320_ifc1210_wrapper is
mgt_tx_p : out std_logic; -- MGT TX P
mgt_status_o : out std_logic_vector(31 downto 0); -- MGT Status
mgt_control_i : in std_logic_vector(31 downto 0); -- MGT Control
mgt_rx_data_o : out std_logic_Vector(15 downto 0); -- for debug purpose
mgt_rx_charisk_o : out std_logic_vector(1 downto 0); -- for debug purpose
---------------------------------------------------------------------------
-- User interface MGT clock
---------------------------------------------------------------------------
clk_evr_o : out std_logic; -- Recovered parallel clock from MGT
rst_evr_o : out std_logic; -- reset according to RX Loss of sync
usr_events_o : out std_logic_vector(3 downto 0); -- User defined event pulses with one clock cycles length & no delay
clk_evr_o : out std_logic; -- Recovered parallel clock from MGT
rst_evr_o : out std_logic; -- reset according to RX Loss of sync
usr_events_o : out std_logic_vector(3 downto 0); -- User defined event pulses with one clock cycles length & no delay
sos_event_o : out std_logic; -- Start-of-Sequence Event
usr_events_adj_o : out std_logic_vector(3 downto 0); -- User defined event pulses adjusted in delay & length
sos_events_adj_o : out std_logic; -- Start-of-Sequence adjusted in delay & length
@ -163,8 +166,10 @@ begin
-- --------------------------------------------------------------------------
evr320_decoder_inst : entity work.evr320_decoder
generic map(
EVENT_RECORDER => g_EVENT_RECORDER,
MEM_DATA_WIDTH => c_TOSCA2_DATA_WIDTH)
FACILITY => g_FACILITY,
EVENT_RECORDER => g_EVENT_RECORDER,
MEM_DATA_WIDTH => c_TOSCA2_DATA_WIDTH,
EXP_REC_CLK_FREQ => 50_632_820)
port map(
-- Debug interface
debug_clk => debug_clk,
@ -219,7 +224,8 @@ begin
o_mgt_rx_data => mgt_rx_data,
o_mgt_rx_charisk => mgt_rx_charisk
);
mgt_rx_charisk_o <= mgt_rx_charisk;
mgt_rx_data_o <= mgt_rx_data;
-- --------------------------------------------------------------------------
-- TMEM
-- --------------------------------------------------------------------------
@ -257,14 +263,14 @@ begin
-- --------------------------------------------------------------------------
clock_meas_inst : entity work.psi_common_clk_meas
generic map(
MasterFrequency_g => g_XUSER_CLK_FREQ,
MaxMeasFrequency_g => 150000000
master_frequency_g => g_XUSER_CLK_FREQ,
max_meas_frequency_g => 150000000
)
port map(
ClkMaster => xuser_CLK,
Rst => xuser_RESET,
ClkTest => clk_evr,
FrequencyHz => evr_frequency
clk_master_i => xuser_CLK,
rst_i => xuser_RESET,
clk_test_i => clk_evr,
frequency_hz_o => evr_frequency
);
-- --------------------------------------------------------------------------
@ -277,7 +283,7 @@ begin
signal event_nr_sync, event_nr : std_logic_vector(7 downto 0);
signal event_detected : std_logic_vector(3 downto 0);
signal event_detected_sync : std_logic_vector(1 downto 0);
constant MAX_COUNT : unsigned(31 downto 0) := to_unsigned(g_XUSER_CLK_FREQ / 100, 32); -- MAX 10ms
constant MAX_COUNT : unsigned(31 downto 0) := to_unsigned(g_XUSER_CLK_FREQ / 10, 32); -- MAX 100ms ~ 10Hz
begin
-- Process: filter events for matching event_nr register:
@ -327,8 +333,8 @@ begin
end if;
end case;
end if;
evr_latency_measure_stat.counter_val <= std_logic_vector(counter);
evr_latency_measure_stat.event_detected <= event_detected_sync(event_detected_sync'left);
end process;
end block;
@ -337,44 +343,27 @@ begin
-- Add delay output
-- --------------------------------------------------------------------------
output_delay_block : block
signal rst0_s, rst1_s : std_logic; -- double stage sync for reset
--signal rst0_s, rst1_s : std_logic; -- double stage sync for reset
signal usr_evt_shaped_s : std_logic_vector(4 downto 0);
signal usr_events_adj_s : std_logic_vector(4 downto 0);
signal usr_events_concat_s : std_logic_vector(4 downto 0);
signal mmcm_locked : std_logic;
signal rxpll_locked : std_logic;
signal evr_rst_in : std_logic;
begin
rxpll_locked <= mgt_status(1);
mmcm_locked <= mgt_status(2);
evr_rst_in <= xuser_RESET or (not rxpll_locked) or (not mmcm_locked);
--*** double stage sync for reset ***--
proc_rst : process(clk_evr)
begin
if rising_edge(clk_evr) then
rst0_s <= evr_rst_in;
rst1_s <= rst0_s;
end if;
end process;
evr_rst_s <= rst1_s;
evr_rst_s <= mgt_status(15); -- RXLOSSOFSYNC
usr_events_concat_s <= usr_events_s & sos_event_s;
gene_adj_out : for i in 0 to 4 generate
--*** Adjust pulse length in clk cycles EVENT 0,1,2,3 ***
inst_pulslength_evt0 : entity work.psi_common_pulse_shaper_cfg
generic map(HoldIn_g => false,
HoldOffEna_g => false,
MaxHoldOff_g => 10,
MaxDuration_g => MaxDuration_c,
RstPol_g => '1')
generic map(HoldIn_g => false,
hold_off_ena_g => false,
max_hold_off_g => 10,
max_duration_g => MaxDuration_c,
Rst_Pol_g => '1')
port map(clk_i => clk_evr,
rst_i => rst1_s,
rst_i => evr_rst_s,
width_i => usr_event_width_s(i),
hold_i => (others => '0'),
dat_i => usr_events_concat_s(i),
@ -382,17 +371,17 @@ begin
--*** delay adjust EVENT 0,1,2,3***
inst_adjdelay_evt0 : entity work.psi_common_delay_cfg
generic map(Width_g => 1,
MaxDelay_g => MaxDelay_c,
RStPol_g => '1',
RamBehavior_g => "RBW",
Hold_g => True)
port map( clk_i => clk_evr,
rst_i => rst1_s,
dat_i(0) => usr_evt_shaped_s(i),
str_i => '1',
del_i => usr_event_delay_s(i),
dat_o(0) => usr_events_adj_s(i));
generic map(width_g => 1,
max_delay_g => MaxDelay_c,
rst_pol_g => '1',
ram_behavior_g => "RBW",
hold_g => True)
port map(clk_i => clk_evr,
rst_i => evr_rst_s,
dat_i(0) => usr_evt_shaped_s(i),
vld_i => '1',
del_i => usr_event_delay_s(i),
dat_o(0) => usr_events_adj_s(i));
end generate;
usr_events_adj_o <= usr_events_adj_s(4 downto 1);

129
hdl/evr320_tmem.vhd
View File

@ -39,7 +39,7 @@ entity evr320_tmem is
evr_evt_rec_control_o : out typ_evt_rec_ctrl;
evr_latency_measure_stat_i : in typ_rec_latency_measure_stat;
evr_latency_measure_ctrl_o : out typ_rec_latency_measure_ctrl;
mgt_status_i : in std_logic_vector(31 downto 0) := (others=>'0');
mgt_status_i : in std_logic_vector(31 downto 0);
mgt_reset_o : out std_logic;
mem_clk_o : out std_logic;
mem_addr_o : out std_logic_vector(10 downto 0);
@ -103,15 +103,17 @@ architecture rtl of evr320_tmem is
-- latency measurement
signal lat_counter_arm : std_logic := '0';
signal lat_event_nr : std_logic_vector(7 downto 0) := c_SOS_EVENT_DEFAULT;
signal lat_event_nr : std_logic_vector(7 downto 0) := x"26"; -- default SOS event
signal lat_counter_val : std_logic_vector(31 downto 0) := (others=>'0');
signal lat_event_detected : std_logic_vector(7 downto 0);
signal lat_arm : std_logic := '0';
signal lat_arm_edge : std_logic_vector(1 downto 0) := (others=>'0');
-- signal evr_force : std_logic_vector(3 downto 0) := (others => '0');
-- signal evr_force_rd : std_logic_vector(3 downto 0) := (others => '0'); -- readback
-- signal evr_force_pulse : typ_arr4(3 downto 0) := (others => (others => '0'));
-- event pulse config
signal evr_puls_width_cfg_s : typ_arr_width :=(others => UsrEventWidthDefault_c);
signal evr_puls_delay_cfg_s : typ_arr_delay :=(others => (others => '0'));
signal evr_puls_width_cfg_s : typ_arr_width :=((others=>(others=>'0')));
signal evr_puls_delay_cfg_s : typ_arr_delay :=((others=>(others=>'0')));
-- ----------------------------------------------------------------------------
-- ----------------------------------------------------------------------------
@ -128,24 +130,8 @@ begin
er_control_concat <= X"0000" & er_event_number & bit2byte(er_event_enable);
lat_counter_val <= evr_latency_measure_stat_i.counter_val;
process (xuser_CLK)
begin
if rising_edge(xuser_CLK) then
-- edge detection of latency arm:
lat_arm_edge <= lat_arm_edge(0) & lat_arm;
lat_counter_arm <= lat_arm_edge(0) and not lat_arm_edge(1);
if (evr_latency_measure_stat_i.event_detected = '1') then
lat_event_detected <= (others=>'1');
end if;
if (lat_counter_arm = '1') then
lat_event_detected <= (others=>'0');
end if;
end if;
end process;
-- --------------------------------------------------------------------------
-- TODO: proper CDC
-- Synchronisation to xuser_CLK
-- --------------------------------------------------------------------------
prc_sync_xuser: process (xuser_CLK)
@ -172,23 +158,21 @@ begin
-- --------------------------------------------------------------------------
-- Read operation
-- --------------------------------------------------------------------------
blk_tmemrd : block
begin
read_tmem_evr: process(xuser_CLK)
begin
if (rising_edge(xuser_CLK)) then
lat_counter_arm <= '0';
if (xuser_TMEM_ENA_reg = '1') then
if (xuser_TMEM_ADD_reg(13 downto REG_ADDR_WIDTH) = c_LOW(13 downto REG_ADDR_WIDTH)) then
case xuser_TMEM_ADD_reg(REG_ADDR_MSB downto TMEM_ADDR_LSB) is
when X"0" => xuser_TMEM_DATR <= event_numbers_concat & X"0000" & mgt_status_evr; -- 64bit / ByteAddr 000
when X"1" => xuser_TMEM_DATR <= reserved(63 downto 32) & X"0000_00" & bit2byte(mgt_reset); -- 64bit / ByteAddr 008 --> 0x00C = not implemented in ifc1210
when X"2" => xuser_TMEM_DATR <= reserved(63 downto 32) & bit2byte(event_enable); -- 64bit / ByteAddr 010 --> 0x014 = Bit0 SW Trigger Event 0, Bit8 SW Trigger Event 1, ...
when X"2" => xuser_TMEM_DATR <= reserved(63 downto 32) & bit2byte(event_enable); -- 64bit / ByteAddr 010 --> 0x014 = Bit0 SW Trigger Event 0, Bit8 SW Trigger Event 1, ... evr_force
when X"3" => xuser_TMEM_DATR <= evr_frequency & reserved(31 downto 0); -- 64bit / ByteAddr 018 --> 0x018 = Implementation Options + c_EVR_Location_vec
when X"4" => xuser_TMEM_DATR <= cs_min_time & cs_min_cnt; -- 64bit / ByteAddr 020
when X"5" => xuser_TMEM_DATR <= reserved(63 downto 0); -- 64bit / ByteAddr 028
when X"6" => xuser_TMEM_DATR <= lat_counter_val & x"00" & lat_event_detected & X"00" & lat_event_nr; -- 64bit / ByteAddr 030
when X"7" => xuser_TMEM_DATR <= reserved(63 downto 32) & reserved(31 downto 0); -- 64bit / ByteAddr 038
when X"6" => xuser_TMEM_DATR <= lat_counter_val & X"000000" & lat_event_nr; -- 64bit / ByteAddr 030
when X"7" => xuser_TMEM_DATR <= reserved(63 downto 32) & lat_counter_val; lat_counter_arm <= '1'; -- 64bit / ByteAddr 038
when X"8" => xuser_TMEM_DATR <= er_handshake_status & er_control_concat; -- 64bit / ByteAddr 040
when X"9" => xuser_TMEM_DATR <= reserved(63 downto 32) & er_status.usr_events_counter; -- 64bit / ByteAddr 048
when X"A" => xuser_TMEM_DATR <= evr_puls_delay_cfg_s(4) & evr_puls_delay_cfg_s(3) & evr_puls_delay_cfg_s(2) & evr_puls_delay_cfg_s(1) ; -- 64bit / ByteAddr 050
@ -203,7 +187,6 @@ begin
end if;
end process;
end block;
-- --------------------------------------------------------------------------
-- Write operation - Byte control
@ -215,7 +198,6 @@ begin
-- default assignments
er_data_ack <= er_data_ack(2 downto 0) & '0';
er_error_ack <= er_error_ack(2 downto 0) & '0';
lat_arm <= '0';
if (xuser_TMEM_ENA_reg = '1' and xuser_TMEM_ADD_reg(13 downto REG_ADDR_WIDTH) = c_LOW(13 downto REG_ADDR_WIDTH)) then
@ -266,18 +248,7 @@ begin
-----------------------------------------------------------------------------------------------------------------
if xuser_TMEM_ADD_reg(6 downto 3) = X"6" then --ByteAddr 030 Latency Measurement
if xuser_TMEM_WE_reg(0) = '1' then lat_event_nr ( 7 downto 0) <= xuser_TMEM_DATW_reg( 7 downto 0); end if;
-- if xuser_TMEM_WE_reg(1) = '1' then -reserved- (15 downto 8) <= xuser_TMEM_DATW_reg(15 downto 8); end if;
-- if xuser_TMEM_WE_reg(2) = '1' then -reserved- (23 downto 16) <= xuser_TMEM_DATW_reg(23 downto 16); end if;
-- if xuser_TMEM_WE_reg(3) = '1' then -reserved- (31 downto 24) <= xuser_TMEM_DATW_reg(31 downto 24); end if;
-- if xuser_TMEM_WE_reg(4) = '1' then -reserved- ( 7 downto 0) <= xuser_TMEM_DATW_reg(39 downto 32); end if;
-- if xuser_TMEM_WE_reg(5) = '1' then -reserved- (15 downto 8) <= xuser_TMEM_DATW_reg(47 downto 40); end if;
-- if xuser_TMEM_WE_reg(6) = '1' then -reserved- (23 downto 16) <= xuser_TMEM_DATW_reg(55 downto 48); end if;
-- if xuser_TMEM_WE_reg(7) = '1' then -reserved- (31 downto 24) <= xuser_TMEM_DATW_reg(63 downto 56); end if;
end if;
-----------------------------------------------------------------------------------------------------------------
if xuser_TMEM_ADD_reg(6 downto 3) = X"7" then --ByteAddr 038 Latency Measurement
if xuser_TMEM_WE_reg(0) = '1' then lat_arm <= xuser_TMEM_DATW_reg(0); end if;
-- if xuser_TMEM_WE_reg(1) = '1' then -reserved- (15 downto 8) <= xuser_TMEM_DATW_reg(15 downto 8); end if;
-- if xuser_TMEM_WE_reg(1) = '1' then -reserved- (15 downto 8) <= xuser_TMEM_DATW_reg(15 downto 8); end if;
-- if xuser_TMEM_WE_reg(2) = '1' then -reserved- (23 downto 16) <= xuser_TMEM_DATW_reg(23 downto 16); end if;
-- if xuser_TMEM_WE_reg(3) = '1' then -reserved- (31 downto 24) <= xuser_TMEM_DATW_reg(31 downto 24); end if;
-- if xuser_TMEM_WE_reg(4) = '1' then -reserved- ( 7 downto 0) <= xuser_TMEM_DATW_reg(39 downto 32); end if;
@ -325,10 +296,9 @@ begin
-- --------------------------------------------------------------------------
mem_clk_o <= xuser_CLK;
mem_addr_o <= std_logic_vector(unsigned(xuser_TMEM_ADD) - unsigned(MEM_ADDR_START));
evr_params_o <= (event_numbers, event_enable, cs_min_cnt, cs_min_time);
--event recorder had to be also added to cdc
evr_evt_rec_control_o <= (er_event_number, er_event_enable, er_data_ack(3), er_error_ack(3));
mgt_reset_o <= mgt_reset;
evr_latency_measure_ctrl_o <= (lat_event_nr, lat_counter_arm);
-- --------------------------------------------------------------------------
-- add CDC output
@ -354,13 +324,13 @@ begin
-- Instance
inst_cdc_fast_stat : entity work.psi_common_status_cc
generic map(DataWidth_g => input_s'length)
port map(ClkA => xuser_CLK,
RstInA => xuser_RESET,
DataA => input_s,
ClkB => evr_clk_i,
RstInB => evr_rst_i,
DataB => output_s);
generic map(width_g => input_s'length)
port map(a_clk_i => xuser_CLK,
a_rst_i => xuser_RESET,
a_dat_i => input_s,
b_clk_i => evr_clk_i,
b_rst_i => evr_rst_i,
b_dat_o => output_s);
-- ------------------------------------------------------------------------
-- Disassemble Output
-- ------------------------------------------------------------------------
@ -378,5 +348,56 @@ begin
evr_pulse_width_o(4) <= output_s(159 downto 144);
end block;
end rtl;
block_cdc_evr_code_param : block
signal input_s, output_s : std_logic_vector(108 downto 0);
begin
-- ------------------------------------------------------------------------
-- Assemble Input
-- ------------------------------------------------------------------------
--** event numbers **
input_s( 7 downto 0) <= event_numbers(0);
input_s(15 downto 8) <= event_numbers(1);
input_s(23 downto 16) <= event_numbers(2);
input_s(31 downto 24) <= event_numbers(3);
--** event pulse enable **
input_s(35 downto 32) <= event_enable;
--** time counter **
input_s(67 downto 36) <= cs_min_time;
input_s(99 downto 68) <= cs_min_cnt;
--** latency counter **
input_s(100) <= lat_counter_arm;
input_s(108 downto 101) <= lat_event_nr;
-- Instance
inst_cdc_fast_stat : entity work.psi_common_status_cc
generic map(width_g => input_s'length)
port map(a_clk_i => xuser_CLK,
a_rst_i => xuser_RESET,
a_rst_o => open,
a_dat_i => input_s,
b_clk_i => evr_clk_i,
b_rst_i => evr_rst_i,
b_rst_o => open,
b_dat_o => output_s);
-- ------------------------------------------------------------------------
-- Disassemble Output
-- ------------------------------------------------------------------------
--** event numbers **
evr_params_o.event_numbers(0) <= output_s( 7 downto 0) ;
evr_params_o.event_numbers(1) <= output_s(15 downto 8) ;
evr_params_o.event_numbers(2) <= output_s(23 downto 16);
evr_params_o.event_numbers(3) <= output_s(31 downto 24);
--** event pulse enable **
evr_params_o.event_enable <= output_s(35 downto 32);
--** time counter **
evr_params_o.cs_min_time <= output_s(67 downto 36);
evr_params_o.cs_min_cnt <= output_s(99 downto 68);
--** latency counter **
evr_latency_measure_ctrl_o.counter_arm <= output_s(100) ;
evr_latency_measure_ctrl_o.event_nr <= output_s(108 downto 101) ;
end block;
end rtl;
-- ----------------------------------------------------------------------------
-- ////////////////////////////////////////////////////////////////////////////
-- ----------------------------------------------------------------------------